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OpenUVR: an Open-Source System Framework for Untethered Virtual Reality Applications 27

OpenUVR: an Open-Source System Framework for Untethered Virt...

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30th ieee international symposium on Software Reliability Engineering (ISSRE)

作者： Rohloff, Alec Allen, Zackary Lin, Kung-Min Okrend, Joshua Nie, Chengyi Liu, Yu-Chia Tseng, Hung-Wei Appl Res Associates Berkeley CA 94720 USA Red Hat Inc Berkeley CA USA Univ Calif Berkeley Berkeley CA 94720 USA Riverside Technol Inc Riverside CA USA SUNY Stony Brook Stony Brook NY 11794 USA Univ Calif Riverside Riverside CA 92521 USA

ISBN: (纸本)9781665403863

Advancements in heterogeneous computing technologies enable the significant potential of virtual reality (VR) applications. To offer the best user experience (UX), a system should adopt an untethered, wireless-network-based architecture to transfer VR content between the user and the content generator. However, modern wireless network technologies make implementing such an architecture challenging, as VR applications require superior video quality-with high resolution, high frame rates, and very low latency. this paper presents OpenUVR, an open-source framework that uses commodity hardware components to satisfy the demands of interactive, real-time VR applications. OpenUVR significantly improves UX through a redesign of the system stack and addresses the most time-sensitive issues associated with redundant memory copying in modern computing systems. OpenUVR presents a cross-layered VR datapath to avoid redundant data operations and computation among system components, OpenUVR customizes the network stack to eliminate unnecessary memory operations incurred by mismatching data formats in each layer, and OpenUVR uses feedback from mobile devices to remove memory buffers. Together, these modifications allow OpenUVR to reduce VR application delays to 14.32 ms, meeting the 20 ms minimum latency in avoiding motion sickness. As an open-source system that is fully compatible with commodity hardware, OpenUVR offers the research community an opportunity to develop, investigate, and optimize applications for untethered, high-performance VR architectures.

关键词： Wireless networks System performance Systems architecture computer architecture Virtual reality Hardware Real-time systems

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Low-Latency Modular Exponentiation for FPGAs 30

Low-Latency Modular Exponentiation for FPGAs

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ieee 30th international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Langhammer, Martin Gribok, Sergey Pasca, Bogdan Intel Corp Swindon Wilts England Intel Corp Santa Clara CA 95051 USA Intel Corp Paris France

ISBN: (纸本)9781665483322

Modular exponentiation, especially for very large integers of hundreds or thousands of bits, is a commonly used function in popular cryptosystems such as RSA. the complexity of this algorithm is partly driven by the very large word sizes, which require many - often millions - of primitive operations in a CPU implementation, or a large amount of logic when accelerated by an ASIC. FPGAs, with their many embedded DSP resources have started to be used as well. In almost all cases, the calculations have required multiple - occasionally many - clock cycles to complete. Recently, blockchain algorithms have required very low-latency implementations of modular multiplications, motivating new implementations and approaches. In this paper we show nine different high performance modular exponentiation for 1024-bit operands, using a 1024-bit modular multiplication as it's core. Rather than just showing a number of completed designs, our paper shows the evolution of architectures which lead to different resource mix options. this will allow the reader to apply the examples to different FPGA targets which may have differing ratios of logic, memory, and embedded DSP blocks. In one design, we show a 1024b modular multiplier requiring 83K ALMs and 2372 DSPs, with a delay of 21.21ns.

关键词： Costs computer architecture Delays Complexity theory Blockchains Low latency communication Field programmable gate arrays

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FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation 66

FPGA-Based Hardware-in-the-Loop Real-Time Simulation Impleme...

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2023 ieee 66th international Midwest symposium on Circuits and Systems, MWSCAS 2023

作者： Kordi, Farshideh Barnard, Christian Fortier, Paul Miled, Amine Université Laval Departement of Electrical and Computer Engineering QuébecQC Canada

ISBN: (纸本)9798350302103

Hardware-in-the-Loop (HIL) simulators have become an essential tool in the automotive industry as they allow comprehensive testing and validation of electronic control units (ECUs), Although HIL simulations are widely used in the vehicle, aerospace and other industries that rely on electronic control systems, they can also be quite challenging to develop. One of the main challenges of HIL simulators is creating a virtual environment that accurately replicates the behavior of the real-world system. Artificial intelligence (AI) algorithms can be trained on extensive real-world datasets to create more accurate virtual environments of complex systems for HIL simulations. Moreover, latency is a crucial factor in producing a reliable virtual environment for ECU in HIL simulations. FPGA (Field Programmable Gate Array) can help to minimize latency in HIL simulations by providing high-performance computing resources. this paper aims to address these challenges by presenting a machine learning-based HIL simulator design on FPGA. the proposed architecture uses FPGA to accelerate the computations of a temporal convolutional neural network (TCN). the paper also describes how increasing the number of input channels can improve the performance of the TCN model on an FPGA. © 2023 ieee.

关键词： anti-lock brake system (ABS) artificial intelligence (AI) electronic control unit (ECU) Hardware-in-the-Loop (HIL) simulator temporal convolutional networks (TCN)

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A New Covert Channel in Fixed-Priority Real-Time Multiframe Tasks

A New Covert Channel in Fixed-Priority Real-Time Multiframe ...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Mohammad Fakhruddin Babar Monowar Hasan School of Electrical Engineering & Computer Science Washington State University USA

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

this study investigates the presence of illicit information flows in fixed-priority multiframe real-time systems. We identify an algorithmic covert channel (called FrameLeaker) that enables a low-priority task to deduce the execution patterns (frames) of a high-priority task. We show that the response time of a targeted low-priority task (receiver) can be used to extract the execution behavior of a high-priority task (sender). We further introduce a metric called "inference precision ratio" to evaluate the efficacy of the received information.

关键词： Measurement Receivers Real-time systems Time factors Task analysis Distributed computing

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WCSim: A Cloud computing Simulator with Support for Bag of Tasks Workflows

WCSim: A Cloud Computing Simulator with Support for Bag of T...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Maicon Ança dos Santos Gabriel J. A. Grabher Matheus F. Kovaleski Cláudio F. R. Geyer Gerson Geraldo H. Cavalheiro PPGC/UFPel Pelotas Brazil LIG/Université Grenoble-Alpes Grenoble France II/UFRGS Porto Alegre Brazil

In this paper, we present WCSim, Workflow Cloud Simulator. Firstly, we argue that this cloud simulation tool offers a high level of accessibility by allowing the description of various components, such as users, infrastructures, and workload, of a given scenario simply by providing parameters at launch time, without requiring the extension of the simulator code. then, we explain how we conceived the components for the simulation models and provide a detailed description of the implemented software. Additionally, we compare the results of a small scenario obtained from two other simulation tools with those provided by WCSim. Finally, we present a case study that illustrates the usage of WCSim. the paper also introduces the a abstraction to model workflows as a Direct Acyclic Graph of Bag of Tasks.

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Managing Complexity in Safety-critical Railway Signaling Systems using Simplex architectures

Managing Complexity in Safety-critical Railway Signaling Sys...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Robert Schmid Katja Assaf Clemens Tiedt Frederic Reiter Dirk Friedenberger Andreas Polze Hasso-Plattner Institute University of Potsdam Potsdam Germany

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

With the increasing reach and applicability of software systems in railway infrastructure, their complexity and the demand for constant change increases. Main factors include the use of unreliable COTS components, technical obsolescence, increasing centralization, international harmonization of technical and operational standards as well as IT-security concerns. Statically assessing the functional safety of a software-based railway system (offline assurance) is thus insufficient to maintain continued *** simplex architectures on multiple layers of the system architecture can alleviate this problem: Using a simple decision logic component, simplex controls the complexity of an evolving and multi-faceted system while maintaining the level of dependability that is required for safe passenger transport. We argue that the introduction of online assurance marks a paradigm shift in the railway domain, where the system safety today is guaranteed by expert assessments.

关键词： Communication system signaling Systems architecture computer architecture Aging Software systems Rail transportation Real-time systems

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Fast Arbitrary Precision Floating Point on FPGA 30

Fast Arbitrary Precision Floating Point on FPGA

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ieee 30th international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Licht, Johannes de Fine Pattison, Christopher A. Ziogas, Alexandros Nikolaos Simmons-Duffin, David Hoefler, Torsten Swiss Fed Inst Technol Dept Comp Sci Zurich Switzerland CALTECH Inst Quantum Informat & Matter Pasadena CA 91125 USA CALTECH Walter Burke Inst Theoret Phys Pasadena CA 91125 USA

ISBN: (纸本)9781665483322

Numerical codes that require arbitrary precision floating point (APFP) numbers for their core computation are dominated by elementary arithmetic operations due to the superlinear complexity of multiplication in the number of mantissa bits. APFP computations on conventional software-based architectures are made exceedingly expensive by the lack of native hardware support, requiring elementary operations to be emulated using instructions operating on machine-word-sized blocks. In this work, we show how APFP multiplication on compile-time fixed-precision operands can be implemented as deep FPGA pipelines with a recursively defined Karatsuba decomposition on top of native DSP multiplication. When comparing our design implemented on an Alveo U250 accelerator to a dual-socket 36-core Xeon node running the GNU Multiple Precision Floating-Point Reliable (MPFR) library, we achieve a 9.8x speedup at 4.8 GOp/s for 512-bit multiplication, and a 5.3x speedup at 1.2 GOp/s for 1024-bit multiplication, corresponding to the throughput of more than 351x and 191x CPU cores, respectively. We apply this architecture to general matrix-matrix multiplication, yielding a 10x speedup at 2.0 GOp/s over the Xeon node, equivalent to more than 375x CPU cores, effectively allowing a single FPGA to replace a small CPU cluster. Due to the significant dependence of some numerical codes on APFP, such as semidefinite program solvers, we expect these gains to translate into real-world speedups. Our configurable and flexible HLS-based code provides as high-level software interface for plug-and-play acceleration, published as an open source project.

关键词： Codes Pipelines Quantum mechanics computer architecture throughput Reliability engineering Hardware

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An Error-Resilient Compute-in-Memory 3D FPCA architecture for high-performance Floating-Point Operations

An Error-Resilient Compute-in-Memory 3D FPCA Architecture fo...

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ieee international symposium on Quality Electronic Design

作者： Hasita Veluri Dilip Vasudevan Lawrence Berkeley National Laboratory Applied Mathematics and Computational Research Berkeley CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

We present a runtime reconfigurable Field Programmable Crossbar Array (FPCA) architecture designed to enable high-accuracy multiplication and division alongside high through-put ML operations. Our innovative in-memory compute-based multiplier and divider designs employing novel partial product reduction techniques support expandable multi-precision floating-point operations. Leveraging advanced interface and peripheral design techniques, our error-resilient FPCA achieves 0% error for in-memory digital operations, demonstrating remarkable robustness and reliability despite device and crossbar irregularities. Additionally, our architecture enhances neural network training throughput by 63.8 × and improves power efficiency by 5.18 ×compared to state-of-the-art memristor-based accelerators. this work paves the way for future developments in high-performance, error-resistant in-memory computing solutions.

关键词： Training three-dimensional displays Runtime computer architecture Artificial neural networks In-memory computing throughput Reliability engineering Robustness System-on-chip

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Poster: Integration of Wearable and Affective computing via Abstraction and Decision Fusion architecture

Poster: Integration of Wearable and Affective Computing via ...

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ieee international symposium on World of Wireless Mobile and Multimedia Networks (WoWMoM)

作者： Mohammadreza Najafi Mohammad K Fallah Saeid Gorgin Ghassem Jaberipur Jeong-A Lee Department of Computer Engineering Chosun University Gwangju South Korea

ISBN: (数字)9798350394665

ISBN: (纸本)9798350394672

this paper introduces an efficient emotion detection method to integrate wearable and affective computing paradigms. Our research contributes to advancing emotion detection technologies, offering potential applications in diverse domains such as healthcare, human-computer interaction, and personalized computing experiences. Our approach addresses the increasing need for real-time emotion recognition while minimizing computational demands. By leveraging low-computation techniques, we propose a novel framework that achieves high accuracy in emotion detection. Besides, advanced data abstraction methods are developed to reduce data workload keeping detection performance. Experimental results demonstrate a notable accuracy rate of $89 .77$%, affirming the efficacy of our proposed method.

关键词： Wireless communication Emotion recognition Affective computing Accuracy Medical services computer architecture Real-time systems

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New FPGA design solution using quantum computation concepts 27

New FPGA design solution using quantum computation concepts

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ieee 27th international symposium for Design and Technology in Electronic Packaging (SIITME)

作者： Mazare, Alin Gheorghita Ionescu, Laurentiu Mihai Lita, Ioan Serban, Gheorghe Belu, Nadia Univ Pitesti Dept Elect Comp & Elect Engn Pitesti Romania Univ Pitesti Dept Mfg & Ind Management Pitesti Romania

ISBN: (纸本)9781665421102

Quantum computer emulators implemented on FPGA are generally designed to illustrate possible applications in which these concepts can be used - as a method of functional testing of possible applications involving quantum computing. In this paper we try to present another possible use of a quantum computation emulator, proposed by the authors, for the synthesis of circuits in FPGA with superior performance to conventional or parallel design methods. the paper presents a synthesis solution of parallel structures based on concepts from quantum computation emulated on FPGA. As will be seen in the paper, using the solution improves the computation time compared to the conventional method and reduces the number of resources allocated compared to the parallel solution. So, the solution which we propose is somewhere between conventional sequential logic circuit design methods - it has a shorter response time than these and parallel circuit design methods - it provides a smaller number of resources than these. In order to show the advantages of the proposed solution, we presented the implementation of a circuit for determining the parity of a binary function. the solution was implemented using the conventional solution, the parallel solution and the proposed solution using quantum computing concepts. It will show the performance of the proposed solution compared to the other design models.

关键词： Quantum computing Quantum computer emulator Field Programmable Gates Array (FPGA) Circuits design

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