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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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high-Quality I/O Bandwidth Prediction with Minimal Data via Transfer Learning Workflow

High-Quality I/O Bandwidth Prediction with Minimal Data via ...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Dmytro Povaliaiev Radita Liem Julian Kunkel Jay Lofstead Philip Carns Chair of High Performance Computing IT Center RWTH Aachen University Aachen Germany Georg-August Universität Göttingen/GWDG Göttingen Germany Sandia National Laboratory Albuquerque USA Argonne National Laboratory Lemont USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Providing a high-quality performance prediction has the potential to enhance various aspects of a cluster, such as devising scheduling and provisioning policies, guiding procurement decisions, suggesting candidate applications for tuning, and identifying probable scaling and porting challenges. Creating such a prediction for the I/O metrics is still challenging, however, due to the intricate interplay of multiple cluster components, making this an ideal case for machine learning. Nevertheless, achieving the required accuracy level with machine learning calls for a substantial amount of high-quality data, which is often a difficult challenge for most HPC clusters. In this work we explore the use of transfer learning to predict the applications’ I/O bandwidth based on a public dataset. As a result, our experiment can provide an I/O bandwidth prediction for a different cluster comparable to the current state-of-the-art result while employing 100 times less data than needed to construct the base model. Furthermore, we evaluate potential future improvements of the proposed workflow.

关键词： Procurement Measurement high performance computing Computational modeling Transfer learning Bandwidth computer architecture Predictive models Data models Tuning

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Utilizing Risk Number and Program Slicing to Improve Human-Machine Pair Inspection 27

Utilizing Risk Number and Program Slicing to Improve Human-M...

引用

27th international Conference on Engineering of Complex computer Systems, ICECCS 2023

作者： Dai, Yujun Liu, Shaoying Xu, Guangquan Liu, Ai Hiroshima University Graduate School of Advanced Science and Engineering Hiroshima Japan Tianjin University School of Cybersecurity College of Intelligence and Computing Tianjin China

ISBN: (纸本)9798350340044

Human-Machine Pair Inspection (HMPI) is a novel code inspection technology proposed in our previous work, which is the style that machine will intelligently guide the programmer to carry out inspections of the program code during programming. For large-scale software projects, the efficiency of HMPI needs to be improved due to the inaccurate measurement of the code structure and the excessive inspection scope. In this paper, to alleviate the above deficiencies, we propose the Risk Number, a code evaluation metric generated based on historical error data. the Risk Number is calculated by a statistical tool called regression analysis, which more accurately indicates the relationship between the nested structure of the code and the likelihood of containing bugs than Cognitive Complexity. Additionally, HMPI is supported by utilizing Risk Number to point out high-risk code and program slicing techniques to extract statements that have dependencies on the code to generate checklists, thereby reducing the scope of inspection. We describe a case study to evaluate the performance of this method by comparing its inspection time and number of detected errors with our previous work. the result shows that the method is likely to guide the programmer to inspect the faulty code earlier and be more efficient in detecting defects than HMPI based on Cognitive Complexity. © 2023 ieee.

关键词： Inspection

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Analyzing HPC Monitoring Data With a View Towards Efficient Resource Utilization

Analyzing HPC Monitoring Data With a View Towards Efficient ...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Samuel Maloney Estela Suarez Norbert Eicker Filipe Guimarães Wolfgang Frings Jülich Supercomputing Centre Forschungszentrum Jülich Germany Institute of Computer Science University of Bonn Germany School of Mathematics and Natural Sciences University of Wuppertal Germany

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Compute nodes in modern HPC systems are growing in size and their hardware has become ever more diverse. Still, many HPC centers allocate the resources of full nodes exclusively to avoid contention, despite the associated risk of underutilization. this paper describes a thorough resource utilization study of CPU and GPU compute and memory capacity, and interconnect bandwidth on JUWELS, a mature leadership-class modular supercomputer, with the aim of identifying opportunities for improving utilization through advanced scheduling and node sharing. Separate analysis of CPU-only and GPU-accelerated nodes finds that CPU compute usage is already close to optimal for the CPU-only nodes, whereas there is plenty of scope for co-scheduling CPU-based jobs on GPU-accelerated nodes. Memory capacity and node-level interconnect bandwidth are sufficient to provision co-scheduled jobs. We analyze multiple one-month datasets to validate robustness of conclusions over time and compare with previous studies on other systems to establish generalizability of results.

关键词： Runtime high performance computing Graphics processing units Bandwidth computer architecture Supercomputers Robustness Hardware Resource management Monitoring

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Optimal Time and Energy-Aware Client Selection Algorithms for Federated Learning on Heterogeneous Resources

Optimal Time and Energy-Aware Client Selection Algorithms fo...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Alan L. Nunes Cristina Boeres Lúcia M. A. Drummond Laércio L. Pilla Fluminense Federal University Niterói Brazil University of Bordeaux CNRS Bordeaux INP Inria LaBRI Talence France

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Federated Learning systems allow training machine learning models distributed across multiple clients, each one using private local data. Iteratively, the clients send their training contributions to a server, which performs a merge to produce an enhanced global model. Due to resource and data heterogeneity, client selection is crucial to optimize the system efficiency and improve the global model generalization. Selecting more clients is likely to increase the overall energy consumption, while a small number of clients may decline the performance of the trained model or require longer training time. We propose two time- and energy-aware client selection algorithms, MEC and ECMTC, which are proven regarding their optimality and evaluated against state-of-the-art algorithms on an extensive series of experiments in both simulation and HPC platform scenarios. the results indicate the benefits of jointly optimizing the time and energy consumption metrics using our proposals.

关键词： Training Measurement Energy consumption Federated learning high performance computing Distributed databases computer architecture Data models Servers Proposals

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Architectural Security and Trust Foundation for RISC-V

Architectural Security and Trust Foundation for RISC-V

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Marouene Boubakri Belhassen Zouari Mediatron Lab SupComUniversity of Carthage Tunis Tunisia

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

Modern System-on-Chips (SoC) rely on Trusted Execution Environment (TEE) to ensure the integrity and confidentiality of sensitive information by providing a secure environment for data processing. Serval TEE enablement with many mechanisms and architectures has been proposed for ARM-based computing devices, thus, presenting a rich body of literature. In counterpart, RISC-V lacks ratified TEE specifications and hence an effective system-wide security approach. Given an increasing number of vendors and Original Equipment Manufacturers (OEM) now plan to adopt the RISC-V in their products, this paper fills the gap and proposes a reference security and trust architecture enforced by TEE to allow the building of new security solutions and applications. We evaluate the work against current industry security requirements and practices and present comprehensive research with a promising direction. To the best of our knowledge, this is the first work exploring, proposing, analyzing, and evaluating complete security enablement for RISC-V with a final goal of delivering enhanced security at a lower cost to the smart devices market based on RISC-V.

关键词： Costs architecture Buildings computer architecture Data processing Real-time systems System-on-chip

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FPGA Checkpointing for Scientific computing 27

FPGA Checkpointing for Scientific Computing

引用

27th ieee international symposium on On-Line Testing and Robust System Design (IOLTS)

作者： Perello Bacardit, Marc Bautista-Gomez, Leonardo Unsal, Osman Barcelona Supercomp Ctr Barcelona Spain

ISBN: (纸本)9781665433709

the use of FPGAs in computational workloads is becoming increasingly popular due to the flexibility of these devices in comparison to ASICs, and their low power consumption compared to GPUs and CPUs. However, scientific applications run for long periods of time and the hardware is always subject to failures due to either soft or hard errors. thus, it is important to protect these long running jobs with fault tolerance mechanisms. Checkpoint-Restart is a popular technique in high-performance computing that allows large scale applications to cope with frequent failures. In this work we approach the fault tolerance of CPUFPGA heterogeneous applications from a high level by using OmpSs@FPGA environment and a multi-level checkpointing library. We analyse the performance of several different applications and we understand what kind of overheads we can expect from checkpointing computational workloads running on FPGAs. Our results demonstrate overheads as low as 0.16% and 0.66% when checkpointing very frequently, indicating that this technique is efficient and does not add a significant amount of overhead to the system. In addition, we showcase a proof of concept for checkpointing partial data of the FPGA task itself. this can prove useful for workloads in which most data is offloaded to the FPGA memory at once and do not constantly move all the data between the accelerator and the CPU.

关键词： FPGA FTI fault tolerance accelerator resilience checkpointing reliability

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A Distributed Algorithm for Identifying Strongly Connected Components on Incremental Graphs

A Distributed Algorithm for Identifying Strongly Connected C...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： S. Srinivasan A. Khanda A. Pandey S. K. Das S. Bhowmick B. Norris Department of Computer Science University of Oregon Eugene OR USA Department of Computer Science and Engineering University of North Texas Denton TX USA Department of Computer Science Missouri University of Science and Technology Rolla MO USA Department of Management Information Systems Bowie State University MD

Incremental graphs that change over time capture the changing relationships of different entities. Given that many real-world networks are extremely large, it is often necessary to partition the network over many distributed systems and solve a complex graph problem over the partitioned network. this paper presents a distributed algorithm for identifying strongly connected components (SCC) on incremental graphs. We propose a two-phase asynchronous algorithm that involves storing the intermediate results between each iteration of dynamic updates in a novel meta-graph storage format for efficient recomputation of the SCC for successive iterations. To the best of our knowledge, this is the first attempt at identifying SCC for incremental graphs across distributed compute nodes. Our experimental analysis on real and synthesized graphs shows up to 2.8x performance improvement over the state-of-the-art by reducing the overall memory utilized and improving the communication bandwidth.

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DeepWave: A Software Stack for Parallelizing Deep Learning Models Used in Geophysics

DeepWave: A Software Stack for Parallelizing Deep Learning M...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Allan Pinto Gustavo Leite Marcio Pereira Hervé Yviquel Sandro Rigo Guido Araujo (LNLS) Brazilian Synchrotron Light Laboratory Brazilian Center for Research in Energy and Materials (CNPEM) Campinas Sao Paulo Brazil Institute of Computing University of Campinas (UNICAMP) Campinas Sao Paulo Brazil

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

this paper introduces DeepWave, a novel software stack, and methodology designed to integrate generative artificial intelligence into traditional seismic surveying techniques, significantly enhancing the computational efficiency of geophysical exploration. By utilizing advanced machine learning frameworks such as JAX, FLAX, and ALPA, DeepWave employs a parallelization strategy for image-to-image translation networks, optimizing the seismic data interpretation process. DeepWave reduces the computational demands of intensive geophysical algorithms, such as Full-waveform Inversion (FWI), while maintaining the accuracy required for detailed subsurface analysis. this method enables faster and more efficient processing of large seismic datasets, providing deeper insights into the Earth’s subsurface structures with reduced computational resources. the results demonstrate a substantial improvement in processing speed and resource management, establishing a new geophysical research and exploration standard.

关键词： Training Deep learning Machine learning algorithms Computational modeling high performance computing Full stack Parallel processing Computational efficiency Resource management Standards

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Evaluation of Early Packet Drop Scheduling Policies in Criticality-Aware Wireless Sensor Networks

Evaluation of Early Packet Drop Scheduling Policies in Criti...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Andras Pinter Leandro Soares Indrusiak Ian Gray Department of Computer Science University of York York United Kingdom School of Computing University of Leeds Leeds United Kingdom

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

this paper introduces three autonomous, criticality-aware packet scheduling policies that address the impact of high traffic loads and degraded conditions in wireless sensor networks. the proposed policies, collectively referred to as Early Packet Drop (EPD), leverage cross-layer information, including RPL Rank, link quality, and time-slotted Medium Access Control schedule, to mitigate Quality of Service degradation. Simulation results demonstrate that EPD consistently outperforms a Criticality-Monotonic Scheduling (CMS) baseline.

关键词： Degradation Wireless communication Wireless sensor networks Schedules Scheduling algorithms Simulation Telecommunication traffic

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Exploiting the Potential of Flexible Processing Units

Exploiting the Potential of Flexible Processing Units

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Mateo Vázquez Muhammad Waqar Azhar Pedro Trancoso Department of Computer Science and Engineering Chalmers University of Technology Gothenburg Sweden

In order to meet the increased computational demands and stricter power constraints of modern applications, architectures have evolved to include domain-specific accelerators. In order to design efficient accelerators, three main challenges need to be addressed: compute, memory, and control. Moreover, since SoCs usually contain multiple accelerators, selecting the right one for each task also become crucial. this becomes specially relevant in Flexible Processing Units (xPUs), processing units that provide multiple functionalities with the same hardware. While it is possible to use shared support components for all functionalities, this will lead to sub-optimal performance. In this work, we take one example of such xPU, and analyze the aspects which have not yet been fully addressed, showing that there is more potential to be exploited. By understanding the required memory patterns, we can achieve up to 72% speedup gains compared to using the memory support optimized for a different functionality. Furthermore, we propose an in-depth analysis of the different functionalities provided by the xPU. We then leverage the insights obtained from this analysis by providing a mechanism that selects the right functionality, maximizing hardware utilization.

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