检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,861 篇 会议
9 篇 期刊文献

馆藏范围

1,870 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,162 篇 工学
- 1,098 篇 计算机科学与技术...
- 479 篇 软件工程
- 285 篇 电气工程
- 138 篇 信息与通信工程
- 126 篇 电子科学与技术（可...
- 52 篇 控制科学与工程
- 33 篇 动力工程及工程热...
- 21 篇 机械工程
- 17 篇 生物医学工程（可授...
- 16 篇 仪器科学与技术
- 15 篇 生物工程
- 14 篇 网络空间安全
- 12 篇 环境科学与工程（可...
- 10 篇 光学工程
- 8 篇 力学（可授工学、理...
- 8 篇 建筑学
- 7 篇 化学工程与技术
218 篇 理学
- 161 篇 数学
- 33 篇 物理学
- 32 篇 系统科学
- 18 篇 生物学
- 17 篇 统计学（可授理学、...
- 9 篇 化学
- 9 篇 地球物理学
196 篇 管理学
- 156 篇 管理科学与工程(可...
- 79 篇 工商管理
- 44 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 9 篇 社会学
10 篇 医学
- 8 篇 基础医学(可授医学...
6 篇 农学
5 篇 教育学

主题

547 篇 computer archite...
187 篇 hardware
122 篇 high performance...
109 篇 field programmab...
108 篇 computational mo...
83 篇 grid computing
80 篇 cloud computing
73 篇 concurrent compu...
73 篇 application soft...
73 篇 distributed comp...
72 篇 computer science
71 篇 parallel process...
71 篇 resource managem...
71 篇 graphics process...
70 篇 kernel
63 篇 throughput
59 篇 bandwidth
59 篇 benchmark testin...
58 篇 optimization
56 篇 runtime

机构

8 篇 school of comput...
8 篇 intel corp santa...
7 篇 univ chicago dep...
7 篇 mathematics and ...
6 篇 georgia inst tec...
6 篇 university of ch...
6 篇 mathematics and ...
6 篇 college of compu...
5 篇 univ wisconsin m...
5 篇 barcelona superc...
5 篇 univ calif santa...
5 篇 northeastern uni...
5 篇 carnegie mellon ...
5 篇 intel corporatio...
5 篇 univ fed rio gra...
4 篇 univ politecn ca...
4 篇 univ toronto on
4 篇 univ illinois ur...
4 篇 georgia institut...
4 篇 oak ridge nation...

作者

11 篇 navaux philippe ...
8 篇 prasanna viktor ...
8 篇 mutlu onur
7 篇 borin edson
7 篇 chong frederic t...
7 篇 guedes dorgival
6 篇 dongarra jack
6 篇 patt yale n.
6 篇 xie yuan
6 篇 torrellas josep
6 篇 schwan karsten
6 篇 ferreira renato
6 篇 i. foster
5 篇 franca felipe m....
5 篇 hwu wen-mei
5 篇 nam sung kim
5 篇 martonosi margar...
5 篇 loh gabriel h.
5 篇 kim nam sung
5 篇 zhou huiyang

语言

1,856 篇 英文
11 篇 中文
2 篇 其他
1 篇 葡萄牙文

检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

共 1870 条记录，以下是171-180 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Characterizing the Impact of Job Execution on the Occurrence of Memory Failures on a Petascale HPC System

Characterizing the Impact of Job Execution on the Occurrence...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Scott Levy Josh Hemmert Kurt B. Ferreira Kevin Pedretti Center for Computing Research Sandia National Laboratories Albuquerque NM USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Characterizing the reliability of current and recent high performance (HPC) systems is critical for forecasting how future systems may behave and informing the design of fault tolerance mechanisms. Although research has been conducted to understand memory failures, there are few examples where the occurrence of memory failures is considered in the broader context of system power, temperature, and the execution of user jobs. In this paper, we combine job data with existing power, temperature, and memory failure data collected on a petascale HPC system. By focusing on periods when jobs were running on the system, we identified trends that were not evident in earlier studies of this same data. the inclusion of job data also demonstrated how user behavior can affect the occurrence of memory failures. In conjunction with this paper, we have publicly released the job data used in this paper to complement existing publicly-available data from Astra regarding power, temperature, and the occurrence of correctable memory failures.

关键词： Temperature distribution high performance computing Random access memory Graphics processing units Focusing Reliability engineering Market research Hardware Object recognition Forecasting

来源：评论

学校读者我要写书评

暂无评论

xBGAS: A Global Address Space Extension on RISC-V for high performance computing 35

xBGAS: A Global Address Space Extension on RISC-V for High P...

引用

35th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Wang, Xi Leidel, John D. Williams, Brody Ehret, Alan Mark, Miguel Kinsy, Michel A. Chen, Yong Texas Tech Univ Lubbock TX 79409 USA Tact Comp Labs Muenster TX USA Texas A&M Univ College Stn TX USA

ISBN: (纸本)9781665440660

the tremendous expansion of data volume has driven the transition from monolithic architectures towards systems integrated with discrete and distributed subcomponents in modern scalable high performance computing (HPC) systems. As such, multi-layered software infrastructures have become essential to bridge the gap between heterogeneous commodity devices. However, operations across synthesized components with divergent interfaces inevitably lead to redundant software footprints and undesired latency. therefore, a scalable and unified computing platform, capable of supporting efficient interactions between individual components, is desirable liar large-scale data-intensive applications. In this work, we introduce the Extended Base Global Address Space, or xBGAS, microarchitecture extension to the RISC-V instruction set architecture (ISA) for scalable high performance computing. the xBGAS extension provides native ISA-level support for direct accesses to remote shared memory by mapping remote data objects into a system's extended address space. We perform both software and hardware evaluations of the xBGAS design. the results show that xBGAS reduces instruction count generated by interprocess communication by 69.26% on average. Overall, xBGAS achieves an average performance gain of 21.96% (up to 37.29%) across the tested workloads.

关键词： Microarchitecture Runtime library high performance computing Instruction sets computer architecture Programming performance gain

来源：评论

学校读者我要写书评

暂无评论

Preventing Order Inversion within Function-as-a-Service for Sensor Networks

Preventing Order Inversion within Function-as-a-Service for ...

引用

international symposium on Object-Oriented Real-Time Distributed computing

作者： Takashi Ikegami Ichiro Satoh Tatsuo Nakajima SOKENDAI / National Institute of Informatics The Graduate University for Advanced Studies Tokyo Japan National Institute of Informatics Tokyo Japan Department of Computer Science and Engineering Waseda University Tokyo Japan

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

Server-less architectures, specifically Function-as-a-Service (FaaS), are sometimes used for data processing in sensor networks. However, due to fluctuations in the start and completion times of FaaS tasks, the order can get reversed even when tasks are required to execute in sequence. As long as the start and end times of FaaS tasks are treated as delay fluctuated, it is not feasible to execute data processing as FaaS tasks. therefore, this paper aims to clarify and formalize the conditions under which the execution order of periodic tasks by FaaS is maintained, assuming that fluctuations in the start and completion times of FaaS tasks can be predicted within a certain range. Furthermore, it presents a method to minimize the impact on data analysis when the completion of FaaS tasks is delayed beyond that predicted range. It is the first challenge that can provide the direction for future research on addressing the fluctuations.

关键词： Fluctuations Data analysis computer architecture Dynamic scheduling Real-time systems Delays Resource management

来源：评论

学校读者我要写书评

暂无评论

Kub: Enabling Elastic HPC Workloads on Containerized Environments

Kub: Enabling Elastic HPC Workloads on Containerized Environ...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Daniel Medeiros Jacob Wahlgren Gabin Schieffer Ivy Peng Department of Computer Science KTH Royal Institute of Technology Sweden

the conventional model of resource allocation in HPC systems is static. thus, a job cannot leverage newly available resources in the system or release underutilized resources during the execution. In this paper, we present Kub, a methodology that enables elastic execution of HPC workloads on Kubernetes so that the resources allocated to a job can be dynamically scaled during the execution. One main optimization of our method is to maximize the reuse of the originally allocated resources so that the disruption to the running job can be minimized. the scaling procedure is coordinated among nodes through remote procedure calls on Kubernetes for deploying workloads in the cloud. We evaluate our approach using one synthetic benchmark and two production-level MPI-based HPC applications - GRO-MACS and CM1. Our results demonstrate that the benefits of adapting the allocated resources depend on the workload characteristics. In the tested cases, a properly chosen scaling point for increasing resources during execution achieved up to 2x speedup. Also, the overhead of checkpointing and data reshuffling significantly influences the selection of optimal scaling points and requires application-specific knowledge.

关键词：

来源：评论

学校读者我要写书评

暂无评论

EQC: Ensembled Quantum computing for Variational Quantum Algorithms 22

EQC: Ensembled Quantum Computing for Variational Quantum Alg...

引用

49th ieee/ACM Annual international symposium on computer architecture (ISCA)

作者： Stein, Samuel Wiebe, Nathan Ding, Yufei Bo, Peng Kowalski, Karol Baker, Nathan Ang, James Li, Ang Pacific Northwest Natl Lab Richland WA 99354 USA Univ Calif Santa Barbara Santa Barbara CA USA Univ Toronto Toronto ON Canada

ISBN: (纸本)9781450386104

Variational quantum algorithm (VQA), which is comprised of a classical optimizer and a parameterized quantum circuit, emerges as one of the most promising approaches for harvesting the power of quantum computers in the noisy intermediate scale quantum (NISQ) era. However, the deployment of VQAs on contemporary NISQ devices often faces considerable system and time-dependant noise and prohibitively slow training speeds. On the other hand, the expensive supporting resources and infrastructure make quantum computers extremely keen on high utilization. In this paper, we propose a virtualized way of building up a quantum backend for variational quantum algorithms: rather than relying on a single physical device which tends to introduce ever-changing device-specific noise with less reliable performance as time-since-calibration grows, we propose to constitute a quantum ensemble, which dynamically distributes quantum tasks asynchronously across a set of physical devices, and adjusts the ensemble configuration with respect to machine status. In addition to reduced machine-dependant noise, the ensemble can provide significant speedups for VQA training. With this idea, we build a novel VQA training framework called EQC - a distributed gradient-based processor-performance-aware optimization system - that comprises: (i) a system architecture for asynchronous parallel VQA cooperative training;(ii) an analytical model for assessing the quality of a circuit output concerning its architecture, transpilation, and runtime conditions;(iii) a weighting mechanism to adjust the quantum ensemble's computational contribution according to the systems' current performance. Evaluations comprising 500K times' circuit evaluations across 10 IBMQ NISQ devices using a VQE and a QAOA applications demonstrate that EQC can attain error rates very close to the most performant device of the ensemble, while boosting the training speed by 10.5x on average (up to 86x and at least 5.2x). EQC is available at

关键词： Quantum computing Variational Quantum Algorithms Distributed computing

来源：评论

学校读者我要写书评

暂无评论

A new level-set analysis and sparse storage format for the SPTRSV in GPUs

A new level-set analysis and sparse storage format for the S...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Manuel Freire Ernesto Dufrechou Pablo Ezzatti

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Due to its relevant role in many numerical methods, the solution of sparse triangular linear systems (SpTRSV) in parallel platforms is continuously studied to extract as much performance as possible from the latest hardware architectures. In the case of GPUs, the latest solvers use the synchronization-free paradigm. When the problem involves several system solutions for the same matrix, they often pre-process it through a levelset analysis to improve the equation solution scheduling in the solution phase. In addition, other optimizations address the load balancing issues and irregular memory access of the SpTRSV. In this work, we modify the classical approach to compute the level sets used in the parallel SpTRSV computation, and we show that the new strategy generally reduces the computation time of the solver. Furthermore, we design an internal matrix representation that can significantly accelerate the solution stage at the cost of increasing the memory storage requirements of the algorithm. the experimental evaluation shows that the proposed modifications can improve the performance of a recent levelset and synchronization-free solver by up to 70%, significantly outperforming other state-of-the-art solvers, especially when several linear systems must be solved for each analysis phase.

关键词： Linear systems Costs Processor scheduling Level set high performance computing Memory management Load management Hardware Sparse matrices Optimization

来源：评论

学校读者我要写书评

暂无评论

Unlimited Vector Extension with Data Streaming Support 21

Unlimited Vector Extension with Data Streaming Support

引用

ACM/ieee 48th Annual international symposium on computer architecture (ISCA)

作者： Domingos, Joao Mario Neves, Nuno Roma, Nuno Tomas, Pedro Univ Lisbon Inst Super Tecn INESC ID Lisbon Portugal INESC ID Inst Telecomunicacoes Lisbon Portugal

ISBN: (纸本)9781665433334

Unlimited vector extension (UVE) is a novel instruction set architecture extension that takes streaming and SIMD processing together into the modern computing scenario. It aims to overcome the shortcomings of state-of-the-art scalable vector extensions by adding data streaming as a way to simultaneously reduce the overheads associated with loop control and memory access indexing, as well as with memory access latency. this is achieved through a new set of instructions that pre-configure the loop memory access patterns. these attain accurate and timely data prefetching on predictable access patterns, such as in multidimensional arrays or in indirect memory access patterns. Each of the configured data streams is associated to a general-purpose vector register, which is then used to interface with the streams. In particular, iterating over a given stream is simply achieved by reading/writing to the corresponding input/output stream, as the data is instantly consumed/produced. To evaluate the proposed UVE, a proof-of-concept gem5 implementation was integrated in an out-of-order processor model, based on the ARM Cortex-A76, thus taking into consideration the typical speculative and out-of-order execution paradigms found in high-performance computing processors. the evaluation was carried out with a set of representative kernels, by assessing the number of executed instructions, its impact on the memory bus and its overall performance. Compared to other state-of-the-art solutions, such as the upcoming ARM Scalable Vector Extension (SVE), the obtained results show that the proposed extension attains average performance speedups over 2.4x for the same processor configuration, including vector length.

关键词： Scalable SIMD/Vector Processing Data Streaming Instruction Set Extension Processor Microarchitecture high-performance computing

来源：评论

学校读者我要写书评

暂无评论

Analysing Mechanisms for Virtual Channel Management in Low-Diameter Networks

Analysing Mechanisms for Virtual Channel Management in Low-D...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Alejandro Cano Cristóbal Camarero Carmen Martínez Ramón Beivide Computer and Electronics Department Universidad de Cantabria Santander Spain

To interconnect their growing number of servers, current supercomputers and data centers are starting to adopt low-diameter networks, such as HyperX, Dragonfly and Dragonfly+. these emergent topologies require balancing the load over their links and finding suitable non-minimal routing mechanisms for them becomes particularly challenging. the Valiant load balancing scheme is a very popular choice for non-minimal routing. Evolved adaptive routing mechanisms implemented in real systems are based on this Valiant scheme. All these low-diameter networks are deadlock-prone when non-minimal routing is employed. Routing deadlocks occur when packets cannot progress due to cyclic dependencies. therefore, developing efficient deadlock-free packet routing mechanisms is critical for the progress of these emergent networks. the routing function includes the routing algorithm for path selection and the buffers management policy that dictates how packets allocate the buffers of the switches on their paths. For the same routing algorithm, a different buffer management mechanism can lead to a very different performance. Moreover, certain mechanisms considered efficient for avoiding deadlocks, may still suffer from hard to pinpoint instabilities that make erratic the network response. this paper focuses on exploring the impact of these buffers management policies on the performance of current interconnection networks, showing a 90% of performance drop if an incorrect buffers management policy is used. Moreover, this study not only characterizes some of these undesirable scenarios but also proposes practicable solutions.

关键词：

来源：评论

学校读者我要写书评

暂无评论

TailorFS: An Adaptive File System to Support Dynamic I/O requirements of HPC Workloads

TailorFS: An Adaptive File System to Support Dynamic I/O req...

引用

international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Hariharan Devarajan Kathryn Mohror Lawrence Livermore National Laboratory

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

high-performance computing (HPC) systems typically provide a global storage system to support large-scale workload’s I/O requirements. However, these workloads have diversified from traditional simulation to include big data analytics and AI workloads. HPC systems include hardware accelerators and storage software with configurations to support this workload diversification. However, selecting the correct combination of these configurations for each workload is a complex task even for I/O experts. To address this problem, we designed TailorFS, a software abstraction using FSView that transparently selects the appropriate file system characteristics including software abstractions, hardware accelerators, and optimizations to accelerate I/O for a given workload. Given a workload’s behavior, TailorFS chooses an appropriate software existing in the system and a corresponding configuration to dynamically optimize the workload. With TailorFS, users can utilize any interface to perform I/O on the file system and get the correct software selected for them based on the described behavior. Finally, TailorFS can accelerate I/O for different workload types by up to 46 × by utilizing workload characteristics. In conclusion, TailorFS can accelerate complex HPC workflows by up to 6.5 × better I/O performance on the Lassen supercomputer by using dynamically created workload-aware FSViews.

关键词： File systems high performance computing Memory management throughput Software Supercomputers Libraries Middleware Optimization Hardware acceleration

来源：评论

学校读者我要写书评

暂无评论

pLUTo: Enabling Massively Parallel Computation in DRAM via Lookup Tables 55

pLUTo: Enabling Massively Parallel Computation in DRAM via L...

引用

55th Annual ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Ferreira, Joao Dinis Falcao, Gabriel Gomez-Luna, Juan Alser, Mohammed Orosa, Lois Sadrosadati, Mohammad Kim, Jeremie S. Oliveira, Geraldo F. Shahroodi, Taha Nori, Anant Mutlu, Onur Swiss Fed Inst Technol Zurich Switzerland Univ Coimbra P-3000 Coimbra Portugal Galicia Supercomputing Ctr Santiago De Compostela Spain Delft Univ Technol Delft Netherlands Intel Santa Clara CA USA

ISBN: (数字)9781665462723

ISBN: (纸本)9781665462723

Data movement between the main memory and the processor is a key contributor to execution time and energy consumption in memory-intensive applications. this data movement bottleneck can be alleviated using Processing-in-Memory (PiM). One category of PiM is Processing-using-Memory (PuM), in which computation takes place inside the memory array by exploiting intrinsic analog properties of the memory device. PuM yields high performance and energy efficiency, but existing PuM techniques support a limited range of operations. As a result, current PuM architectures cannot efficiently perform some complex operations (e.g., multiplication, division, exponentiation) without large increases in chip area and design complexity. To overcome these limitations of existing PuM architectures, we introduce pLUTo (processing-using-memory with lookup table (LUT) operations), a DRAM-based PuM architecture that leverages the high storage density of DRAM to enable the massively parallel storing and querying of lookup tables (LUTs). the key idea of pLUTo is to replace complex operations with low-cost, bulk memory reads (i.e., LUT queries) instead of relying on complex extra logic. We evaluate pLUTo across 11 real-world workloads that showcase the limitations of prior PuM approaches and show that our solution outperforms optimized CPU and GPU baselines by an average of 713x and 1.2x, respectively, while simultaneously reducing energy consumption by an average of 1855x and 39.5x. Across these workloads, pLUTo outperforms state-of-the-art PiM architectures by an average of 18.3x. We also show that different versions of pLUTo provide different levels of flexibility and performance at different additional DRAM area overheads (between 10.2% and 23.1%). pLUTo 's source code and all scripts required to reproduce the results of this paper are openly and fully available at https://***/CMU- SAFARI/pLUTo.

关键词： performance evaluation Energy consumption Microarchitecture Source coding Random access memory computer architecture System integration

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共187页 << < 14 15 16 17 18 19 20 21 22 23 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：