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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Partial scan beyond cycle cutting

Partial scan beyond cycle cutting

引用

international symposium on Fault-Tolerant computing (FTCS)

作者： G.S. Saund M.S. Hsiao J.H. Patel Center for Reliable and High-Performance Computing University of Illinois Urbana-Champaign Urbana IL USA

this paper addresses the problem of flip flop selection for partial scan in sequential circuits. In particular it addresses some of the shortcomings of the popular flip flop selection methods, based on cutting cycles present in the graph of the circuit structure. Previous approaches assume that cutting all cycles makes the circuit totally testable, which is not always true. In the proposed approach, first subsets of flip flops are formed based on cycles in the S-graph and flip flops with self-loops. Flip flops are selected from these subsets based on a testability measure which uses an approximate valid state analysis. Once a flip flop is selected from a subset, testability measures may indicate the need for more flip flops, thus possibly selecting more flip flops than required for minimum cycle cutting. the goal is to select the fewest number of flip flops required to obtain high fault coverage for all partial scan circuits. Experimental results on the benchmark circuits show that a test generation efficiency near 100% is achieved for most circuits.

关键词： Circuit testing Circuit faults Sequential analysis Sequential circuits Contracts Semiconductor device testing Logic testing Benchmark testing Design methodology Design for testability

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Probabilistic checkpointing

Probabilistic checkpointing

引用

international symposium on Fault-Tolerant computing (FTCS)

作者： Hyo-Chang Nam Jong Kim SungJe Hong Sunggu Lee Department of Computer Science and Engineering Pohang University of Science and Technology Pohang South Korea Department of Electrical Engineering Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)0818678313

Many optimization schemes have been proposed to reduce the overhead of checkpointing. Incremental checkpointing based on memory page protection has been one of the successful schemes used to reduce the overhead and to improve the performance of checkpointing. In this paper, we propose two checkpointing schemes, called "block encoding" and "combined block encoding", which further reduce the checkpointing overhead. the smallest unit of checkpoint data in our scheme is a block, which is smaller than a page-this reduces the amount of checkpoint data required when compared with page-based incremental checkpointing. One drawback of the proposed schemes is the possibility of aliasing in encoded words. In this paper, however, we show that the aliasing probability is near zero when an 8-byte encoded word is used. the performance of the proposed schemes is analyzed and measured using experiments. First, we construct an analytic model that predicts the checkpointing overhead. By using this model, we can estimate the block size that produces the best performance for a given target program. Next, the proposed schemes are implemented on libckpt, a general-purpose checkpointing library for Unit based system which was developed at the University of Tennessee. According to our experimental results, the proposed schemes reduce the overhead by 11.7% in the best case and increase the overhead by 0.5% in the worst case in comparison with page-based incremental checkpointing. In most cases, the combined block encoding scheme shows an improvement over both block encoding and page-based incremental checkpointing.

关键词： Checkpointing Encoding Costs Delay computer science Protection performance analysis Libraries Fault tolerant systems Multiprocessing systems

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One-transistor-cell 4-valued universal-literal CAM for cellular logic image processing

One-transistor-cell 4-valued universal-literal CAM for cellu...

引用

international symposium on Multiple-Valued Logic

作者： T. Hanyu M. Arakaki M. Kameyama Department of Computer and Mathematical Sciences Graduate School of Information Scienccs Tohoku University Sendai Japan

A non-volatile 4-valued content-addressable memory (CAM) is proposed for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal in each CAM cell is used to compare a 4-valued input pixel with a 4-valued template pattern. Any CAM cell functions are performed by a pair of a simple threshold operation and a logic-value conversion which is shared by CAM cells in the same column of a CAM cellular array. Moreover, the use of a single floating-gate MOS transistor makes it possible to implement a universal-literal circuit together with a 4-valued storage element. As a result, a high-density 4-valued universal-literal CAM, with a single transistor cell is designed by using a multi-layer interconnection technology. Its performance is much superior to that of conventional CAM-based implementations under the same dynamic power dissipation.

关键词： computer aided manufacturing CADCAM Logic Image processing Circuits MOSFETs Hardware Power dissipation threshold voltage Concurrent computing

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Towards Web/Java-based high performance distributed computing - An evolving virtual machine

Towards Web/Java-based high performance distributed computin...

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5th ieee international symposium on high performance Distributed computing

作者： Fox, G Furmanski, W SYRACUSE UNIV NE PARALLEL ARCHITECTURES CTRSYRACUSENY

ISBN: (纸本)0818675829

We discuss here the emergent Web based distributed environments for HPCC on the NII with the focus on Java as an enabling technology. We start with a review of the past, presence and the near term future of the 'Java phenomenon', exposed here in the background of some related previous approaches towards a distributed interpretative virtual machine architecture.

关键词： Distributed computer systems

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Supporting HPDC applications over ATM networks with cell-based transport mechanisms

Supporting HPDC applications over ATM networks with cell-bas...

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5th ieee international symposium on high performance Distributed computing

作者： VilaSallent, J SolePareta, J UNIV POLITECN CATALUNYA DEPT COMP ARCHITECTUREBARCELONACATALONIASPAIN

ISBN: (纸本)0818675829

In this paper, we address the problem of supporting high performance Distributed computing (HPDC) applications running over ATM networks. For this purpose, we consider a logically separate subnetwork for these applications. After presenting an architectural reference model for the HPDC subnetwork and distinguishing which functions should be installed over the ATM network in order to satisfy the needs of HPDC applications, we propose two mechanisms that aim at optimizing communications by taking advantage of both the special properties of HPDC traffic and the cell-based nature of ATM. the performance of these mechanisms is evaluated and compared with that achieved by the SSCOP protocol. the results show that when the ATM network experiences high load and the HPDC applications make an intensive use of arrays, cell-based mechanisms become more robust than standard SSCOP and provide low latency and efficient cell loss recovery. Since both situations are very likely to occur in HPDC environments, we conclude that the introduction of cell-based retransmission mechanisms does contribute to enhance performance of HPDC systems over ATM networks.

关键词： Distributed computer systems

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Core legion object model

Core legion object model

引用

Proceedings of the 1996 5th ieee international symposium on high performance Distributed computing

作者： Lewis, Mike Grimshaw, Andrew Univ of Virginia Charlottesville United States

ISBN: (纸本)0818675829

the Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault-tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools;the system will enable fault-tolerance, wide area parallel processing, inter-operability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. this paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects - those objects that cooperate to create, locate, manage, and remove objects in the Legion system. the object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.

关键词： computer architecture

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Approach towards benchmarking of fault-tolerant commercial systems

Approach towards benchmarking of fault-tolerant commercial s...

引用

Proceedings of the 1996 26th international symposium on Fault-Tolerant computing

作者： Tsai, Timothy K. Iyer, Ravishankar K. Jewitt, Doug Univ of Illinois at Urbana-Champaign Urbana United States

this paper presents a benchmark for dependable systems. the benchmark consists of two metrics, number of catastrophic incidents and performance degradation, which are obtained by a tool that (1) generates synthetic workloads that produce a high level of CPU, memory, and I/O activity and (2) injects CPU, memory, and I/O faults according to an injection strategy. the benchmark has been installed on two TMR-based prototype machines: TMR Prototype A and TMR Prototype B. An implementation for a third prototype, is based on a duplex architecture, is in progress. the results demonstrate the utility of the benchmark in comparing the system-level fault tolerance of these machines and in providing insight into their design. In particular, the benchmark shows that Prototype B suffers fewer catastrophic incidents than Prototype A under the same workload conditions and fault injection method. However, Prototype B also suffers more performance degradation in the presence of faults, which might be an important concern for time-critical applications.

关键词： Fault tolerant computer systems

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Runtime support for parallelization of data-parallel applications on adaptive and nonuniform computational environments

Runtime support for parallelization of data-parallel applica...

引用

international symposium on high performance Distributed computing

作者： M. Kaddoura S. Ranka School of Computer and Information Science 2-120 Center for Science & Technology Syracuse University Syracuse NY USA

In this paper, we discuss the runtime support required for the parallelization of unstructured data-parallel applications on nonuniform and adaptive environments. the approach presented is reasonably general and is applicable to a wide variety of regular as well as irregular applications. We present performance results for the solution of an unstructured mesh on a cluster of heterogeneous workstations.

关键词： Concurrent computing Workstations Load management Application software Runtime environment Processor scheduling Information science computer networks Multiprocessor interconnection networks computer architecture

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Towards Web/Java-based high performance distributed computing-an evolving virtual machine 96

Towards Web/Java-based high performance distributed computin...

引用

international symposium on high performance Distributed computing

作者： G. Fox W. Furmanski Northeast Parallel Architectures Center Syracuse University Syracuse NY USA

ISBN: (纸本)9780818675829

Discusses the emergent World Wide Web-based distributed environments for high-performance computing and communications (HPCC) on the National Information Infrastructure (NII) with the focus on Java as an enabling technology. We start with a review of the past, present and near-term future of the "Java phenomenon", exposed in the background of some related previous approaches towards a distributed interpretative virtual machine architecture. Next, we discuss the anticipated role of Java in building distributed Web-based computing environments. We outline an evolutionary path from the current Web technology "soup" towards "all-Java" systems and we illustrate this process in terms of the Northeast Parallel architectures Center (NPAC) Web technology prototypes (WebVM, WebFlow, Bridge-based Collaboratory) and selected applications (CareWeb, 3D Visible Human).

关键词： Java Distributed computing high performance computing Virtual machining computer architecture Buildings Parallel architectures Prototypes Collaboration Humans

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A task migration implementation of the Message-Passing Interface

A task migration implementation of the Message-Passing Inter...

引用

international symposium on high performance Distributed computing

作者： J. Robinson S.H. Russ B. Flachs B. Heckel NSF Engineering Research Center for Computatiorial Field Simulation Mississippi State University USA MicroMagnetic Inc. Sunnyvale CA USA

In order to use networks of workstations in parallel processing applications, several schemes have been devised to allow processes on different, possibly heterogeneous, platforms to communicate with one another. the Message-Passing Interface (MPI) is one such scheme that allows for message-passing across different architectures. the MPI specification does not make provisions for the migration of a process between machines. this paper describes the work required to modify, an MPI implementation to allow for task migration. It also describes "Hector", our heterogeneous computing task allocator that is used to migrate tasks automatically and improve the overall performance of a parallel program.

关键词： Workstations Concurrent computing Parallel processing Parallel programming computer networks Computational modeling computer architecture Scientific computing Floating-point arithmetic Distributed computing

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