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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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CNI: a high-performance network interface for workstation clusters 96

CNI: a high-performance network interface for workstation cl...

引用

international symposium on high performance Distributed computing

作者： P. Sarkar M. Bailey University of Arizona Tucson AZ US Dept. of Comput. Sci. Arizona Univ. Tucson AZ USA

ISBN: (纸本)9780818675829

Networks of workstations provide an economic solution for scalable computing because they do not require specialized components. Even though recent advances have shown that it is possible to obtain high bandwidth between applications, interconnect latency remains a serious concern. We present CNI, a cluster network interface that not only provides both low latency and high bandwidth but also efficiently supports multiple programming paradigms. this is done by functionally coupling the network adaptor board more closely to the CPU without changing the standard workstation architecture. CNI results in performance gains for applications, substantially reducing communication overhead and delay.

关键词： Network interfaces Workstations Delay Bandwidth computer networks performance gain

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Employing logic-enhanced memory for high-performance ATM network interfaces 96

Employing logic-enhanced memory for high-performance ATM net...

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international symposium on high performance Distributed computing

作者： H. Agusleo N. Soparkar Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

ISBN: (纸本)9780818675829

With the advent of asynchronous transfer mode (ATM), network speeds are increasing substantially, and the greater communication bandwidth provides considerable potential for distributed applications. However, communication throughput delivered to the user applications has not increased as rapidly: network interfacing has become the next bottleneck. Consequently, better designs for network interfaces are essential to take full advantage of the higher-speed communication links such as the ATM. We present a novel hardware architecture for an ATM network interface employing memory with select on-chip data processing logic; i.e., logic-enhanced memory (LEM). We exhibit how LEM-based interfaces are particularly suitable for servers, where the majority of the operations are memory-intensive processing for client requests.

关键词： Network interfaces Asynchronous transfer mode Bandwidth Application software throughput computer networks Protocols Hardware Network-on-a-chip Logic

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Supporting HPDC applications over ATM networks with cell-based transport mechanisms 96

Supporting HPDC applications over ATM networks with cell-bas...

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international symposium on high performance Distributed computing

作者： J. Vila-Sallent J. Sole-Pareta Department of Computer Architecture Universitat Politecnica de Catalunya Catalonia Spain

ISBN: (纸本)9780818675829

We address the problem of supporting high performance distributed computing (HPDC) applications running over ATM networks. For this purpose, we consider a logically separate subnetwork for these applications. After presenting an architectural reference model for the HPDC subnetwork and distinguishing which functions should be installed over the ATM network in order to satisfy the needs of HPDC applications, we propose two mechanisms that aim at optimizing communications by taking advantage of both the special properties of HPDC traffic and the cell based nature of ATM. the performance of these mechanisms is evaluated and compared with that achieved by the SSCOP protocol. the results show that when the ATM network experiences high load and the HPDC applications make an intensive use of arrays, cell based mechanisms become more robust than standard SSCOP and provide low latency and efficient cell loss recovery. Since both situations are very likely to occur in HPDC environments, we conclude that the introduction of cell based retransmission mechanisms does contribute to enhance performance of HPDC systems over ATM networks.

关键词： Asynchronous transfer mode Workstations Application software Protocols Delay Distributed computing Costs Concurrent computing computer networks high-speed networks

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Prototyping network architectures on a supercomputer 96

Prototyping network architectures on a supercomputer

引用

international symposium on high performance Distributed computing

作者： M.C. Chan G. Pacifici R. Stadler Center for Telecommunications Research Columbia University New York NY USA T.J. Watson Research Center IBM Hawthorne NY USA

ISBN: (纸本)9780818675829

Outlines a methodology for developing network control systems which allows for an evaluation of the dynamic behavior and overall performance at an early stage of the development process. Our approach is to build a software prototype which is designed according to the architecture under consideration and runs the intended control algorithms. the functional and dynamic properties of this prototype are tested and evaluated on an emulation platform that we built for this purpose. By providing support for real-time visualization and interactive emulation, this platform can be used to study multimedia networks in various scenarios, such as different load patterns, network sizes and management operations. the current implementation runs on a KSR-1 and an SP2 parallel processor, which are connected to a graphics workstation via ATM links. We use the platform in several projects, one of which aims at developing an architecture for managing multimedia network services.

关键词： Prototypes Supercomputers Software prototyping computer architecture Emulation Control systems Algorithm design and analysis Software algorithms Testing Visualization

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A heterogeneous hierarchical solution to cost-efficient high performance computing

A heterogeneous hierarchical solution to cost-efficient high...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： Z.B. Miled J.A.B. Fortes Sch. of Electr. & Comput. Eng. Purdue Univ. West Lafayette IN USA School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

Two facts that suggest the desirability of a hierarchical approach to cost-effective high-performance computing are empirically established in this paper. the first fact is the temporal locality of programs with respect to the degree of parallelism. Two temporal (instruction and data) locality principles are identified and empirically established for a set of programs. the impact of this behavior is discussed with respect to the proposed heterogeneous multilevel architecture. the second fact that supports the hierarchical architecture is the cost-efficiency advantage of heterogeneous over homogeneous multiprocessor systems. An initial performance analysis is presented which quantifies this fact for the proposed heterogeneous hierarchical organization. the proposed multilevel processor configuration uses fast and costly resources sparingly to reduce sequential and low parallelism bottlenecks. the resulting organization tries to balance cost, speed and parallelism granularity.

关键词： high performance computing Parallel processing Concurrent computing Costs Bridges Multiprocessing systems Research and development Application software computer applications Environmental economics

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QUANTA: quality of service architecture for native TCP/IP over ATM networks 96

QUANTA: quality of service architecture for native TCP/IP ov...

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international symposium on high performance Distributed computing

作者： S. Dharanikota K. Maly Department of Computer Science Old Dominion University Norfolk VA USA

ISBN: (纸本)9780818675829

We propose a quality of service (QoS) architecture, QUANTA, for an end system protocol suite. We use TCP(UDP)/IP over ATM as a testbed to develop the architecture. We measure the application level QoS in terms of throughput, delay, round trip time, and loss to identify the base line performance an application can expect from such an environment. From the no-load condition we measure the behavior of these protocols at various data rates and user submitted data block sizes. We demonstrate the tradeoffs involved in obtaining high throughput, low delays, low round trip time, and zero losses at different data rates. We use host load condition experiments to understand the interaction between the CPU intensive jobs and the communication intensive jobs. We use network load condition experiments to observe interaction between multiple streams of the above two protocol suites, and its effect on the application QoS. Given these observations we define the missing components in the current protocol architectures to provide tighter control on the QoS guarantees. Components we define in QUANTA include a two level application to network QoS translator protocol tuning components, local feedback component, class based scheduling etc.

关键词： Quality of service TCPIP Protocols throughput Delay effects Testing Loss measurement Time measurement performance loss Size measurement

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Measurement and simulation based performance analysis of parallel I/O in a high-performance cluster system

Measurement and simulation based performance analysis of par...

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international symposium on Parallel and Distributed Processing (IPDPS)

作者： C. Natarajan R.K. Iyer Coordinated Science Laboratory University of Illinois Urbana-Champaign Urbana IL USA

this paper presents a measurement and simulation based study of parallel I/O in a high-performance cluster system: the Pittsburgh Supercomputing Center (PSC) DEC Alpha Supercluster. the measurements were used to characterize the performance bottlenecks and the throughput limits at the compute and I/O nodes, and to provide realistic input parameters to PioSim, a simulation environment we have developed to investigate parallel I/O performance issues in cluster systems. PioSim was used to obtain a detailed characterization of parallel I/O performance, in the high performance cluster system, for different regular access patterns and different system configurations. this paper also explores the use of local disks at the compute nodes for parallel I/O, and finds that the local disk architecture outperforms the traditional parallel I/O over remote I/O node disks architecture, even when as much as 68-75% of the requests from each compute node goes to remote disks.

关键词： Analytical models performance analysis Concurrent computing computer architecture Computational modeling throughput File systems Coordinate measuring machines high performance computing System performance

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TOP-C: a task-oriented parallel C interface 96

TOP-C: a task-oriented parallel C interface

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international symposium on high performance Distributed computing

作者： G. Cooperman Coll. of Comput. Sci. Northeastern Univ. Boston MA USA

ISBN: (纸本)9780818675829

the goal of this work is to simplify parallel application development, and thus ease the learning barriers faced by non-experts. It is especially useful where there is little data-parallelism to be recognized by a compiler. the applications programmer need learn the intricacies of only one primary subroutine in order to get the full benefits of the parallel interface. the applications programmer defines a high level concept, the task, that depends only on his application, and not on any particular parallel library. the task is defined by its three phases: (a) the task input, (b) sequential code to execute the task, and (c) any modifications of global variables that occur as a result of the task. In particular, side effects (which change global variable values) must not occur in phase (b). Forcing the user to re-organize his computation in these terms allows us to present the applications programmer with a single global environment visible to all processors (whether on a SMP or a NOW architecture), in the context of a masterslave architecture. Both a shared memory implementation (running on an SGI or SUN Solaris architecture) and a NOW memory implementation (running on top of MPI) are described. the implementations were tested by a naive program for integer factorization, and by a more sophisticated Todd-Coxeter coset enumeration. Integer factorization was chosen so as to exercise the major features of TOP-C in an unambiguous context.

关键词： Programming profession computer architecture Algorithms Libraries Sun Testing

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NYNET Communication System (NCS): a multithreaded message passing tool over ATM network 96

NYNET Communication System (NCS): a multithreaded message pa...

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international symposium on high performance Distributed computing

作者： Sung-Yong Park S. Hariri Yoonhee Kim J.S. Harris R. Yadav Northeast Parallel Architectures Center NPAC Department of Electrical and Computer Engineering Syracuse University Syracuse NY USA

ISBN: (纸本)9780818675829

Current advances in processor technology, and the rapid development of high speed networking technology, such as ATM, have made high performance network computing an attractive computing environment for large-scale high performance distributed computing (HPDC) applications. However, due to the communications overhead at the host-network interface, most of the HPDC applications are not getting the full benefit of high speed communication networks. this overhead can be attributed to the high cost of operating system calls, context switching, the use of inefficient communication protocols, and the coupling of data and control paths. We present an architecture and implementation for a low-latency, high-throughput message passing tool, that we refer to as the NYNET (ATM wide area network testbed in New York state) Communication System (NCS), which can support a variety of HPDC applications with different Quality of Services (QOS) requirements. NCS uses multithreading to provide efficient techniques that overlap computation and communication. NCS uses read/write trap routines to bypass traditional operating system calls. this reduces latency and avoids using inefficient communication protocols. By separating data and control paths, NCS eliminates unnecessary control transfers. this optimizes the data path and improves performance. Benchmarking results show that the performance of NCS is at least a factor of two better than the performance of corresponding p4 and PVM primitives.

关键词： Message passing Distributed computing Communication system control Asynchronous transfer mode computer networks high performance computing Operating systems Protocols high-speed networks Large-scale systems

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the core Legion object model 96

The core Legion object model

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international symposium on high performance Distributed computing

作者： M. Lewis A. Grimshaw Department of Computer Science University of Virginia Charlottesville VA USA University of Virginia Charlottesville VA US Dept. of Comput. Sci. Virginia Univ. Charlottesville VA USA

ISBN: (纸本)9780818675829

the Legion project at the University of Virginia is an architecture for designing and building system services that provide the illusion of a single virtual machine to users, a virtual machine that provides secure shared object and shared name spaces, application adjustable fault tolerance, improved response time, and greater throughput. Legion targets wide area assemblies of workstations, supercomputers, and parallel supercomputers. Legion tackles problems not solved by existing workstation based parallel processing tools; the system will enable fault tolerance, wide area parallel processing, interoperability, heterogeneity, a single global name space, protection, security, efficient scheduling, and comprehensive resource management. the paper describes the core Legion object model, which specifies the composition and functionality of Legion's core objects-those objects that cooperate to create, locate, manage, and remove objects in the Legion system. the object model facilitates a flexible extensible implementation, provides a single global name space, grants site autonomy to participating organizations, and scales to millions of sites and trillions of objects.

关键词： Virtual machining Fault tolerant systems Workstations Supercomputers Parallel processing Buildings Delay throughput Assembly Protection

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