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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Geyser: A Compilation Framework for Qantum computing with Neutral Atoms 49

Geyser: A Compilation Framework for Qantum Computing with Ne...

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49th ieee/ACM international symposium on computer architecture, ISCA 2022

作者： Patel, Tirthak Silver, Daniel Tiwari, Devesh Northeastern University Boston United States

ISBN: (纸本)9781450386104

Compared to widely-used superconducting qubits, neutral-atom quantum computing technology promises potentially better scalability and flexible arrangement of qubits to allow higher operation parallelism and more relaxed cooling requirements. the high performance computing (HPC) and architecture community is beginning to design new solutions to take advantage of neutral-atom quantum architectures and overcome its unique challenges. We propose Geyser, the frst work to take advantage of the multiqubit gates natively supported by neutral-atom quantum computers by appropriately mapping quantum circuits to three-qubit-friendly physical arrangement of qubits. then, Geyser creates multiple logical blocks in the quantum circuit to exploit quantum parallelism and reduce the number of pulses needed to realize physical gates. these circuit blocks elegantly enable Geyser to compose equivalent circuits with three-qubit gates, even when the original program does not have any multi-qubit gates. Our evaluation results show Geyser reduces the number of operation pulses by 25%-90% and improves the algorithm's output fdelity by 25%-60% points across different algorithms. © 2022 Copyright held by the owner/author(s). Publication rights licensed to ACM.

关键词： Qubits

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Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences

Improving Virtual Prototype Driven Hardware Optimization by ...

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ieee Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Jan Zielasko Rune Krauss Marcel Merten Rolf Drechsler Institute of Computer Science University of Bremen Bremen Germany Cyber-Physical Systems DFKI GmbH Bremen Germany

Tailoring hardware to an application significantly enhances its performance compared to using a general-purpose processor. While hardware optimization is essential to meet the user requirements for resource-constrained embedded systems, it generally entails considerable costs and a high level of effort. In recent work virtual prototypes have been shown to be an effective analysis tool for guiding this process. In best-case scenarios, it is possible to identify a single recurring instruction sequence that covers approximately 55 % of all executed instructions and is thus suitable for optimization by a Hardware Accelerator (HA). However, challenges arise for applications where each identified sequence only covers a small fraction of the total execution. In order to achieve comparable coverage, several HAs can be designed, but this also multiplies the hardware costs. To address these issues, this work proposes an approach to extend and merge identified sequences allowing the design of a single HA for the merged sequence. Experiments show that this approach significantly increases the coverage achievable with a single HA while the resulting performance loss is negligible compared to building multiple HAs.

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Is RISC-V ready for Space? A Security Perspective 35

Is RISC-V ready for Space? A Security Perspective

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35th ieee international symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022

作者： Cassano, Luca Mascio, Stefano Di Palumbo, Alessandro Menicucci, Alessandra Furano, Gianluca Bianchi, Giuseppe Ottavi, Marco Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Italy Department of Space Engineering Delft University of Technology Netherlands Dipartimento di Elettronica Ingegneria Dell Informazione Università Degli Studi di Roma Tor Vergata Italy European Space Agency Netherlands Faculty of Electrical Engineering Mathematics and Computer Science University of Twente Netherlands

ISBN: (数字)9781665459389

ISBN: (纸本)9781665459389

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. therefore, the adoption of Commercial-Off-the-Shelf (COTS) components and third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (Hths) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. the paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain. © 2022 ieee.

关键词： Space applications

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S-Clflush: Securing Against Flush-based Cache Timing Side-Channel Attacks

S-Clflush: Securing Against Flush-based Cache Timing Side-Ch...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Tejeshwar Bhagatsing thorawade Prajakta Yeola Varun Venkitaraman Virendra Singh Indian Institute of Technology Bombay India

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

Micro-architectural attacks exploit intrinsic vulnerabilities within computing systems, circumventing advanced security techniques such as cryptographic algorithms, access control policies, and secure enclaves. these attacks encompass a range of methodologies, including cache timing side-channel attacks like Flush+Reload, Flush+Flush, and Prime+Probe, as well as speculative execution attacks such as Spectre and Meltdown. these exploits leverage specific characteristics of micro-architecture to infer sensitive data, posing a significant threat to system security. Cache timing side-channel attacks exploit the inclusive nature of the last-level cache (LLC) to deduce the memory access patterns of victim processes. By observing the timing variations associated with cache hits and misses, attackers can extract confidential information, such as cryptographic keys. Although existing mitigation strategies provide a level of security, they typically do so at the expense of system performance and increased hardware. these trade-offs limit the practical applicability of such defences in performance-critical environments. this paper proposes S-Clflush: Secure Clflush, an innovative defence mechanism specifically designed to counter flush-based cache timing side-channel attacks. S-Clflush achieves this by modifying the existing clflush instruction to prevent attackers from inferring memory access patterns based on cache access latency. Unlike traditional mitigation techniques, S-Clflush enhances security without incurring performance degradation or additional area overhead. the proposed mechanism is formally verified to ensure its security guarantees. Our evaluation against the state-of-the-art mitigation technique TimeCache shows a 0.5% improvement in performance and a 58% reduction in MPKI on average without adding area overhead.

关键词： Degradation Prevention and mitigation System performance high performance computing Side-channel attacks computer architecture Hardware Timing Security Data mining

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To Protect or Not To Protect: Probability-Aware Selective Protection for Sparse Iterative Solvers

To Protect or Not To Protect: Probability-Aware Selective Pr...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Daniel Ryley Johnson Hongyang Sun Joshua Dennis Booth Padma Raghavan University of Kansas Lawrence KS USA University of Alabama in Huntsville Huntsville AL USA Vanderbilt University Nashville TN USA

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

With the increasing scale of high-performance computing (HPC) systems, transient bit-flip errors are now more likely than ever, posing a threat to long-running scientific applications. A substantial portion of these applications involve simulation of partial differential equations (PDEs), modeling physical processes over discretized spatial and temporal domains, with some requiring solving sparse linear systems of equations. While these applications are often paired with system-level application-agnostic resilience techniques, such as checkpointing and replication, using these techniques imposes significant overhead. In this work, we present a probability-aware framework that produces low-overhead selective protection schemes for the widely used Preconditioned Conjugate Gradient (PCG) method, whose performance can heavily degrade due to error propagation through the sparse matrix-vector multiplication (SpMV) operation. through the use of a straightforward mathematical model and an optimized machine learning model, our selective protection schemes incorporate error probability to protect only certain crucial operations. An experimental evaluation using 15 matrices from the SuiteSparse Matrix Collection demonstrates that our protection schemes effectively reduce resilience overheads, outperforming two baseline and two existing protection schemes across all error probabilities.

关键词： Linear systems Error probability high performance computing Partial differential equations Machine learning Mathematical models Sparse matrices Protection Transient analysis Resilience

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To Derive or Not to Derive: I/O Libraries Take Charge of Derived Quantities Computation

To Derive or Not to Derive: I/O Libraries Take Charge of Der...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Ana Gainaru Norbert Podhorszki Liz Dulac Qian Gong Scott Klasky Greg Eisenhauer Antonios Kougkas Xian-He Sun Jay Lofstead Oak Ridge National Laboratory Georgia Institute of Technology Illinois Institute of Technology Sandia National Laboratory

ISBN: (数字)9798350356168

ISBN: (纸本)9798350356175

the ever-increasing volume of data produced by HPC simulations necessitates scalable methods for data exploration and knowledge extraction. Scientific data analysis often involves complex queries across distributed datasets, requiring manipulation of multiple primary variables and generating derived data that needs to be handled efficiently, creating challenges for applications that need to parse many large datasets. Relying on individual applications to handle all intermediate data generally leads to redundant computations across studies and unnecessary data transfers. In this paper, we investigate the performance of different approaches where applications define derived variables as quantities of interest (QoIs) and offload the computation and transfer of these QoIs to the I/O library. this significantly reduces redundancy and optimizes data movement across the distributed storage and processing infrastructure by allowing control over when and where derived variables are computed. We present a detailed analysis of the performance-storage trade-offs associated with different solutions and showcase results for our study on two large-scale datasets created from climate and combustion simulations.

关键词： Analytical models Solid modeling Computational modeling high performance computing Redundancy Distributed databases Process control Libraries Data models Meteorology

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Confidential Serverless Made Efficient with Plug-In Enclaves 21

Confidential Serverless Made Efficient with Plug-In Enclaves

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ACM/ieee 48th Annual international symposium on computer architecture (ISCA)

作者： Li, Mingyu Xia, Yubin Chen, Haibo Shanghai Jiao Tong Univ Inst Parallel & Distributed Syst Shanghai AI Lab Shanghai Peoples R China

ISBN: (纸本)9781665433334

Serverless computing has become a fact of life on modern clouds. A serverless function may process sensitive data from clients. Protecting such a function against untrusted clouds using hardware enclave is attractive for user privacy. In this work, we run existing serverless applications in SGX enclave, and observe that the performance degradation can be as high as 5.6 x to even 422.6 x . Our investigation identifies these slowdowns are related to architectural features, mainly from page-wise enclave initialization. Leveraging insights from our overhead analysis, we revisit SGX hardware design and make minimal modification to its enclave model. We extend SGX with a new primitive-region-wise plugin enclaves that can be mapped into existing enclaves to reuse attested common states amongst functions. By remapping plugin enclaves, an enclave allows in-situ processing to avoid expensive data movement in a function chain. Experiments show that our design reduces the enclave function latency by 94.74-99.57%, and boosts the autoscaling throughput by 19-179 x.

关键词： Intel SGX Serverless Confidential computing

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performance Modeling of MARE2DEM's Adaptive Mesh Refinement for Makespan Estimation

Performance Modeling of MARE2DEM's Adaptive Mesh Refinement ...

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international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Bruno Da Silva Alves Lucas Mello Schnorr Graduate Program in Computer Science (PPGC) Institute of Informatics – UFRGS Porto Alegre Brazil

Adaptive Mesh Refinement (AMR) is a widely known technique to adapt the accuracy of a solution in critical areas of the problem domain instead of using regular or irregular but static meshes. the MARE2DEM is a parallel application that employs the AMR technique to model 2D electromagnetics in oil and gas exploration. the modeling consists in iteratively applying a data inversion based on a set of measurements collected and registered by a survey on an area of interest. the parallelism of the MARE2DEM works by dividing the workload into a set of refinement groups that represent overlapping areas of the problem domain. Each refinement group can be computed independently of the others by a set of workers, carrying out the AMR in the meshes when necessary. the shape and compute performance of the refinement group depend directly of a set of user-defined parameters. In this article, we provide a method to estimate the MARE2DEM performance for all possible values that can be used in the influencing parameters of the application for a given case study. Our relatively cheap method enables the geologist to configure MARE2DEM correctly and extract the best performance for a given cluster configuration. We detail how the method works and evaluate its effectiveness with success, pinpointing the best values for the creating refinement groups using a real case study from the Marlim field on the coast of Rio de Janeiro, Brazil. Although we demonstrate our evaluation with this scenario, our method works for any input of MARE2DEM.

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Two-Step Register Allocation for Implementing Single-Path Code

Two-Step Register Allocation for Implementing Single-Path Co...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Emad Jacob Maroun Martin Schoeberl Peter Puschner Institute of Computer Engineering TU Wien Vienna Austria Department of Applied Mathematics and Computer Science Technical University of Denmark Kongens Lyngby Denmark

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

Register allocation is a crucial step in the compilation pipeline that decides what program values occupy which physical registers. Single-path code’s use of predicated instructions instead of branching control-flow means register allocation must also allocate predicate registers. In this paper, we improve the original single-path transformation to allow generic register allocators to allocate predicate registers. Our improved transformation splits register allocation into two. First, the general-purpose registers are allocated as usual using a generic register allocator. then, the main steps of the single-path transformation are performed while still using virtual predicate registers. Lastly, register allocation is rerun using the generic allocator to allocate the predicate registers. Our results show the improved single-path transformation increasing performance by up to 80 % and reducing code size by up to 43 % compared to the original transformation that uses a custom predicate allocator.

关键词： Codes Pipelines Real-time systems Registers Resource management Distributed computing

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Multi-Link Failure Effects on MPLS Resilient Fast-Reroute Network architectures 24

Multi-Link Failure Effects on MPLS Resilient Fast-Reroute Ne...

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24th ieee international symposium on Real-Time Distributed computing (ISORC)

作者： Gray, Wayne Tsokanos, Athanasios Kirner, Raimund Univ Hertfordshire Cyber Secur Ctr Hatfield England

ISBN: (纸本)9781665404143

MPLS has been in the forefront of high-speed Wide Area Networks (WANs), for almost two decades [1, 12]. the performance advantages in implementing Multi-Protocol Label Switching (MPLS) are mainly its superior speed based on fast label switching and its capability to perform Fast Reroute rapidly when failure(s) occur - in theory under 50 ms [16, 17], which makes MPLS also interesting for real-time applications. We investigate the aforementioned advantages of MPLS by creating two real testbeds using actual routers that commercial Internet Service Providers (ISPs) use, one with a ring and one with a partial mesh architecture. In those two testbeds we compare the performance of MPLS channels versus normal routing, both using the Open Shortest Path First (OSPF) routing protocol. the speed of the Fast Reroute mechanism for MPLS when failures are occurring is investigated. Firstly, baseline experiments are performed consisting of MPLS versus normal routing. Results are evaluated and compared using both single and dual failure scenarios within the two architectures. Our results confirm recovery times within 50 ms.

关键词： Multiprotocol label switching Wide area networks Web and internet services Switches computer architecture Network architecture Routing

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