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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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All-Optical Reconfigurable Activation Function Based on Saturable Absorption

All-Optical Reconfigurable Activation Function Based on Satu...

引用

ieee international symposium on Quality Electronic Design

作者： Oceane Destras Felipe Gohring De Magalhaes Sébastien Le Beux Gabriela Nicolescu Département de génie informatique et génie logiciel Polytechnique Montreal Montreal QC Canada Department of Electrical and Computer Engineering Concordia University Montreal QC Canada

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

the development of optical neural networks (ONNs) has opened up new possibilities for high-speed and energy-efficient computing. However, the limited range of available optical activation functions poses a significant bottleneck. To address this, we propose an all-optical, reconfigurable activation function circuit based on semiconductor saturable absorber mirrors and Mach-Zehnder interferometers, capable of emulating activation functions such as ReLU, Sigmoid, and Tanh. the reprogrammability of the proposed design allows the same circuit to be reused for multiple tasks by dynamically adjusting the activation function, optimizing both space and energy efficiency in ONNs. through extensive testing, we have identified the most critical parameters of the optical activation function for effective training of ONNs. We demonstrate via numerical simulation that this optical activation function achieves competitive results for the performance of ONNs, reaching up to 98.5% accuracy on the MNIST dataset.

关键词： Integrated optics Training Optical interferometry Optical design Neural networks Optical computing computer architecture Optical fiber networks Nonlinear optics high-speed optical techniques

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Ternary-Valued Associative Processor Design

Ternary-Valued Associative Processor Design

引用

ieee international symposium on Quality Electronic Design

作者： Mira Hout Rouwaida Kanj Ahmed M. Eltawil Mohammed E. Fouda ECE Dept. American University of Beirut Lebanon Synopsys Inc Austin TX USA King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In-memory computing architectures have emerged as a promising solution to address the memory-wall bottleneck and enable efficient vectorized and parallel arithmetic operations. this paper proposes a hardware architecture and algorithms for ternary-valued associative processors (TAP) which is a critical step toward broadening their computational versatility. To facilitate the in-memory implementation of complex arithmetic and logic functions, we introduce an efficient methodology for the automatic generation of corresponding look-up tables (LUTs). A SPICE-MATLAB co-simulator is developed to evaluate the performance of the proposed TAP-based in-memory ternary adder in terms of energy consumption, computational delay, and area overhead. Comparative analysis demonstrates that the ternary AP adder achieves energy and area reductions of 11% and 6.2%, respectively, compared to its binary counterpart. Furthermore, compared to state-of-the-art ternary carry-lookahead adder, the proposed solution exhibits around 100x and 9.5x reduction in energy and delay, respectively. this work highlights the potential of in-memory and parallel computing processors to high-efficiency arithmetic operations, offering scalable and energy-efficient solutions for emerging computational workloads.

关键词： Energy consumption Program processors computer architecture Parallel processing In-memory computing Energy efficiency Delays Table lookup Adders Arithmetic

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Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems

Deep Neural Network Inference Partitioning in Embedded Hybri...

引用

ieee international symposium on Quality Electronic Design

作者： Fabian Kreß Julian Hoefer Qiushi Lin Patrick Schmidt Zhenhua Zhu Yu Zhu Tanja Harbaum Yu Wang Jürgen Becker Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Tsinghua University Beijing China

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Deep Neural Networks (DNNs) deployed in resource-constrained embedded systems, like automotive platforms, often face severe “memory wall” problems and energy-consuming data movements. To address this challenge, existing work has proposed Processing-In-Memory (PIM) architectures based on emerging non-volatile memory, which perform analog-domain computations inside memory, offering great potentials to solve the “memory wall” problem. However, PIM-based accelerators suffer from circuit noise, impacting DNN accuracy. therefore, building a heterogeneous multi-chiplet architecture based on energy-efficient analog PIM and high-precision digital computing units has become a promising DNN acceleration solution that achieves both high energy efficiency and high accuracy. In this paper, we present an automated framework to explore layer-wise DNN inference partitioning in hybrid analog-digital multi-chiplet systems. After performing a topological ordering, it analyzes the robustness of each layer to constrain mapping decisions across available analog PIM chiplets and digital chiplets. By considering several functional and performance metrics, the framework identifies Pareto-optimal partitioning schemes. Exten-sive experimental results on a variety of DNN models show a reduction in latency of up to 52% with a loss in accuracy of less than 1%.

关键词： Accuracy Quantization (signal) Chiplets architecture Scalability Artificial neural networks computer architecture Robustness Energy efficiency Analog-digital conversion

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HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy-Efficient Classification

HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy...

引用

ieee international symposium on Quality Electronic Design

作者： Ahmed Mamdouh Dayane Reis Computer Science and Engineering University of South Florida Tampa USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Hyperdimensional computing (HDC) processes information in a high-dimensional space, offering advantages over deep neural networks (DNNs), such as smaller model sizes, robustness to soft errors, and the capability for one/few-shot learning without significant accuracy drops in some applications. Although HDC shows great potential, encoding data into a hyperdimensional space poses challenges due to the significant data movement between processing units and memory in conventional architectures. Processing-in-memory (PIM) embeds computation directly within memory, reducing latency and energy consumption. Among PIM approaches, in-DRAM computation leverages the parallelism of DRAM to perform bulk bit-wise operations with high throughput. In this paper, we present HIDE, the first hyperdimensional in-DRAM encoder for fast and energy-efficient classification. HIDE integrates H DC encoding directly within commodity DRAM, significantly reducing energy consumption and improving system performance. HIDE achieves up to $272.8\times (23.3\times)$ encoding speedup over a CPU (GPU) during training, with energy reductions of 94.8% (95.0%) during training (inference). Integrating HIDE with the GPU achieves an overall system speedup of $15\times(7.2\times)$ during training (inference) compared to a GPU-only system, along with energy savings of 92.3% and 82.7%, respectively, for classification tasks with the MNIST, ISOLET, and UCHAR datasets.

关键词： Training Energy consumption Memory architecture Energy conservation Graphics processing units Random access memory throughput Encoding Energy efficiency Central Processing Unit

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MambaLiteSR: Image Super-Resolution with Low-Rank Mamba Using Knowledge Distillation

MambaLiteSR: Image Super-Resolution with Low-Rank Mamba Usin...

引用

ieee international symposium on Quality Electronic Design

作者： Romina Aalishah Mozhgan Navardi Tinoosh Mohsenin Department of Electrical and Computer Engineering Johns Hopkins University

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Generative Artificial Intelligence (AI) has gained significant attention in recent years, revolutionizing various applications across industries. Among these, advanced vision models for image super-resolution are in high demand, particularly for deployment on edge devices where real-time processing is crucial. However, deploying such models on edge devices is challenging due to limited computing power and memory. In this paper, we present MambaLiteSR, a novel lightweight image Super-Resolution (SR) model that utilizes the architecture of Vision Mamba. It integrates State Space Blocks and a reconstruction module for efficient feature extraction. To optimize efficiency without affecting performance, MambaLiteSR employs knowledge distillation, transferring essential information from a larger Mamba-based teacher model to a smaller student model through hyperparameter tuning. through a mathematical analysis of model parameters and their impact on the Peak Signal-to-Noise Ratio (PSNR), we identify key factors and adjust them accordingly. Our comprehensive evaluation shows that MambaLiteSR outperforms state of the art edge SR methods by reducing power consumption while maintaining competitive PSNR and SSIM scores across benchmark datasets such as Set5, Set14, and BSD100. It also reduces the power usage during training by adopting low-rank approximation. Moreover, MambaLiteSR reduces the total number of parameters without degrading performance, enabling the efficient deployment of generative AI models on resource-constrained devices. Deployment on the embedded NVIDIA Jetson Orin Nano confirms the superior balance of MambaLiteSR size, latency, and resource efficiency. the experimental results show that MambaLiteSR achieves performance comparable to both the baseline and other edge models while using 15% fewer parameters than the baseline. It also improves the power consumption by up to 58% compared to state-of-the-art SR edge models, all while maintaining low energy consumpt

关键词： performance evaluation Training Power demand PSNR Generative AI Image edge detection Computational modeling Superresolution Real-time systems Tuning

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Chasing Carbon: the Elusive Environmental Footprint of computing 27

Chasing Carbon: The Elusive Environmental Footprint of Compu...

引用

27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Gupta, Udit Kim, Young Geun Lee, Sylvia Tse, Jordan Lee, Hsien-Hsin S. Wei, Gu-Yeon Brooks, David Wu, Carole-Jean Harvard Univ Cambridge MA 02138 USA Facebook Inc Menlo Pk CA 94025 USA Arizona State Univ Tempe AZ USA

ISBN: (纸本)9781665422352

Given recent algorithm, software, and hardware innovation, computing has enabled a plethora of new applications. As computing becomes increasingly ubiquitous, however, so does its environmental impact. this paper brings the issue to the attention of computer-systems researchers. Our analysis, built on industry-reported characterization, quantifies the environmental effects of computing in terms of carbon emissions. Broadly, carbon emissions have two sources: operational energy consumption, and hardware manufacturing and infrastructure. Although carbon emissions from the former are decreasing thanks to algorithmic, software, and hardware innovations that boost performance and power efficiency, the overall carbon footprint of computer systems continues to grow. this work quantifies the carbon output of computer systems to show that most emissions related to modern mobile and data-center equipment come from hardware manufacturing and infrastructure. We therefore outline future directions for minimizing the environmental impact of computing systems.

关键词： Data center mobile energy carbon footprint

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BRIM: Bistable Resistively-Coupled Ising Machine 27

BRIM: Bistable Resistively-Coupled Ising Machine

引用

27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Afoakwa, Richard Zhang, Yiqiao Vengalam, Uday Kumar Reddy Ignjatovic, Zeljko Huang, Michael Univ Rochester Dept Elect & Comp Engn Rochester NY 14627 USA

ISBN: (纸本)9781665422352

Physical Ising machines rely on nature to guide a dynamical system towards an optimal state which can be read out as a heuristical solution to a combinatorial optimization problem. Such designs that use nature as a computing mechanism can lead to higher performance and/or lower operation costs. Quantum annealers are a prominent example of such efforts. However, existing Ising machines are generally bulky and energy intensive. Such disadvantages may be acceptable if these designs provide some significant intrinsic advantages at a much larger scale in the future, which remains to be seen. But for now, integrated electronic designs of Ising machines allow more immediate applications. We propose one such design that uses bistable nodes, coupled with programmable and variable strengths. the design is fully CMOS compatible for on-chip applications and demonstrates competitive solution quality and significantly superior execution time and energy.

关键词： Ising machine optimization CMOS accelerators nature-based computing quantum annealing

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COMET: Client-Oriented METadata Service for highly Available Distributed File Systems 27

COMET: Client-Oriented METadata Service for Highly Available...

引用

ieee 27th international symposium on computer architecture and high performance computing

作者： Xue, Ruini Ao, Lixiang Guan, Zhongyang Univ Elect Sci & Technol China Sch Engn & Comp Sci Chengdu Peoples R China

ISBN: (纸本)9781467380119

highly available metadata services of distributed file systems are essential to cloud applications. However, existing highly available metadata designs lack client-oriented features that treat metadata discriminately, leading to a single metadata fault domain and low availability. After investigating the workload characteristics of Hadoop, we propose Client-Oriented METadata (COMET), a novel highly available metadata service design that divides and distributes metadata into independent regions in terms of clients. these regions are isolated fault domains inherently, and failures in one region will not break file operations in other regions. A prototype of COMET was implemented based on HDFS, and the experimental results show that COMET can significantly improve metadata availability of HDFS without obvious performance degradation. It can also deliver scalable performance and faster metadata recovery due to its decentralized architecture.

关键词： Distributed Storage File System Metadata high Availability Hadoop HDFS

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Non-stationary simulation of computer systems and dynamic performance evaluation: a concern-based approach and case study on cloud computing 27

Non-stationary simulation of computer systems and dynamic pe...

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ieee 27th international symposium on computer architecture and high performance computing

作者： Pereira, Lourenco A., Jr. Mamani, Edwin L. C. Santana, Marcos J. Santana, Regina H. C. Nobile, Pedro Northon Monaco, Francisco Jose Univ Sao Paulo Dept Sistemas Comp Sao Carlos SP Brazil Inst Fed Sao Paulo Dept Informat Sao Carlos SP Brazil Univ Sao Paulo Dept Sist Comp Sao Carlos SP Brazil

ISBN: (纸本)9781467380119

this paper introduces an approach to the design of discrete event simulation experiments aimed at transient performance analysis. Specially in complex, multi-tier applications, the net effects of small delays introduced by buffers, IO operations, communication latency and averaged measurements, may result in significant inertia along the input-output path. In order to bring out these dynamic properties, the simulation experiment should excite the system with non-stationary workload under controlled conditions. the work discusses on the dynamic properties of large-scale distributed computer systems and how these may impact delivered performance. these rationales are explored to motivate a concern-based architecture which captures the elicited requirements. the design approach is systematic formulated and illustrated by a case study on extending a well-known cloud computing simulation framework to meet the aimed features. Experimental results of ongoing work are also addressed.

关键词： Cloud computing performance Evaluation Quality of Service

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Ascend: a Scalable and Unified architecture for Ubiquitous Deep Neural Network computing 27

Ascend: a Scalable and Unified Architecture for Ubiquitous D...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Liao, Heng Tu, Jiajin Xia, Jing Liu, Hu Zhou, Xiping Yuan, Honghui Hu, Yuxing Huawei Shenzhen Peoples R China

ISBN: (纸本)9781665422352

Deep neural networks (DNNs) have been successfully applied to a great variety of applications, ranging from small IoT devices to large scale services in a data center. In order to improve the efficiency of processing these DNN models, dedicated hardware accelerators are required for all these scenarios. theoretically, there exists an optimized acceleration architecture for each application. However, considering the cost of chip design and corresponding tool-chain development, researchers need to trade off between efficiency and generality. In this work, we demonstrate that it is practical to use a unified architecture, called Ascend, to support those applications, ranging from IoT devices to data-center services. We provide a lot of design details to explain that the success of Ascend relies on contributions from different levels. First, heterogeneous computing units are employed to support various DNN models. And the datapath is adapted according to the requirement of computing and data access. Second, when scaling the Ascend architecture from a single core to a cluster containing thousands of cores, it involves design efforts, such as memory hierarchy and system level integration. third, a multi-tier compiler, which provides flexible choices for developers, is the last critical piece. Experimental results show that using accelerators based on the Ascend architecture can achieve comparable or even better performance in different applications. In addition, various chips based on the Ascend architecture have been successfully commercialized. More than 100 million chips have been used in real products.

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