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LUTIC: A CRAM-based architecture for Power Failure Resilient In-Memory computing

LUTIC: A CRAM-based Architecture for Power Failure Resilient...

引用

ieee Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Khakim Akhunov Kasim Sinan Yildirim Department of Information Engineering and Computer Science University of Trento Italy

Processing In-Memory (PIM) based on emerging non-volatile memory technologies can accelerate machine learning tasks even for batteryless devices operating intermittently. However, existing PIM solutions for intermittent systems offer limited parallelism and do not support a high degree of programmability. this paper presents LUTIC —a novel architecture that can accelerate a broader class of intermittent data-intense operations. Our results demonstrate that, compared to existing commercial low-energy accelerators and PIM solutions for intermittent computing, LUTIC improves performance and energy efficiency with better parallelism support.

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Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics 21

Albireo: Energy-Efficient Acceleration of Convolutional Neur...

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ACM/ieee 48th Annual international symposium on computer architecture (ISCA)

作者： Shiflett, Kyle Karanth, Avinash Bunescu, Razvan Louri, Ahmed Ohio Univ Athens OH 45701 USA Univ N Carolina Charlotte NC USA George Washington Univ Washington DC 20052 USA

ISBN: (纸本)9781665433334

With the end of Dennard scaling, highly-parallel and specialized hardware accelerators have been proposed to improve the throughput and energy-efficiency of deep neural network (DNN) models for various applications. However, collective data movement primitives such as multicast and broadcast that are required for multiply-and-accumulate (MAC) computation in DNN models are expensive, and require excessive energy and latency when implemented with electrical networks. this consequently limits the scalability and performance of electronic hardware accelerators. Emerging technology such as silicon photonics can inherently provide efficient implementation of multicast and broadcast operations, making photonics more amenable to exploit parallelism within DNN models. Moreover, when coupled with other unique features such as low energy consumption, high channel capacity with wavelength-division multiplexing (WDM), and high speed, silicon photonics could potentially provide a viable technology for scaling DNN acceleration. In this paper, we propose Albireo, an analog photonic architecture for scaling DNN acceleration. By characterizing photonic devices such as microring resonators (MRRs) and Mach-Zehnder modulators (MZM) using photonic simulators, we develop realistic device models and outline their capability for system level acceleration. Using the device models, we develop an efficient broadcast combined with multicast data distribution by leveraging parameter sharing through unique WDM dot product processing. We evaluate the energy and throughput performance of Albireo on DNN models such as ResNet18, MobileNet and VGG16. When compared to current state-of-the-art electronic accelerators, Albireo increases throughput by 110X, and improves energy-delay product (EDP) by an average of 74 X with current photonic devices. Furthermore, by considering moderate and aggressive photonic scaling, the proposed Albireo design shows that EDP can be reduced by at least 229 X.

关键词： optical computing silicon photonics hardware acceleration deep neural networks

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A Solution for Conference Room Cluster Audio System Based on Distributed architecture

A Solution for Conference Room Cluster Audio System Based on...

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ACIS international Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)

作者： Xiaoyi Xu Xin Zhang Zenglai Wei School of Music and Recording Arts Communication University of China Beijing China School of Computer and Cyber Sciences Communication University of China Beijing China

ISBN: (数字)9798350391954

ISBN: (纸本)9798350391961

With the rapid development of information technology, people have put forward higher requirements for the audio-visual experience and usage functions of conference spaces. the traditional, single-function conference room configuration can no longer adapt to the diverse needs of modern work and interactive activities. How to achieve efficient management and control, seamless interconnection, and resource sharing of audio systems across spaces, while ensuring the acoustic characteristics and flexibility of each independent space, has become a core issue that needs to be urgently resolved in building a multi-hall, multifunctional conference room cluster. Based on the audio system project of the Academic Center of the Communication University of China, this paper proposes a solution for a conference room cluster audio system based on a distributed architecture. this solution not only overcomes the limitations of traditional systems in terms of scalability, collaborative work, and resource scheduling but also promotes lossless transmission, real-time processing, and adaptive configuration of audio signals. thus, it ensures the consistency and high quality of the audio experience within the entire cluster, providing practical guidance for the design and optimization of future conference room audio systems.

关键词： Technological innovation Federated learning Audio systems Scalability computer architecture Aerospace electronics Propagation losses

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A Review of Dynamic RRA Techniques on 5G And Beyond Mobile Networks

A Review of Dynamic RRA Techniques on 5G And Beyond Mobile N...

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ACIS international Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)

作者： Boikobo Nokane Bassey Isong Moshe Masonta Computer Science Dept. & UDSC North-West University Mafikeng and Council for Scientific and Industrial Research (CSIR) South Africa Computer Science Dept. & UDSC North-West University Mafikeng South Africa Council for Scientific and Industrial Research (CSIR) Pretoria South Africa

ISBN: (数字)9798350391954

ISBN: (纸本)9798350391961

the 5G mobile network aims to enhance wireless communication by providing faster and reliable connectivity. Open radio access network (RAN) architecture, which offers flexibility and innovation in Radio Resource Allocation (RRA), is central for optimal network performance. However, traditional RRA methods fall short of meeting the complex demands of 5G due to scalability issues. Incorporating machine learning (ML) techniques into open RAN can enhance adaptability and intelligence, ensuring that 5G networks meet high performance and service quality standards. this paper presents a comprehensive review of ML-based and traditional RRA methods in meeting the evolving demands of wireless networks. Literature from relevant articles were selected and analysed to highlight the techniques used, trends, strengths, and limitations. the findings reveal the potential and transformative impact of ML on the future of wireless communications, particularly in achieving the key performance indicators and quality of service expected from 5G and beyond networks. It also shows that research in ML-based RRA methods is at its infancy stage and more research is needed to advance the technology.

关键词： Technological innovation 5G mobile communication Reviews Wireless networks Scalability Software algorithms Open RAN

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Progressive Evolution Scheme with Socialization Swarm for Privacy Blockchain

Progressive Evolution Scheme with Socialization Swarm for Pr...

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Pacific Rim international symposium on Dependable computing

作者： Daoqi Han Tao Yu Yueming Lu Key Laboratory of Trustworthy Distributed Computing and Service Ministry of Education Beijing University of Posts and Telecommunications Beijing China Institute of Network Science and Cyberspace Tsinghua University Beijing China

To enhance the dependability of lightweight blockchain, this paper presents a privacy protection mechanism in open networks with a secure ledger for each cell of society. We propose a swarm intelligence scheme called hierarchical RAFT (HRAFT), which accumulates valuable workloads about the credibility of all the nodes to sort for selecting candidates. thus, the scheme achieves high-performance decentralization by progressive evolution consensus.

关键词： Privacy Schedules Blockchains Particle swarm optimization

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Analysis and Design of a Compute-in-Memory System for Epileptic Seizure Detection System

Analysis and Design of a Compute-in-Memory System for Epilep...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Mobeen Gulfaraz Sam Johnson Wala Saadeh Electrical Engineering Dept. Lahore University of Management Sciences (LUMS) Lahore Pakistan Engineering and Design Dept. Western Washington University (WWU) Bellingham WA USA

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

this paper presents an area and power-efficient design of a dual-channel electroencephalogram (EEG) based digital processor that can identify the onset of seizures with high accuracy. Multiple modules, including feature extraction and classification, constitute the hardware design. Neural networks are employed as classifiers because of their exceptional performance. these networks are data-driven algorithms that cause the system's performance to deteriorate and its power consumption to increase. A compute-in-memory (CIM) architecture has thus been used to address this problem. the performance of the neural network algorithm is evaluated using an open-source database of CHBMIT with 87.1% accuracy, 91.2% sensitivity, and 90.5% specificity. In contrast, the performance of hardware architecture was evaluated using its power, area, and latency. the synthesis and implementation were carried out using the 0.18µm CMOS process. A comparison of two architectures, the fixed point neural network architecture and the CIM neural network architecture, clearly indicated that the CIM processor performed significantly better in terms of power and area while sacrificing latency because of bit serial computing. To detect seizures in real-time, the CIM processor consumes 241µJ/classification while the fixed-point neural network consumes 256µJ/classification of energy.

关键词： Accuracy Sensitivity Neural networks computer architecture In-memory computing Feature extraction Hardware

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Finer-LRU: A Scalable Page Management Scheme for HPC Manycore architectures 35

Finer-LRU: A Scalable Page Management Scheme for HPC Manycor...

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35th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Bang, Jiwoo Kim, Chungyong Kim, Sunggon Chen, Qichen Lee, Cheongjun Byun, Eun-Kyu Lee, Jaehwan Eom, Hyeonsang Seoul Natl Univ Dept Comp Sci & Engn Seoul South Korea Korea Aerosp Univ Dept Elect & Informat Engn Goyang South Korea Korea Inst Sci & Technol Informat Div Natl Supercomp Daejeon South Korea

ISBN: (纸本)9781665440660

In HPC systems, the increasing need for a higher level of concurrency has led to packing inure cores within a single chip. However, since multiple processes share memory space, the frequent access to resources in critical sections where only atomic operation has to be executed can result in poor performance. In this paper, we focus on reducing lock contention on the memory management system of an HPC manycore architecture. One of the critical sections causing severe lock contention in the I/O path is in the page management system, which uses multiple Least Recently Used (LRU) lists with a single lock instance. To solve this problem, we propose a Finer-LRU scheme, which optimizes the page reclamation process by splitting LRU lists into multiple sub-lists, each having its own lock instance. Our evaluation result shows that the Finer-LRU scheme can improve sequential write throughput by 57.93% and reduce latency by 98.94% compared to the baseline Linux kernel version 5.2.8 in the Intel Knights Landing (KNL) architecture.

关键词： high performance computing Manycore architecture Page reclamation process Fine-grained lock

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Mosaic: Harnessing the Micro-Architectural Resources of Servers in Serverless Environments

Mosaic: Harnessing the Micro-Architectural Resources of Serv...

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ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Jovan Stojkovic Esha Choukse Enrique Saurez Íñigo Goiri Josep Torrellas University of Illinois at Urbana-Champaign Microsoft Azure Research - Systems

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

With serverless computing, users develop scalable applications using lightweight functions as building blocks, while cloud providers own most of the computing stack, allowing for better resource optimizations. In this paper, we observe that modern server-class processors are inefficiently utilized in serverless environments. Cores perform frequent context switches within function invocations and have a high degree of oversubscription. In such an environment, functions frequently lose their micro-architectural state in stateful hardware structures like caches, TLBs, and branch predictors, causing performance degradation. At the same time, modern processors are dimensioned for the needs of a broad set of applications, rendering them suboptimal for serverless workloads. Based on these insights, we propose Mosaic, an architecture optimized for serverless environments that maintains generality to efficiently support other workloads. Mosaic has two components: (1) MosaicCPU, a processor architecture that efficiently runs both serverless workloads and traditional monolithic applications, and (2) MosaicScheduler, a software stack for serverless systems that maximizes the benefits of MosaicCPU. MosaicCPU slices micro-architectural structures into small chunks and assigns tiles of such chunks to functions. the processor retains the state of functions in their tiles across context switches, thereby improving performance. Furthermore, currently-inactive tiles are set to a low power mode, thereby reducing energy consumption. In addition, MosaicScheduler maximizes efficiency by introducing predictive right-sizing of the per-function tiles, alongside with smart scheduling based on the state of the tiles. Overall, compared to conventional server-class processors, Mosaic improves the throughput of serverless workloads by 225% while using 22% less power.

关键词： Context Schedules Program processors Processor scheduling Full stack Serverless computing computer architecture throughput Rendering (computer graphics) Optimization

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All-Optical Reconfigurable Activation Function Based on Saturable Absorption

All-Optical Reconfigurable Activation Function Based on Satu...

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ieee international symposium on Quality Electronic Design

作者： Oceane Destras Felipe Gohring De Magalhaes Sébastien Le Beux Gabriela Nicolescu Département de génie informatique et génie logiciel Polytechnique Montreal Montreal QC Canada Department of Electrical and Computer Engineering Concordia University Montreal QC Canada

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

the development of optical neural networks (ONNs) has opened up new possibilities for high-speed and energy-efficient computing. However, the limited range of available optical activation functions poses a significant bottleneck. To address this, we propose an all-optical, reconfigurable activation function circuit based on semiconductor saturable absorber mirrors and Mach-Zehnder interferometers, capable of emulating activation functions such as ReLU, Sigmoid, and Tanh. the reprogrammability of the proposed design allows the same circuit to be reused for multiple tasks by dynamically adjusting the activation function, optimizing both space and energy efficiency in ONNs. through extensive testing, we have identified the most critical parameters of the optical activation function for effective training of ONNs. We demonstrate via numerical simulation that this optical activation function achieves competitive results for the performance of ONNs, reaching up to 98.5% accuracy on the MNIST dataset.

关键词： Integrated optics Training Optical interferometry Optical design Neural networks Optical computing computer architecture Optical fiber networks Nonlinear optics high-speed optical techniques

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SOPHGO BM1684X: A Commercial high performance Terminal AI Processor with Large Model Support

SOPHGO BM1684X: A Commercial High Performance Terminal AI Pr...

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ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Peng Gao Yang Liu Jun Wang Wanlin Cai Guangchong Shen Zonghui Hong Jiali Qu Ning Wang State Key Laboratory of Networking and Switching Technology Beijing University of Posts and Telecommunications Beijing China SOPHGO TECHNOLOGIES PTE. LTD. Beijing China

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

this paper presents BM1684X, a cutting-edge AI processor from SOPHGO designed to meet the demanding requirements of broad AI applications. Firstly, we employ SIMD architecture with very large data width to design our TPU to reduce the area ratio of the instruction unit and greatly improves the computing power density. Secondly, the customization of special acceleration instructions within the EU enables the dynamic pipeline execution, leading to a reduction in the total number of instructions and execution time. this customization enhances the performance of TPU in processing RQ and DQ operations, crucial for AI computations. thirdly, the CUBE array within the TPU implements the multiplication and addition operations of 64 pairs of INT8 operands in the channel dimension of the feature map. By utilizing an addition tree instead of a conventional adder, the implementation significantly reduces both area and power consumption, optimizing the efficiency of TPU. Additionally, the BM1684X processor incorporates a 64-input, 64-output, 8-bit crossbar within the lane, facilitating high-performance data gathering. this crossbar design enhances data gathering capabilities, enabling efficient data processing and manipulation within the TPU architecture. Furthermore, BM1684X offers three distinct memory access modes, showing the processor's versatility in addressing a wide range of AI processing needs and optimizing DRAM utilization for various tasks and workloads. Finally, we design a TPU-MLIR toolchain, highlighting its rich features such as unified processing of multiple frameworks, hierarchical design of model abstractions, correctness guarantees, and traceability of each transformation step. BM1684X excels in providing high-performance computing for a variety of AI models including large models, demonstrating its capabilities through comprehensive evaluations with industry-leading peers.

关键词： Power system measurements Power demand Microarchitecture Single instruction multiple data Computational modeling high performance computing Pipelines Random access memory computer architecture Artificial intelligence

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