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COMPASS: SRAM-Based computing-in-Memory SNN Accelerator with Adaptive Spike Speculation

COMPASS: SRAM-Based Computing-in-Memory SNN Accelerator with...

引用

ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Zongwu Wang Fangxin Liu Ning Yang Shiyuan Huang Haomin Li Li Jiang Department of Computer Science and Engineering Shanghai Jiao Tong University Shanghai Qi Zhi Institute MoE Key Lab of Artificial Intelligence AI Institute Shanghai Jiao Tong University

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Brain-inspired spiking neural networks (SNNs) are considered energy-efficient alternatives to conventional deep neural networks (DNNs). By adopting event-driven information processing, SNNs can significantly reduce the computational demands associated with DNNs, while still achieving comparable performance. However, current SNNs primarily prioritize high accuracy by constructing complex neuron models that generate sparse spikes. Unfortunately, this approach results in low energy efficiency and high latency, posing a significant challenge for deploying SNNs at the edge. Furthermore, the dominant computation in SNNs, which involves spike-wise Accumulate-Compare operations, is well-suited for computing-in-Memory (CIM) architectures. However, exploiting high parallel processing and spike sparsity in CIM-based SNN accelerators is challenging due to the irregularity and time dependency of spikes. To address these limitations, the paper proposes COMPASS, a SRAM-based CIM architecture for efficient SNNs. We first introduce an efficient method to exploit irregular sparsity for both input spikes (explicit) and output spikes (implicit). this is achieved through a speculation mechanism that exploit dynamic spike patterns, enabling lean hardware for sparsity utilization. Additionally, the CIM architecture is carefully modified to facilitate dynamic spike pattern generation and exploitation with minimal overhead. Moreover, we design an adaptive dataflow with temporal spike representation tailored for input/output spikes, reducing memory footprint and enabling parallel execution. Comprehensive evaluation results demonstrate that COMPASS can achieve 26.7x end-to-end speedup over recent SNN accelerators hardware implementation with up to 386.7x less energy per inference.

关键词： Accuracy Neurons computer architecture Spiking neural networks Parallel processing In-memory computing Energy efficiency Hardware Spatiotemporal phenomena Compass

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Cambricon-Q: A Hybrid architecture for Efficient Training 21

Cambricon-Q: A Hybrid Architecture for Efficient Training

引用

ACM/ieee 48th Annual international symposium on computer architecture (ISCA)

作者： Zhao, Yongwei Liu, Chang Du, Zidong Guo, Qi Hu, Xing Zhuang, Yimin Zhang, Zhenxing Song, Xinkai Li, Wei Zhang, Xishan Li, Ling Xu, Zhiwei Chen, Tianshi Chinese Acad Sci Inst Comp Technol SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Cambricon Tech Ltd Beijing Peoples R China Chinese Acad Sci Inst Software Beijing Peoples R China

ISBN: (纸本)9781665433334

Deep neural network (DNN) training is notoriously time-consuming, and quantization is promising to improve the training efficiency with reduced bandwidth/storage requirements and computation costs. However, state-of-the-art quantized algorithms with negligible training accuracy loss, which require on-the-fly statistic-based quantization over a great amount of data (e.g., neurons and weights) and high-precision weight update, cannot be effectively deployed on existing DNN accelerators. To address this problem, we propose the first customized architecture for efficient quantized training with negligible accuracy loss, which is named as Cambricon-Q. Cambricon-Q features a hybrid architecture consisting of an ASIC acceleration core and a near-data-processing (NDP) engine. the acceleration core mainly targets at improving the efficiency of statistic-based quantization with specialized computing units for both statistical analysis (e.g., determining maximum) and data reformating, while the NDP engine avoids transferring the high-precision weights from the off-chip memory to the acceleration core. Experimental results show that on the evaluated benchmarks, Cambricon-Q improves the energy efficiency of DNN training by 6.41x and 1.62x, performance by 4.20x and 1.70x compared to CPU and TPU, respectively, with only <= 0.4% accuracy degradation compared with full precision training.

关键词： Training Quantization (signal) Statistical analysis Neurons Memory management Graphics processing units computer architecture

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HIE-DRAM: high performance Efficient In-DRAM computing architecture for SIMD

HIE-DRAM: High Performance Efficient In-DRAM Computing Archi...

引用

ieee international symposium on Quality Electronic Design

作者： Mayank Kabra Prashanth H C Kedar Deshpande Madhav Rao IIIT Bangalore Bangalore India

In-memory and near-memory computing allows for placing the processing elements around the periphery or inside the memory blocks. Performing the computation as soon as the data is made available in the memory sub-blocks avoids the need to wait for the processor to manage the data movement. the paper focuses on a new 11 transistor (11T) computing design and a novel operation with energy savings and performance improvement when compared to the current state-of-the-art (SOTA) available single-instruction- multiple-data in-DRAM (SIMDRAM) computing. the novel 11T pass transistor design is structured to offer logical AND, OR, XNOR and its complement operations. these are sequenced to generate desired operational output with a minuscule change of 4 row circuitry that corresponds to footprint expense of 0.05% when compared to the existing DRAM architecture. Based on these logical operations, 13 scalar instructions covering arithmetic, predication, reduction, and relational function types are characterized. these scalar operations is a mix of logarithmic, quadratic, and linear functions applied on either a single or multiple operand. With respect to single-instruction- multiple-data (SIMD) topology, vector operations comprising addition, multiplication, sparse multiplication, selection, unique, reduction, and prefix summation are also realized. All these operations were compared with the current SOTA SIMDRAM architectural design to showcase profound computing time benefits and energy savings. the proposed 11T in-DRAM-compute design offers 5.18% to 50.57% improvement in computing latency and energy across 10 scalar operations, over SIMDRAM architecture. the novel high performance and efficient in-DRAM computing (HIE-DRAM) implementation is a step towards utilizing real-time in-memory vector data processing for autonomous applications.

关键词： Technological innovation Sensitivity Microprocessors Random access memory computer architecture Real-time systems Topology

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Ternary-Valued Associative Processor Design

Ternary-Valued Associative Processor Design

引用

ieee international symposium on Quality Electronic Design

作者： Mira Hout Rouwaida Kanj Ahmed M. Eltawil Mohammed E. Fouda ECE Dept. American University of Beirut Lebanon Synopsys Inc Austin TX USA King Abdullah University of Science and Technology (KAUST) Thuwal Saudi Arabia Rain Neuromorphics Inc. San Francisco CA USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

In-memory computing architectures have emerged as a promising solution to address the memory-wall bottleneck and enable efficient vectorized and parallel arithmetic operations. this paper proposes a hardware architecture and algorithms for ternary-valued associative processors (TAP) which is a critical step toward broadening their computational versatility. To facilitate the in-memory implementation of complex arithmetic and logic functions, we introduce an efficient methodology for the automatic generation of corresponding look-up tables (LUTs). A SPICE-MATLAB co-simulator is developed to evaluate the performance of the proposed TAP-based in-memory ternary adder in terms of energy consumption, computational delay, and area overhead. Comparative analysis demonstrates that the ternary AP adder achieves energy and area reductions of 11% and 6.2%, respectively, compared to its binary counterpart. Furthermore, compared to state-of-the-art ternary carry-lookahead adder, the proposed solution exhibits around 100x and 9.5x reduction in energy and delay, respectively. this work highlights the potential of in-memory and parallel computing processors to high-efficiency arithmetic operations, offering scalable and energy-efficient solutions for emerging computational workloads.

关键词： Energy consumption Program processors computer architecture Parallel processing In-memory computing Energy efficiency Delays Table lookup Adders Arithmetic

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Multi-Criteria Optimization of Distributed Real-Time Network Topologies

Multi-Criteria Optimization of Distributed Real-Time Network...

引用

international symposium on Object-Oriented Real-Time Distributed computing

作者： Florient Champenois Florian Brandner thierry Grandpierre Etienne Borde Abraham Suissa Laurent Georges Research and Technology Safran Electronics and Defenses Massy France LTCI Télécom Paris Institut Polytechnique de Paris Palaiseau France LIGM Univ Gustave Eiffel CNRS Marne-la-Vallée France Computer Science and Software Eng. Dept University of Canterbury Christchurch New Zealand

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

Communication needs in avionics and transportation have radically changed over the recent years. Traditionally, the underlying hard real-time networks were designed in a centralized way, focusing on redundancy and isolation. Today, real-time communication is ubiquitous, from large airplanes to small vehicles. the associated networks must support a wide range of applications, and large amounts of data. Centralized approaches from the avionics domain, e.g., AFDX, are too costly, too heavyweight, and not flexible enough for these *** this paper we explore a new distributed network architecture designed to support jumbo airliners, but also small aircraft and drones. Communication redundancy is achieved using redundant paths, which have to be adapted and optimized to the application. the main challenge then is to build an optimized network configuration ensuring safety, fault tolerance, timing, and performance of both critical, and non-critical communication. Minimizing volume and weight of the equipment is also mandatory. Since the solution space is too large to be explored in reasonable time, we propose a genetic algorithm. Our experiments show that our algorithm converges quickly and offers solutions of excellent quality. the computed solutions are in the top 2% among the best solutions obtained using an exhaustive exploration. Our approach thus enables system engineers to quickly explore and choose very good solution for their systems.

关键词： Redundancy Fault tolerant systems Transportation Stars Aerospace electronics Real-time systems Topology

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UFC: A Unified Accelerator for Fully Homomorphic Encryption

UFC: A Unified Accelerator for Fully Homomorphic Encryption

引用

ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Minxuan Zhou Yujin Nam Xuan Wang Youhak Lee Chris Wilkerson Raghavan Kumar Sachin Taneja Sanu Mathew Rosario Cammarota Tajana Rosing Illinois Institute of Technology University of California San Diego Intel Labs

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Fully homomorphic encryption (FHE) is crucial for post-quantum privacy-preserving computing. Researchers have proposed various FHE schemes that excel at different encrypted computations, such as single-instruction multiple-data (SIMD) arithmetic or arbitrary single-data functions. Hybrid-scheme FHE, which exploits appropriate schemes for specific tasks, is essential for real-world applications requiring optimal performance and accuracy. However, existing FHE accelerators only adopt scheme-specific custom designs, leading to inefficiency or lack of capability to support applications in hybrid FHE settings. In this work, we propose a Unified FHE aCcelerator (UFC) that provides better performance and cost-efficiency than prior scheme-specific accelerators on hybrid FHE applications. Our design process involves a comprehensive analysis of processing flows to abstract the primitives covering all operations in hybrid FHE applications. the UFC architecture primarily comprises hardware function units for these primitives, diverging from the deeply pipelined units in previous designs. this approach enables high hardware utilization across different FHE schemes. Further-more, we propose several algorithm-hardware co-optimizations to minimize the hardware cost of supporting various data shuffling patterns in FHE. this enables high-throughput implementation of function units that provide good cost efficiency. We also propose several compiler-level optimizations to achieve high hardware utilization of the unified architecture for computing FHE data in various algorithmic parameter settings. We evaluate the performance of UFC on different FHE programs, including scheme-specific and hybrid-scheme workloads. Our experiments show that UFC provides up to 6.0 × speedup and 1.6 × delay-energy-area efficiency improvement over state-of-the-art FHE accelerators.

关键词： Costs Microarchitecture Single instruction multiple data Scalability computer architecture Hardware Cryptography Homomorphic encryption Optimization Arithmetic

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Intrusion Detection Schemes Based on Synthetic Minority Oversampling Technique and Machine Learning Models

Intrusion Detection Schemes Based on Synthetic Minority Over...

引用

international symposium on Object-Oriented Real-Time Distributed computing

作者： Ali Hussein Ali Maha Charfeddine Boudour Ammar Bassem Ben Hamed REGIM-Lab: REsearch Groups in Intelligent Machines University of Sfax National School of Electronics and Telecommunications of Sfax Tunisia REGIM-Lab: REsearch Groups in Intelligent Machines University of Sfax National Engineering School of Sfax (ENIS) Sfax Tunisia Laboratory of Signals systeMs aRtificial Intelligence and neTworkS (SM@RTS) University of Sfax National School of Electronics and Telecommunications of Sfax Tunisia

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

With the progression and sophistication of technology, the frequency and intricacy of cyber-attacks also escalate. Malicious hackers and cybercriminals are perpetually devising novel techniques to infiltrate computer systems and steal vital data illicitly. To tackle these risks, organizations must deploy efficient Intrusion Detection Systems (IDSs) to detect and respond to attacks promptly. In recent times, IDSs have garnered considerable interest due to their efficacy and accuracy in identifying anomalous patterns in network traffic through the utilization of machine learning methodologies. this study aims to develop a model capable of detecting intrusions by utilizing several machine learning algorithms on the selected features derived from the modeling procedure. Multicollinearity is a statistical method employed to identify high relationships between variables. this study uses a Synthetic Minority Oversampling Technique (SMOTE) to tackle the problem of imbalanced datasets. SMOTE is a powerful technique that can successfully balance the distribution of classes and improve the accuracy of a machine learning model in identifying the underrepresented class. A study is done to examine several machine learning approaches and evaluate the efficiency of the proposed methodology. the performance of Machine Learning algorithms on the well-established Intrusion Detection benchmark CSE-CIC-IDS2018 and KDD CUP99 datasets shows great potential.

关键词： Radio frequency Accuracy Machine learning algorithms computer hacking Statistical analysis Intrusion detection Telecommunication traffic

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Efficient DDoS Attack Detection through Lightweight Deep Learning Model in Cloud computing Environment

Efficient DDoS Attack Detection through Lightweight Deep Lea...

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Cluster, Cloud and Internet computing Workshops (CCGridW), ieee/ACM international symposium on

作者： Brij B. Gupta Akshat Gaurav Varsha Arya Kwok Tai Chui Department of Computer Science and Information Engineering Asia University Taichung Taiwan Lebanese American University Beirut Lebanon Ronin Institute Montclair NJ USA Asia University Taichung Taiwan Hong Kong Metropolitan University (HKMU) Hong Kong

ISBN: (数字)9798350377514

ISBN: (纸本)9798350377521

In the era of cybersecurity, Distributed Denial of Service (DDoS) attacks continue to pose a substantial threat to network availability and reliability. To counter these attacks, sophisticated detection mechanisms are imperative. this paper presents an innovative approach to DDoS attack detection using a lightweight deep learning model. Leveraging the KDDCup dataset, a well-established benchmark in intrusion detection research, we have achieved remarkable results with a training accuracy of 99.61% and a testing accuracy of 99.56%. Our proposed model emphasizes efficiency without compromising accuracy, addressing the resource constraints often associated with real-time attack detection. By employing a carefully designed architecture, we reduce computational complexity while maintaining a high level of discriminatory power between normal and attack traffic. this lightweight deep learning model not only demonstrates superior performance but also showcases its potential for rapid deployment in scenarios demanding swift and reliable attack detection.

关键词： Deep learning Training Adaptation models Accuracy Computational modeling Intrusion detection Denial-of-service attack Data models Reliability computer crime

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Hyperdimensional computing vs. Neural Networks: Comparing architecture and Learning Process

Hyperdimensional Computing vs. Neural Networks: Comparing Ar...

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ieee international symposium on Quality Electronic Design

作者： Dongning Ma Cong Hao Xun Jiao Villanova University Georgia Institute of Technology

ISBN: (数字)9798350309270

ISBN: (纸本)9798350309287

Hyperdimensional computing (HDC) has obtained abundant attention as an emerging non von Neumann computing paradigm. Inspired by the way human brain functions, HDC leverages high dimensional patterns to perform learning tasks. Compared to neural networks, HDC has shown advantages such as energy efficiency and smaller model size, but sub-par learning capabilities in sophisticated applications. Recently, researchers have observed when combined with neural network components, HDC can achieve better performance than conventional HDC models. this motivates us to explore the deeper insights behind theoretical foundations of HDC, particularly the connection and differences with neural networks. In this paper, we make a comparative study between HDC and neural network to provide a different angle where HDC can be derived from an extremely compact neural network trained upfront. Experimental results show such neural network-derived HDC model can achieve up to 21% and 5% accuracy increase from conventional and learning-based HDC models respectively. this paper aims to provide more insights and shed lights on future directions for researches on this popular emerging learning scheme.

关键词： Training Analytical models Computational modeling computer architecture Brain modeling Energy efficiency Task analysis

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Understanding the Resiliency of Cloud Storage Services

Understanding the Resiliency of Cloud Storage Services

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Pacific Rim international symposium on Dependable computing

作者： Archita Ghosh J Lakshmi Indian Institute of Science Bangalore India

A cloud storage system requires multiple functional and management layers to render a global-scale storage solution. Providing a reliable service through this complex architecture becomes a challenging task. Moreover, the mere complexity of the system makes it difficult to identify the critical components for maintaining a reliable service. While data redundancy has been the predominant factor in improving reliability, it becomes crucial to understand if it is sufficient for the reliability of a cloud storage service. this work proposes a resiliency evaluation method that identifies the components necessary for storage service rendition and the ability of the system to absorb the effect of their failures and minimize the impact on service. Using this method, the resiliency of two distinct cloud storage services, OpenStack Swift and CephFS, are evaluated. the evaluation has revealed that data access requests may get delayed (up to 8x of mean response time) and even fail due to the lack of resiliency for access path components, even when there is enough user data redundancy. the lack of effort is evident while maintaining the consistency of critical internal data components resulting in reduced reliability. Even for stored data, some common failures result in loss of recoverability. the work concludes with some general observations and possible solutions that will help to improve storage service reliability.

关键词： Cloud computing Redundancy computer architecture Complexity theory Reliability Time factors Task analysis

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