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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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performance Evaluation of LoRaWAN Propagation Models for Real-Time IoT Deployments

Performance Evaluation of LoRaWAN Propagation Models for Rea...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Marwa Said Karim Houidi Akram Hakiri Nédra Mellouli-Nauwynck Hella Kaffel Ben Ayed Dept of Computer Sciences Faculty of Sciences University of Tunis El Manar University of Pau and Pays de l’Adour E2S UPPA LIUPPA France University of Paris 8 LIASD France ESILV Devinci Group France

ISBN: (数字)9798350371284

ISBN: (纸本)9798350371291

LoRaWAN protocol has shown promising benefits to diverse IoT verticals by enabling information exchange over long distances via their gateways and enable full sensor coverage while maintaining low power consumption, a long battery lifetime, and transmission across large geographic distances. However, the planning, deployment, and management of LoRaWAN roll-outs are challenging. While several path loss models have been proposed to improve the transmission of packets between sensor nodes and remote gateways, the quality of the data transmission becomes a concern. In this paper, we study four path loss propagation models and test them in a simulation environment in order to identify which model offers better transmission and coverage *** results of experiments show how the Free Space Path Loss (FSPL) model achieves 68% better accuracy performances against baseline propagation models in terms of signal propagation and full sensors’ coverage.

关键词： Wireless communication Computational modeling Predictive models Logic gates Propagation losses Data models Real-time systems

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Research on computer Vision-Based Environment Perception and Decision-Making System for Autonomous Vehicles

Research on Computer Vision-Based Environment Perception and...

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ieee international symposium on Information (IT) in Medicine and Education, ITME

作者： Ye Sun Li Shen Shuangnan Wu Hao Yan Feng Sheng Hunan Automotive Engineering Vocational University Zhuzhou China

ISBN: (数字)9798350356670

ISBN: (纸本)9798350356687

this paper delves into the design and implementation of autonomous vehicle systems, with a focus on the overall architecture, hardware platforms, software design, and system integration. the autonomous driving system captures environmental information through high-precision sensors, which is then processed in real-time and decisions are made by powerful computing units, leading to vehicle control actions. throughout the design and implementation process, emphasis is placed on real-time performance, robustness, and safety considerations. System performance is continuously enhanced through algorithm optimizations, hardware advancements, and improvements in system integration strategies. the objective of this research is to provide a robust foundation for the advancement of autonomous vehicles, thereby propelling progress in smart transportation systems.

关键词： Software design System performance System integration Real-time systems Hardware Safety Smart transportation Vehicle dynamics Autonomous vehicles Testing

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Pacific Rim international symposium on Dependable computing

作者： Md Mashrur Arifin Jyh-Haw Yeh Computer Science Department Boise State University Idaho USA

ISBN: (数字)9798331540746

ISBN: (纸本)9798331540753

Generative Adversarial Networks (GANs) have revolutionized the generation of synthetic malware images, providing significant applications in cybersecurity. Traditional image-based metrics such as Inception Score (IS) and Fréchet Inception Distance (FID) evaluate the visual quality of these images but fail to capture their malicious nature fully. We propose a novel evaluation framework, cTIMS (Correlated Textual-Based and Image-Based Metric Suites), which integrates both image and text-based metrics to provide a comprehensive assessment. Utilizing the multimodal image captioning model BLIP, we extract textual descriptions of GAN-synthesized malware images and analyze the correlation between image metrics (IS, FID) and text metrics (BLEU, METEOR, ROUGE). Additionally, we introduce Kolmogrov-Arnold Network (KAN)-based CNN architectures (VGG16-KAN, VGG19-KAN), demonstrating significant performance improvements in malware classification. the effectiveness of the Train Real Test Synthetic (TRTS) approach in validating these correlations is also evaluated, confirming the method’s reliability in selecting high-quality GAN-generated images.

关键词： Measurement Visualization Analytical models Correlation computer architecture Generative adversarial networks Malware Reliability Meteors computer crime

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Deep Neural Network Inference Partitioning in Embedded Hybrid Analog-Digital Systems

Deep Neural Network Inference Partitioning in Embedded Hybri...

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ieee international symposium on Quality Electronic Design

作者： Fabian Kreß Julian Hoefer Qiushi Lin Patrick Schmidt Zhenhua Zhu Yu Zhu Tanja Harbaum Yu Wang Jürgen Becker Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Tsinghua University Beijing China

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Deep Neural Networks (DNNs) deployed in resource-constrained embedded systems, like automotive platforms, often face severe “memory wall” problems and energy-consuming data movements. To address this challenge, existing work has proposed Processing-In-Memory (PIM) architectures based on emerging non-volatile memory, which perform analog-domain computations inside memory, offering great potentials to solve the “memory wall” problem. However, PIM-based accelerators suffer from circuit noise, impacting DNN accuracy. therefore, building a heterogeneous multi-chiplet architecture based on energy-efficient analog PIM and high-precision digital computing units has become a promising DNN acceleration solution that achieves both high energy efficiency and high accuracy. In this paper, we present an automated framework to explore layer-wise DNN inference partitioning in hybrid analog-digital multi-chiplet systems. After performing a topological ordering, it analyzes the robustness of each layer to constrain mapping decisions across available analog PIM chiplets and digital chiplets. By considering several functional and performance metrics, the framework identifies Pareto-optimal partitioning schemes. Exten-sive experimental results on a variety of DNN models show a reduction in latency of up to 52% with a loss in accuracy of less than 1%.

关键词： Accuracy Quantization (signal) Chiplets architecture Scalability Artificial neural networks computer architecture Robustness Energy efficiency Analog-digital conversion

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EQC: Ensembled Qantum computing for Variational Qantum Algorithms 49

EQC: Ensembled Qantum Computing for Variational Qantum Algor...

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49th ieee/ACM international symposium on computer architecture, ISCA 2022

作者： Stein, Samuel Wiebe, Nathan Ding, Yufei Bo, Peng Kowalski, Karol Baker, Nathan Ang, James Li, Ang Pacifc Northwest National Laboratory RichlandWA United States University Of California Santa BarbaraCA United States University Of Toronto TorontoON Canada

ISBN: (纸本)9781450386104

Variational quantum algorithm (VQA), which is comprised of a classical optimizer and a parameterized quantum circuit, emerges as one of the most promising approaches for harvesting the power of quantum computers in the noisy intermediate scale quantum (NISQ) era. However, the deployment of VQAs on contemporary NISQ devices often faces considerable system and time-dependant noise and prohibitively slow training speeds. On the other hand, the expensive supporting resources and infrastructure make quantum computers extremely keen on high utilization. In this paper, we propose a virtualized way of building up a quantum backend for variational quantum algorithms: rather than relying on a single physical device which tends to introduce everchanging device-specifc noise with less reliable performance as time-since-calibration grows, we propose to constitute a quantum ensemble, which dynamically distributes quantum tasks asynchronously across a set of physical devices, and adjusts the ensemble confguration with respect to machine status. In addition to reduced machine-dependant noise, the ensemble can provide signifcant speedups for VQA training. With this idea, we build a novel VQA training framework called EQC-a distributed gradientbased processor-performance-aware optimization system-that comprises: (i) a system architecture for asynchronous parallel VQA cooperative training;(ii) an analytical model for assessing the quality of a circuit output concerning its architecture, transpilation, and runtime conditions;(iii) a weighting mechanism to adjust the quantum ensemble's computational contribution according to the systems' current performance. Evaluations comprising 500K times' circuit evaluations across 10 IBMQ NISQ devices using a VQE and a QAOA applications demonstrate that EQC can attain error rates very close to the most performant device of the ensemble, while boosting the training speed by 10.5× on average (up to 86× and at least 5.2×). EQC is available at https://

关键词： Quantum computers

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TianheStar: Orchestrating SSSP Applications on Tianhe Supercomputer

TianheStar: Orchestrating SSSP Applications on Tianhe Superc...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Xinbiao Gan Qian Tang Feng Xiong Shijie Li Bo Yang Tiejun Li School of Computer National University of Defense Technology

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

computing single-source shortest paths (SSSP) is one of the fundamental problems in graph theory and is also essential for data-intensive applications. As the potential of artificial intelligence (AI) continues to be explored, and with the advent of exascale supercomputing, there is a growing need for an extremely fast graph engine for SSSP applications. Current distributed SSSP engines for large-scale graph applications, unfortunately, often exhibit poor efficiency when running on supercomputers. In this paper, we introduce TianheStar, an ultra-fast SSSP engine designed specifically for graph search on the Tianhe supercomputer. TianheStar effectively minimizes communication costs and establishes a new balance between computation and communication. the key idea of TianheStar is to leverage network topology information for performing topology-aware message aggregation and architecture-aware group communication. these two techniques effectively reduce the number of messages and the average number of communication hops, respectively. We validate TianheStar using Graph500, a widely adopted benchmark for graph search on supercomputers. Extensive evaluation demonstrates that, compared to the state-of-the-art solutions, TianheStar achieves a remarkable performance improvement. We have deployed TianheStar on the latest Tianhe supercomputer and secured the top position in the latest Graph500. We achieved an outstanding performance of 23,021 GTEPS (Giga Traversed Edges Per Second) for SSSP using 4096 nodes. Furthermore, we have delved into real-world graphs representing the USA road networks and conducted computations to determine the shortest paths between vertices. Our experimental results demonstrate that TianheStar can traverse the USA road network, comprising over 58,333,344 edges, in less than 0.1 second on the Tianhe supercomputer. this performance represents a speedup of over a thousand times compared to parallel shortest-path graph computations on the Aziz supercompu

关键词： Cloud computing Costs Network topology Roads high performance computing Benchmark testing Supercomputers Graph theory Artificial intelligence Engines

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Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-Chip architecture

Ring Road: A Scalable Polar-Coordinate-based 2D Network-on-C...

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ieee/ACM international symposium on Microarchitecture (MICRO)

作者： Yinxiao Feng Wei Li Kaisheng Ma Institute for Interdisciplinary Information Sciences (IIIS) Tsinghua University Beijing China Department of Computer Science and Technology Tsinghua University Beijing China

ISBN: (数字)9798350350579

ISBN: (纸本)9798350350586

Networks-on-chip (NoCs) are scaled out to build large-scale multi-chip networks to meet the growing demand for computing. However, the traditional router-based NoC architecture has significant limitations: 1) the overhead of routers is high, especially for long-distance traffic that traverses numerous chips and hops; 2) On/off-chip traffic is mixed up, so the local NoC performance is dragged down by the cross-chip traffic; 3) the routing design of intra/inter-chip networks is also entangled. the alternative router-less solution based on isolated multi-ring (IMR) can address some of these issues; however, the complete lack of routers leads to wiring overhead and limited scalability thus not suitable for large-scale multi-chip networks. therefore, we are motivated to design a new network architecture that can reduce router/wiring overhead, isolate on/off-chip traffic, and decouple inter/intra-chip routing design by combining the advantages of both routers and router-less rings. In this paper, we propose Ring Road, in which high-speed isolated multi-rings are integrated with compact routers, thus achieving flexible traffic delivery with less router usage and overhead. A polar-coordinate-based description is presented to describe the topology, and corresponding deadlock-free routing algorithms are discussed. As a standalone NoC, Ring Road is low-cost, low-latency, and high-performance. It can also be scaled out into multi-chip networks without redesigning the on-chip routing regardless of inter-chip topology. With low-cost isolated ring channels, no matter how heavy the cross-chip traffic is, the local NoC performance remains consistent. Circuit implementation and post-synthesis analysis show that Ring Road achieves $1.7\sim 2\times$ bandwidth-per-area and $1.6\sim 1.9\times$ bandwidth-per-power compared with the traditional mesh router. Cycle-accurate simulation shows that Ring Road achieves better performance and energy efficiency at various workloads and conf

关键词： Wiring Microarchitecture Roads Scalability Network-on-chip System recovery Network architecture Routing Topology Low latency communication

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Coupling Semantic Association Graphs with Contrastive Learning in Recommendation

Coupling Semantic Association Graphs with Contrastive Learni...

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ACIS international Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed computing (SNPD)

作者： Yifan Ji Jing Zhou School of Computer and Cyber Sciences Communication University of China Beijing China

ISBN: (数字)9798350391954

ISBN: (纸本)9798350391961

Knowledge graphs (KGs) are typically used to enhance the performance of recommender systems by leveraging their characteristic to supplement the sparse user-item interaction data in the latter. this is because KGs feature abundant semantic information about entities (e.g. users or items in recommender systems) and inter-entity relationships. Deep learning has been seen gain wide use in boosting the performance of recommender systems. thanks to focusing merely on nodes in a KG, or entities, such an approach, however, suffers from well capturing the semantics hidden in the node connectivity when learning node embeddings, leading to undesirable discovery of potential semantic associations between nodes. Against this background, we propose for recommender systems a multi-level cross-view contrastive learning mechanism that learns high-quality feature representations from unlabeled data. By incorporating item-item correlations into item embeddings, we developed an interitem semantic association graph (SAG), which was intended to model more comprehensive and finer-grained inter-item semantic associations. A series of experiments have been carried out and the findings verify that the proposed mechanism outperforms other baseline models on all metrics, confirming the effectiveness of coupling SAGs with contrastive learning in enhancing the performance of recommender systems.

关键词： Couplings Measurement Deep learning Semantics Software algorithms Focusing Contrastive learning

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Utilizing Risk Number and Program Slicing to Improve Human-Machine Pair Inspection

Utilizing Risk Number and Program Slicing to Improve Human-M...

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ieee international Conference on Engineering of Complex computer Systems

作者： Yujun Dai Shaoying Liu Guangquan Xu Ai Liu Graduate School of Advanced Science and Engineering Hiroshima University Hiroshima Japan School of Cybersecurity College of Intelligence and Computing Tianjin University Tianjin China

Human-Machine Pair Inspection (HMPI) is a novel code inspection technology proposed in our previous work, which is the style that machine will intelligently guide the programmer to carry out inspections of the program code during programming. For large-scale software projects, the efficiency of HMPI needs to be improved due to the inaccurate measurement of the code structure and the excessive inspection scope. In this paper, to alleviate the above deficiencies, we propose the Risk Number, a code evaluation metric generated based on historical error data. the Risk Number is calculated by a statistical tool called regression analysis, which more accurately indicates the relationship between the nested structure of the code and the likelihood of containing bugs than Cognitive Complexity. Additionally, HMPI is supported by utilizing Risk Number to point out high-risk code and program slicing techniques to extract statements that have dependencies on the code to generate checklists, thereby reducing the scope of inspection. We describe a case study to evaluate the performance of this method by comparing its inspection time and number of detected errors with our previous work. the result shows that the method is likely to guide the programmer to inspect the faulty code earlier and be more efficient in detecting defects than HMPI based on Cognitive Complexity.

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SIMD Extensions - A Historical Perspective

SIMD Extensions - A Historical Perspective

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international symposium for Design and Technology of Electronics Packages (SIITME)

作者： Diana Vuţă-Popescu Ionuţ Cătălin Antofi Cătălin Bogdan Ciobanu Csaba Zoltán Kertész Transilvania University of Braşov Romania National Institute of Research and Development in Microtechnologies Bucharest Romania

ISBN: (数字)9798331539511

ISBN: (纸本)9798331539528

this work provides a historical perspective on the Single Instruction Multiple Data (SIMD) instruction set extensions. SIMD extensions are crucial in modern processors for handling large amounts of data and exploiting data-level parallelism. the effectiveness of SIMD optimizations is influenced by several factors, including data size. Modern SIMD extensions support both integer and floating point numbers. Furthermore, sub-word parallelism is exploited, improving performance when processing narrow data types. We provide an overview of the SIMD extensions for SPARC (VIS), x86 (MMX, SSE, AVX, AVX2, AVX-512, AMX), PowerPC (AltiVec), MIPS (MDMX), Arm (Neon, SVE, SVE2, SME) and RISC-V (RVV) architectures. Furthermore, we provide examples of modern processors featuring SIMD extensions for x86, Arm and RISC-V architectures.

关键词： Neon Single instruction multiple data Instruction sets high performance computing Computational modeling computer architecture Machine learning Hardware Optimization Electronics packaging

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