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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

共 1870 条记录，以下是251-260 订阅

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DeepVM: Integrating Spot and On-Demand VMs for Cost-Efficient Deep Learning Clusters in the Cloud

DeepVM: Integrating Spot and On-Demand VMs for Cost-Efficien...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Yoochan Kim Kihyun Kim Yonghyeon Cho Jinwoo Kim Awais Khan Ki-Dong Kang Baik-Song An Myung-Hoon Cha Hong-Yeon Kim Youngjae Kim Dept. of Computer Science and Engineering Sogang University Seoul Republic of Korea LG Electronics Oak Ridge National Laboratory TN USA ETRI Daejeon Republic of Korea

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

Distributed Deep Learning (DDL), as a paradigm, dictates the use of GPU-based clusters as the optimal infrastructure for training large-scale Deep Neural Networks (DNNs). However, the high cost of such resources makes them inaccessible to many users. Public cloud services, particularly Spot Virtual Machines (VMs), offer a cost-effective alternative, but their unpredictable availability poses a significant challenge to the crucial checkpointing process in DDL. To address this, we introduce DeepVM, a novel solution that recommends cost-effective cluster configurations by intelligently balancing the use of Spot and On-Demand VMs. DeepVM leverages a four-stage process that analyzes instance performance using the FLOPP (FLoating-point Operations Per Price) metric, performs architecture-level analysis with linear programming, and identifies the optimal configuration for the user-specific needs. Extensive simulations and real-world deployments in the AWS environment demonstrate that DeepVM consistently outperforms other policies, reducing training costs and overall makespan. By enabling cost-effective checkpointing with Spot VMs, DeepVM opens up DDL to a wider range of users and facilitates a more efficient training of complex DNNs.

关键词： Training Deep learning Checkpointing Measurement Cloud computing Costs Artificial neural networks Linear programming

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Load Balancing Optimization for Transformer in Distributed Environment 27

Load Balancing Optimization for Transformer in Distributed E...

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27th ieee international Conference on Parallel and Distributed Systems, ICPADS 2021

作者： Ma, Delu Lei, Zhou Chen, Shengbo Wang, Peng School of Computer Engineering and Science Shanghai University Shanghai200444 China Shanghai Key Laboratory of Computer Software Testing and Evaluating Shanghai201112 China

ISBN: (纸本)9781665408783

In recent years, the demand for artificial intelligence applications has increased dramatically. Complex models can promote machine learning to achieve excellent results, but computing efficiency has gradually reached a bottleneck. therefore, more researchers are exploring the improvement of the efficiency of intelligent computing systems. Distributed machine learning can improve the efficiency of model training and inference, but problems such as communication delay and load imbalance between computing nodes still exist. In the multi-GPU distributed computing environment, this paper takes the vision field algorithm VIT (vision transformer) as the optimization object, which has the advantage of convenient parallel training, and proposes several related solutions. Firstly, the parameter server is used as the system logic architecture and in order to reduce the idleness of the computing devices during the training process, the device working status query mechanism is designed to realize load balancing. Secondly, combined with the pre-trained small VIT algorithm model, semi-asynchronous communication method is proposed to reduce the communication overhead of computing devices and accelerate global convergence. the results of this experiment carried out in the existing distributed environment has demonstrated that compared with the existing synchronization method, the computational efficiency has been improved well under the premise of slightly reducing the accuracy. © 2021 ieee.

关键词： Computation theory

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Hardware Acceleration of SpMV Multiplier for Deep Learning 25

Hardware Acceleration of SpMV Multiplier for Deep Learning

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25th international symposium on VLSI Design and Test, VDAT 2021

作者： Mahesh, M. Nalesh, S. Kala, S. Indian Institute of Information Technology Department of Computer Science and Engineering Kottayam India Cochin University of Science and Technology Department of Electronics Kerala India Indian Institute of Information Technology Department of Electronics and Communication Engineering Kottayam India

ISBN: (纸本)9781665419925

Deep Learning techniques are widely adopted in many computer vision tasks and are practically implemented in real-world systems. Deep learning is a promising method for machine learning, where complex functions can be learned directly from the data. Deep learning algorithms provide high accuracy for recognition tasks, while consuming significant resources for computation, compared to the conventional algorithms. State-of-the-art deep learning networks have hundreds of millions of parameters, which makes them less suitable for adoption in devices with constrained memory and power requirements like edge computing devices and mobile devices. Techniques like quantization and inducing sparsity, aims to reduce the total number of computations needed for deep learning inference. For portable embedded applications, general purpose computing hardware like GPPs (General Purpose Processors) and GPUs (Graphic Processing Units) are not preferred as these applications demand high energy efficiency. Field Programmable Gate Arrays (FPGAs) are suitable hardware solutions for edge computing, which gives better power consumption with increased flexibility. In this paper we propose a bandwidth-efficient sparse matrix-vector (SpMV) multiplier architecture for faster deep learning inference. Our architecture also reduces memory-bandwidth bottleneck present in hardware realization of deep learning algorithms. Proposed architecture can use the maximum available memory bandwidth of the computing device, using the multiple MAC (multiply and accumulate) channels. the proposed architecture has been implemented on Kintex-7 FPGA with an operating frequency of 270 MHz and gave significant performance gain when compared with existing implementation. © 2021 ieee.

关键词： Bandwidth

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Building Agile Workflow Microservice System for HPC Applications Based on Fast-start OSv 27

Building Agile Workflow Microservice System for HPC Applicat...

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27th ieee international Conference on Parallel and Distributed Systems, ICPADS 2021

作者： Hu, Qiang Ma, Lixian Shao, En Tan, Guangming Institute of Computing Technology CAS State Key Laboratory of Computer Architecture Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781665408783

the advances of containers have significantly promoted the development of microservice architecture. this architecture splits a monolithic application into multiple independent components and the container orchestrator manages these components by the container in the cloud environment. the feasibility of deploying high performance computing(HPC) applications as microservices has been proven, but the existing container orchestrator incurs a large performance overhead as there is interference between different containers on the same physical host. In this paper, we design an agile workflow microservice system for HPC applications with fast-start OSv. We consider improving HPC workflow performance from two aspects: single OSv startup time optimization and workflow orchestration optimization. For single OSv startup time optimization, we design a fast-start OSv by analyzing the process of OSv startup and finding an optimization by modifying OSv source code. In this way, we get nearly 50% improvement of startup time. For workflow orchestration optimization, we propose four optimization techniques to speed up the execution of workflow by jointly considering OSv and workflow features, namely: node fusion, node merge, image preload, boot delay. Furthermore, we utilize our fast startup OSv to design an orchestration system for efficiently building an agile HPC workflow microservice by Kubevirt. Our experimental results optimization microservice system reduces the execution time by 30% compared with the original deployment with docker. © 2021 ieee.

关键词： Containers

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CLITE: Efficient and QoS-Aware Co-location of Multiple Latency-Critical Jobs for Warehouse Scale computers 26

CLITE: Efficient and QoS-Aware Co-location of Multiple Laten...

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26th ieee international symposium on high performance computer architecture (HPCA)

作者： Patel, Tirthak Tiwari, Devesh Northeastern Univ Boston MA 02115 USA

ISBN: (纸本)9781728161495

Large-scale data centers run latency-critical jobs with quality-of-service (QoS) requirements, and throughput-oriented background :jobs, which need to achieve high performance. Previous works have proposed methods which cannot co-locate multiple latency-critical jobs with multiple backgrounds jobs while: (I) meeting the QoS requirements of all latency-critical jobs, and (2) maximizing the performance of the background jobs. this paper proposes CLITE, a Bayesian Optimization-based, multi-resource partitioning technique which achieves these goals.

关键词： Latency Critical Jobs Multi Tenancy QoS Delivery Warehouse Scale computing

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FPGA-Based Hardware-in-the-Loop Real-Time Simulation Implementation

FPGA-Based Hardware-in-the-Loop Real-Time Simulation Impleme...

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Midwest symposium on Circuits and Systems (MWSCAS)

作者： Farshideh Kordi Christian Barnard Paul Fortier Amine Miled Departement of Electrical and Computer Engineering Université Laval Québec QC Canada

Hardware-in-the-Loop (HIL) simulators have become an essential tool in the automotive industry as they allow comprehensive testing and validation of electronic control units (ECUs), Although HIL simulations are widely used in the vehicle, aerospace and other industries that rely on electronic control systems, they can also be quite challenging to develop. One of the main challenges of HIL simulators is creating a virtual environment that accurately replicates the behavior of the real-world system. Artificial intelligence (AI) algorithms can be trained on extensive real-world datasets to create more accurate virtual environments of complex systems for HIL simulations. Moreover, latency is a crucial factor in producing a reliable virtual environment for ECU in HIL simulations. FPGA (Field Programmable Gate Array) can help to minimize latency in HIL simulations by providing high-performance computing resources. this paper aims to address these challenges by presenting a machine learning-based HIL simulator design on FPGA. the proposed architecture uses FPGA to accelerate the computations of a temporal convolutional neural network (TCN). the paper also describes how increasing the number of input channels can improve the performance of the TCN model on an FPGA.

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On-chip Parallel Photonic Reservoir computing using Multiple Delay lines 32

On-chip Parallel Photonic Reservoir Computing using Multiple...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Hasnain, Syed Ali Mahapatra, Rabi Texas A&M Univ Dept Comp Sci & Engn College Stn TX 77843 USA

ISBN: (纸本)9781728199245

Silicon-Photonics architectures have enabled high speed hardware implementations of Reservoir computing (RC). With a delayed feedback reservoir (DFR) model, only one non-linear node can be used to perform RC. However, the delay is often provided by using off-chip fiber optics which is not only space inconvenient but it also becomes architectural bottleneck and hinders to scalability. In this paper, we propose a completely on-chip photonic RC architecture for high performance computing, employing multiple electronically tunable delay lines and micro-ring resonator (MRR) switch for multi-tasking. Proposed architecture provides 84% less error compared to the state-of-the-art standalone architecture in [8] for executing NARMA task. For multi-tasking, the proposed architecture shows 80% better performance than [8]. the architecture outperforms all other proposed architectures as well. the on-chip area and power overhead of proposed architecture due to delay lines and MRR switch are 0.0184mm(2) and 26mW respectively.

关键词： Reservoir computing (RC) Delayed Feedback Reservoir (DFR) Recurrent Neural Network (RNN) Mach Zehnder Interferometer (MZI) Micro ring Resonator (MRR)

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FFT optimizations and performance assessment targeted towards satellite and airborne radar processing 32

FFT optimizations and performance assessment targeted toward...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Schlemon, Maron Naghmouchi, Jamin German Aerosp Ctr DLR Microwaves & Radar Inst Oberpfaffenhofen Germany Innovat Gesell TU Braunschweig mbH Next Generat Comp Braunschweig Germany

ISBN: (纸本)9781728199245

Following the re-invention of the FFT algorithm by Cooley and Tukey in 1965, a lot of effort has been invested into optimization of this algorithm and all its variations. In this paper, we discuss its use and optimization for current and future radar applications, and give a brief survey on implementations that have claimed relatively high advantages in terms of performance over existing solutions. Correspondingly, we present an in-depth analysis of state-of-the-art solutions and our own implementation that will allow the reader to evaluate the performance improvements on a fair basis. therefore, we discuss the development of a high-performance Fast Fourier Transform (FFT) using an enhanced Radix-4 decimation in frequency (DIF) algorithm, compare it against the Fastest Fourier Transform in the West (FFTW) autotuned library as well as other solutions and frameworks.

关键词： FFT Radix-4 DIF high performance Algorithms Parallel computing Embedded computing SAR Chirp Compression

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A highly Efficient SGEMM Implementation using DMA on the Intel/Movidius Myriad-2 32

A Highly Efficient SGEMM Implementation using DMA on the Int...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Bakshi, Suyash Johnsson, Lennart Univ Houston Dept Comp Sci Main Campus Houston TX 77204 USA

ISBN: (纸本)9781728199245

Reducing energy consumption and achieving high energy efficiency in computation has become the top priority in high performance computing. high energy efficiency generally requires high resource utilization since energy demand for many applications and architectures is dependent on active time. We show that by using DMA the 28nm CMOS node Myriad-2 Vision Processing Unit can achieve 25 GFLOPs/W for FP32 matrix-multiplication. Our main contributions are: (i) An analysis of data transfer needs for inner and outer-product formulations of matrix multiplication with respect to the Myriad-2 memory hierarchy, (ii) An efficient use of DMA for managing matrix block transfers between on-chip and main memory (iii) A detailed analysis of the effects of matrix block shapes and DRAM page faults on performance and energy efficiency.

关键词： DMA DRAM page faults Energy efficiency high bandwidth high performance Matrix multiplication Myriad 2 Outer product formulation SGEMM

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Data Locality Aware Computation Offloading in Near Memory Processing architecture for Big Data Applications

Data Locality Aware Computation Offloading in Near Memory Pr...

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international Conference on high performance computing

作者： Satanu Maity Mayank Goel Manojit Ghose Department of Computer Science and Engineering Indian Institute of Information Technology Guwahati India

the data-intensive applications of today's big data era often produce a large memory footprint. As a result, a significant volume of data needs to travel from memory to the CPU under the traditional Von-Neumann computing paradigm. Near-memory processing (NMP) or processing-in-memory (PIM) is a potential alternate computation framework where a computation unit is placed near the memory (or inside the memory) and a portion of an application is executed on it (termed computation offloading) aiming to reduce the amount of data movement and its consequences. Although a few computation offloading strategies have been proposed in recent times, the existing approaches do not consider the data locality offered by the last level cache and the overall execution time of the application while designing their policies. In this paper, we propose a data locality-aware computation offloading strategy for a hybrid computing system comprising the host processor and NMP-enabled 3D memory. After the application code is instrumented using the LLVM compiler framework, the strategy offloads a portion of an application to NMP if its estimated overall execution time is less. An extensive simulation performed on a set of standard simulators for a bunch of large graph-based application benchmarks reports the effectiveness of the proposed strategy by achieving a maximum speedup of 40% and 11.8% as compared to the host-only configuration and the state-of-art policy, respectively. the proposed strategy also reduces the off-chip data transfer and energy consumption by a significant margin as compared to the host-only configuration (avg 27%) and the state-of-art policy (avg 28%). Further, the proposed policy reduces the LLC miss rate by 57% as compared to the state-of-art policy.

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