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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

共 1870 条记录，以下是261-270 订阅

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Cache Register Sharing Structure for Channel-level Near-memory Processing in NAND Flash Memory

Cache Register Sharing Structure for Channel-level Near-memo...

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ieee international symposium on Quality Electronic Design

作者： Hyunwoo Kim Hyundong Lee Jongbeom Kim Yunjeong Go Seungwon Baek Jaehong Song Junhyeon Kim Minyoung Jung Hyodong Kim Seongju Kim Taigon Song School of Electronic and Electrical Engineering Kyungpook National University (KNU) Daegu South Korea School of Electronics Engineering Kyungpook National University (KNU) Daegu South Korea

A vast number of data used for Artificial intelligence causes bottleneck between the processor and memory. To tackle this issue, a technology that embeds a processing unit in the memory (PIM: Processing-in Memory) has been proposed. However, SRAM/DRAM based PIM have a issue for lack of capacity. thus, we propose a NAND flash PIM scheme that shares the cache register. Our scheme significantly reduces the read latency and operation time by -22.8% and -43.7%, compared to the conventional memory system. the power-performance-area (PPA) was reduced by 17.2% by shortening the number of cycles. Our NAND PIM specializes in tasks requiring high-performance computing.

关键词： Registers Flash memories computer architecture Artificial intelligence Arrays Random access memory Microprocessors

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Optimizing Green Energy Consumption of Fog computing architectures 32

Optimizing Green Energy Consumption of Fog Computing Archite...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Gougeon, Adrien Camus, Benjamin Orgerie, Anne-Cecile Univ Rennes INRIA CNRS IRISAENS Rennes Rennes France

ISBN: (纸本)9781728199245

the Cloud already represents an important part of the global energy consumption, and this consumption keeps increasing. Many solutions have been investigated to increase its energy efficiency and to reduce its environmental impact. However, with the introduction of new requirements, notably in terms of latency, an architecture complementary to the Cloud is emerging: the Fog. the Fog computing paradigm represents a distributed architecture closer to the end-user. Its necessity and feasibility keep being demonstrated in recent works. However, its impact on energy consumption is often neglected and the integration of renewable energy has not been considered yet. the goal of this work is to exhibit an energy-efficient Fog architecture considering the integration of renewable energy. We explore three resource allocation algorithms and three consolidation policies. Our simulation results, based on real traces, show that the intrinsic low computing capability of the nodes in a Fog context makes it harder to exploit renewable energy. In addition, the share of the consumption from the communication network between the computing resources increases in this context, and the communication devices are even harder to power through renewable sources.

关键词： Fog computing Job scheduling Renewable energy

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Heterogeneous Multi-Functional Look-Up-Table-based Processing-in-Memory architecture for Deep Learning Acceleration

Heterogeneous Multi-Functional Look-Up-Table-based Processin...

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ieee international symposium on Quality Electronic Design

作者： Sathwika Bavikadi Purab Ranjan Sutradhar Amlan Ganguly Sai Manoj Pudukotai Dinakarrao Department of Electrical and Computer Engineering George Mason University Fairfax VA USA Department of Computer Engineering Rochester Institute of Technology Rochester NY USA

Emerging applications including deep neural networks (DNNs) and convolutional neural networks (CNNs) employ massive amounts of data to perform computations and data analysis. Such applications often lead to resource constraints and impose large overheads in data movement between memory and compute units. Several architectures such as Processing-in-Memory (PIM) are introduced to alleviate the bandwidth bottlenecks and inefficiency of traditional computing architectures. However, the existing PIM architectures represent a trade-off between power, performance, area, energy efficiency, and programmability. To better achieve the energy-efficiency and flexibility criteria simultaneously in hardware accelerators, we introduce a multi-functional look-up-table (LUT)-based reconfigurable PIM architecture in this work. the proposed architecture is a many-core architecture, each core comprises processing elements (PEs), a stand-alone processor with programmable functional units built using high-speed reconfigurable LUTs. the proposed LUTs can perform various operations, including convolutional, pooling, and activation that are required for CNN acceleration. Additionally, the proposed LUTs are capable of providing multiple outputs relating to different functionalities simultaneously without the need to design different LUTs for different functionalities. this leads to optimized area and power overheads. Furthermore, we also design special-function LUTs, which can provide simultaneous outputs for multiplication and accumulation as well as special activation functions such as hyperbolics and sigmoids. We have evaluated various CNNs such as LeNet, AlexNet, and ResNet18,34,50. Our experimental results have demonstrated that when AlexNet is implemented on the proposed architecture shows a maximum of 200× higher energy efficiency and 1.5× higher throughput than a DRAM-based LUT-based PIM architecture.

关键词： Deep learning Neural networks computer architecture Programming throughput Energy efficiency Real-time systems

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XPySom: high-performance Self-Organizing Maps 32

XPySom: High-Performance Self-Organizing Maps

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Mancini, Riccardo Ritacco, Antonio Lanciano, Giacomo Cucinotta, Tommaso Scuola Super Sant Anna Pisa Italy Scuola Normale Super Pisa Pisa Italy

ISBN: (纸本)9781728199245

In this paper, we introduce XPySom, a new opensource Python implementation of the well-known Self-Organizing Maps (SOM) technique. It is designed to achieve high performance on a single node, exploiting widely available Python libraries for vector processing on multi-core CPUs and GP-GPUs. We present results from an extensive experimental evaluation of XPySom in comparison to widely used open-source SOM implementations, showing that it outperforms the other available alternatives. Indeed, our experimentation carried out using the Extended MNIST open data set shows a speed-up of about 7x and 100x when compared to the best open-source multi-core implementations we could find with multi-core and GP-GPU acceleration, respectively, achieving the same accuracy levels in terms of quantization error.

关键词： self-organizing maps (SOMs) performance comparison experimental evaluation GP-GPU acceleration

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SMART: Serverless Module Analysis and Recognition Technique for Managed Applications

SMART: Serverless Module Analysis and Recognition Technique ...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Adi Ashkenazi Edita Grolman Aviad Elyashar Dudu Mimran Oleg Brodt Yuval Elovici Asaf Shabtai Department of Software and Information Systems Engineering Ben-Gurion University of the Negev Israel Cyber Labs@BGU Ben-Gurion University of the Negev Israel Department of Computer Science Shamoon College of Engineering Beer-Sheva Israel

ISBN: (数字)9798350395662

ISBN: (纸本)9798350395679

Serverless Function-as-a-Service (FaaS) environments enable developers to build and run cloud applications without the need to manage the underlying servers and computing infrastructure, allowing them to focus on implementing the application logic. Such environments contain numerous functions and dynamic resources, e.g., APIs and databases, making it challenging to gain insight and context of internal events i.e., recognize modules. Module in a serverless application is a set of functions and resources, that represents a functional unit that shares logical context. this paper presents SMART, a method for automatic analysis and recognition of modules for managed serverless applications. the proposed method creates an event-based graph by analyzing the standard serverless logs that document events involving the application’s functions and resources and utilizes well-known community detection algorithms (such as Louvain), with graph centrality metrics (such as degree centrality) to recognize the modules. SMART enables high-level visibility of the application’s structure and logical context which can facilitate security analysis and contribute to improved decision-making of incident response handlers, who typically do not have direct access to the application’s design and code, which can lead to challenges in fully understanding the system’s intricacies. We focused on the popular Amazon Web Services (AWS) Lambda serverless computing platform and evaluated the proposed method on three different demo applications (Airline Booking, VOD, and E-commerce). We compared SMART’s performance to four overlapping community detection algorithms and showed that it outperformed them in the task of module recognition, with a maximum improvement of 61% on the omega index metric compared to the Speaker-Listener Label Propagation algorithm. In addition, we demonstrate that the use of large language models (LLMs) with the knowledge gained by SMART can enrich security analysis insights.

关键词： Measurement Web services Serverless computing computer architecture Security Indexes Electronic commerce Detection algorithms Standards Airline industry

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HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy-Efficient Classification

HIDE: A Hyperdimensional In-DRAM Encoder for Fast and Energy...

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ieee international symposium on Quality Electronic Design

作者： Ahmed Mamdouh Dayane Reis Computer Science and Engineering University of South Florida Tampa USA

ISBN: (数字)9798331509422

ISBN: (纸本)9798331509439

Hyperdimensional computing (HDC) processes information in a high-dimensional space, offering advantages over deep neural networks (DNNs), such as smaller model sizes, robustness to soft errors, and the capability for one/few-shot learning without significant accuracy drops in some applications. Although HDC shows great potential, encoding data into a hyperdimensional space poses challenges due to the significant data movement between processing units and memory in conventional architectures. Processing-in-memory (PIM) embeds computation directly within memory, reducing latency and energy consumption. Among PIM approaches, in-DRAM computation leverages the parallelism of DRAM to perform bulk bit-wise operations with high throughput. In this paper, we present HIDE, the first hyperdimensional in-DRAM encoder for fast and energy-efficient classification. HIDE integrates H DC encoding directly within commodity DRAM, significantly reducing energy consumption and improving system performance. HIDE achieves up to $272.8\times (23.3\times)$ encoding speedup over a CPU (GPU) during training, with energy reductions of 94.8% (95.0%) during training (inference). Integrating HIDE with the GPU achieves an overall system speedup of $15\times(7.2\times)$ during training (inference) compared to a GPU-only system, along with energy savings of 92.3% and 82.7%, respectively, for classification tasks with the MNIST, ISOLET, and UCHAR datasets.

关键词： Training Energy consumption Memory architecture Energy conservation Graphics processing units Random access memory throughput Encoding Energy efficiency Central Processing Unit

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A Robotic Communication Middleware Combining high performance and high Reliability 32

A Robotic Communication Middleware Combining High Performanc...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Liu, Wei Wu, Hao Jiang, Ziyue Gong, Yifan Jin, Jiangming TuSimple San Diego CA 92122 USA

ISBN: (数字)9781728199245

ISBN: (纸本)9781728199245

With the significant advances of AI technology, intelligent robotic systems have achieved remarkable development and profound effects. To enable massive data transmission in an efficient and reliable way, both high performance and high reliability should be taken into account in system design. However, the conventional communication middleware used in the majority of autonomous robotic systems, is based on socked-based methods, which always lead to high latency. Moreover, some sophisticated communication middleware utilizes shared memory upon ring buffers for high performance without consideration of the reliability. To obtain both high performance and high reliability, we employ shared memory for performance improvement and propose a novel socket-based communication control algorithm to improve reliability during data transmission. Furthermore, based on the proposed algorithm, we implement a novel robotic communication middleware, named Robust-Z, combining both high performance and high reliability. Experimental results show that (1) Robust-Z is able to gain up to 41% and 5% performance improvement compared to ROS2 and Apollo CyberRT, respectively;(2) Robust-Z is able to provide crash safety and reduce 5.2% data missing rate compared with CyberRT.

关键词： Autonomous Navigation Systems Inter-process Communication high performance high Availability

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Controlling Garbage Collection and Request Admission to Improve performance of FaaS Applications 32

Controlling Garbage Collection and Request Admission to Impr...

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32nd ieee international symposium on computer architecture and high-performance computing (SBAC-PAD) / 11th Workshop on Applications for Multi-Core architectures (WAMCA)

作者： Quaresma, David Fireman, Daniel Pereira, thiago Emmanuel Univ Fed Campina Grande Campina Grande Paraiba Brazil Fed Inst Alagoas Arapiraca Brazil

ISBN: (纸本)9781728199245

Runtime environments like Java's JRE, .NET's CLR, and Ruby's MRI, are popular choices for cloud-based applications and particularly in the Function as a Service (FaaS) serverless computing context. A critical component of runtime environments of these languages is the garbage collector (GC). the GC frees developers from manual memory management, which could potentially ease development and avoid bugs. the benefits of using the GC come with a negative impact on performance;that impact happens because either the GC needs to pause the runtime execution or competes with the running program for computational resources. In this work, we evaluated the usage of a technique - Garbage Collector Control Interceptor (GCI) that eliminates the negative impact of GC on performance by controlling GC executions and transparently shedding requests while the collections are happening. We executed experiments simulating AWS Lambda's behavior and found that GCI is a viable solution. It benefited the user by improving the response time up to 10:86% at 99.9th percentile and reducing cost by 7:22%, but it also helped the platform provider by improving resource utilization by 14:52%

关键词： serverless faas garbage collector cold start gci cloud computing cloud services

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Blink: Towards Efficient RDMA-based Communication Coroutines for Parallel Python Applications 27

Blink: Towards Efficient RDMA-based Communication Coroutines...

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27th ieee international Conference on high performance computing, Data, and Analytics (HiPC)

作者： Shafi, Aamir Hashmi, Jahanzeb Maqbool Subramoni, Hari Panda, Dhabaleswar K. Ohio State Univ Columbus OH 43210 USA

ISBN: (纸本)9781665422925

Python is emerging as a popular language in the data science community due to its ease-of-use, vibrant community, and rich set of libraries. Dask is a popular Python-based distributed computing framework that allows users to process large amounts of data on parallel hardware. the Dask distributed package is a non-blocking, asynchronous, and concurrent library that offers support for distributed execution of tasks on datacenter and HPC environments. A few key requirements of designing high-performance communication backends for Dask distributed is to provide scalable support for coroutines that are unlike regular Python functions and can only be invoked from asynchronous applications. In this paper, we present Blink-a high-performance communication library for Dask on high-performance RDMA networks like InfiniBand. Blink offers a multi-layered architecture that matches the communication requirements of Dask and exploits high-performance interconnects using a Cython wrapper layer to the C backend. We evaluate the performance of Blink against other counterparts using various micro-benchmarks and application kernels on three different cluster testbeds with varying interconnect speeds. Our micro-benchmark evaluation reveals that Blink outperforms other communication backends by more than 3x for message sizes ranging from 1 Byte to 64 KByte, and by a factor of 2x for message sizes ranging from 128 KByte to 8 MByte. Using various application-level evaluations, we demonstrate that Dask achieves up to 7% improvement in application throughput (e.g., total worker throughput).

关键词： Asynchronous I/O in Python Parallel and Distributed computing Framework Communication on RDMA Networks Efficient Data Science in Python

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Revisiting Huffman Coding: Toward Extreme performance on Modern GPU architectures 35

Revisiting Huffman Coding: Toward Extreme Performance on Mod...

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35th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Tian, Jiannan Rivera, Cody Di, Sheng Chen, Jieyang Liang, Xin Tao, Dingwen Cappello, Franck Washington State Univ Sch Elect Engn & Comp Sci Pullman WA 99164 USA Univ Alabama Dept Comp Sci Tuscaloosa AL 35487 USA Argonne Natl Lab Math & Comp Sci Div Lemont IL USA Oak Ridge Natl Lab Oak Ridge TN USA Univ Illinois Champaign IL USA

ISBN: (纸本)9781665440660

Today's high-performance computing (HPC) applications are producing vast volumes of data, which are challenging to store and transfer efficiently during the execution, such that data compression is becoming a critical technique to mitigate the storage burden and data movement cost. Huffman coding is arguably the most efficient Entropy coding algorithm in information theory, such that it could be found as a fundamental step in many modern compression algorithms such as DEFLATE. On the other hand, today's HPC applications are more and more relying on the accelerators such as GPU on supercomputers, while Huffman encoding suffers from low throughput on GPUs, resulting in a significant bottleneck in the entire data processing. In this paper, we propose and implement an efficient Huffman encoding approach based on modern GPU architectures, which addresses two key challenges: (1) how to parallelize the entire Huffman encoding algorithm, including codebook construction, and (2) how to fully utilize the high memory-bandwidth feature of modern GPU architectures. the detailed contribution is fourfold. (1) We develop an efficient parallel codebook construction on GPUs that scales effectively with the number of input symbols. (2) We propose a novel reduction based encoding scheme that can efficiently merge the codewords on GPUs. (3) We optimize the overall GPU performance by leveraging the state-of-the-art CUDA APIs such as Cooperative Groups. (4) We evaluate our Huffman encoder thoroughly using six real-world application datasets on two advanced GPUs and compare with our implemented multi-threaded Huffman encoder. Experiments show that our solution can improve the encoding throughput by up to 5.0x and 6.8x on NVIDIA RTX 5000 and V100, respectively, over the state-of-the-art GPU Huffman encoder, and by up to 3.3x over the multi-thread encoder on two 28-core Xeon Platinum 8280 CPUs.

关键词： Distributed processing Platinum Graphics processing units computer architecture throughput Data processing Supercomputers

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