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Towards high performance, Portability, and Productivity: Lightweight Augmented Neural Networks for performance Prediction 27

Towards High Performance, Portability, and Productivity: Lig...

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27th ieee international Conference on high performance computing, Data, and Analytics (HiPC)

作者： Srivastava, Ajitesh Zhang, Naifeng Kannan, Rajgopal Prasanna, Viktor K. Univ Southern Calif Los Angeles CA 90007 USA Us Army Res Lab West Adelphi MD USA

ISBN: (纸本)9781665422925

Writing high-performance code requires significant expertise in the programming language, compiler optimizations, and hardware knowledge. this often leads to poor productivity and portability and is inconvenient for a non-programmer domain-specialist such as a Physicist. More desirable is a high-level language where the domain-specialist simply specifies the workload in terms of high-level operations (e.g., matrixmultiply(A, B)), and the compiler identifies the best implementation fully utilizing the heterogeneous platform. For creating a compiler that supports productivity, portability, and performance simultaneously, it is crucial to predict the performance of various available implementations (variants) of the dominant operations (kernels) contained in the workload on various hardware to decide (a) which variant should be chosen for each kernel in the workload, and (b) on which hardware resource the variant should run. To enable the performance prediction, we propose lightweight augmented neural networks for arbitrary combinations of kernel-variant-hardware. A key innovation is utilizing the mathematical complexity of the kernels as a feature to achieve higher accuracy. these models are compact to reduce training time and allow fast inference during compile-time and run-time. Using models with less than 75 parameters, and only 250 training data instances, we are able to obtain accurate performance predictions, significantly outperforming traditional feed-forward neural networks on 48 kernel-variant-hardware combinations. We further demonstrate that our variant-selection approach can be used in Halide implementations to obtain up to 1.7x speedup over Halide auto-scheduler.

关键词： Lightweight augmented neural networks performance prediction Productivity Portability Compiler Heterogeneous platforms

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An Automated Approach to Compare Bit Serial and Bit Parallel In-Memory computing for DNNs

An Automated Approach to Compare Bit Serial and Bit Parallel...

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ieee international symposium on Circuits and Systems

作者： Alok Parmar Kailash Prasad Nanditha Rao Joycee Mekie Inernion Insiue of Inforion Technoogy Bngore IndiIndin Insiue of Technoogy Gndhingr IndiInernion Insiue of Inforion Technoogy Bngore IndiIndin Insiue of Technoogy Gndhingr Indi

ISBN: (数字)9781665484855

ISBN: (纸本)9781665484862

this paper presents an exhaustive comparison of two different techniques for In-Memory computing in SRAM: bit-serial arithmetic (BSA), and bit-parallel arithmetic (BPA). We have modeled both BSA and BPA and integrated them with CACTI for the CMOS 28nm technology node. the results are analyzed for both approaches with ten different sub-array configurations ranging from 128 128 to 2048 2048. We performed the convolution operation on the ImageNet dataset for comparison. the key observation is that the BPA begins to yield at least 25% better (lower) Energy Delay Product (EDP) as compared to that in BSA for large (2048 2048) sub-array sizes. the BSA yields 4 lower delay on an average, while the BPA yields 6 lower dynamic energy. Hence, the choice of the IMC architecture needs to be made depending on the application need (low energy/high performance). We have also simulated 12 different multi-bank IMC arrangements and show that just modifying the memory array structure can improve the EDP by up to 8 .

关键词： Semiconductor device modeling Convolution Computational modeling Random access memory computer architecture In-memory computing Energy efficiency

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Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit high performance RISC-V Processor with Vector Extension 20

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-o...

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47th ACM/ieee Annual international symposium on computer architecture (ISCA)

作者： Chen, Chen Xiang, Xiaoyan Liu, Chang Shang, Yunhai Guo, Ren Liu, Dongqi Lu, Yimin Hao, Ziyi Luo, Jiahui Chen, Zhijian Li, Chunqiang Pu, Yu Meng, Jianyi Yan, Xiaolang Xie, Yuan Qi, Xiaoning Alibaba Cloud T Head Div Hangzhou Peoples R China

ISBN: (纸本)9781728146614

the open source RISC-V ISA has been quickly gaining momentum. this paper presents Xuantie-910, an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division. It is fully based on the RV64GCV instruction set and it features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations. It also implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing. Xuantie-910 supports multi-core multi-cluster SMP with cache coherence. Each cluster contains 1 to 4 core(s) capable of booting the Linux operating system. Each single core utilizes the state-of-the-art 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture, achieving a maximum clock frequency of 2.5 GHz in the typical process, voltage and temperature condition in a TSMC 12nm FinFET process technology. Each single core with the vector execution unit costs an area of 0.8 mm(2) (excluding the L2 cache). the toolchain is enhanced significantly to support the vector extension and custom extensions. through hardware and toolchain co-optimization, to date Xuantie-910 delivers the highest performance (in terms of IPC, speed, and power efficiency) for a number of industrial control flow and data computing benchmarks, when compared with its predecessors in the RISC-V family. Xuantie-910 FPGA implementation has been deployed in the data centers of Alibaba Cloud, for application-specific acceleration (e.g., blockchain transaction). the ASIC deployment at low-cost SoC applications, such as IoT endpoints and edge computing, is planned to facilitate Alibaba's end-to-end and cloud-to-edge computing infrastructure.

关键词： RISC-V multi-core cache memory architectures out of order vector extension

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Baldur: A Power-Efficient and Scalable Network Using All-Optical Switches 26

Baldur: A Power-Efficient and Scalable Network Using All-Opt...

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26th ieee international symposium on high performance computer architecture (HPCA)

作者： Jokar, Mohammad Reza Qiu, Junyi Chong, Frederic T. Goddard, Lynford L. Dallesasse, John M. Feng, Milton Li, Yanjing Univ Chicago Dept Comp Sci Chicago IL 60637 USA Univ Illinois Dept Elect & Comp Engn 1406 W Green St Urbana IL 61801 USA

ISBN: (数字)9781728161495

ISBN: (纸本)9781728161495

We present the first all-optical network, Baldur, to enable power-efficient and high-speed communications in future exascale computing systems. the essence of Baldur is its ability to perform packet routing on-the-fly in the optical domain using an emerging technology called the transistor laser (TL), which presents interesting opportunities and challenges at the system level. Optical packet switching readily eliminates many inefficiencies associated with the crossings between optical and electrical domains. However, TL gates consume high power at the current technology node, which makes TL-based buffering and optical clock recovery impractical. Consequently, we must adopt novel (bufferless and clock-less) architecture and design approaches that are substantially different from those used in current networks. At the architecture level, we support a bufferless design by turning to techniques that have fallen out of favor for current networks. Baldur uses a low-radix, multi-stage network with a simple routing algorithm that drops packets to handle congestion, and we further incorporate path multiplicity and randomness to minimize packet drops. this design also minimizes the number of TL gates needed in each switch. At the logic design level, a non-conventional, length-based data encoding scheme is used to eliminate the need for clock recovery. We thoroughly validate and evaluate Baldur using a circuit simulator and a network simulator. Our results show that Baldur achieves up to 3,000X lower average latency while consuming 3.2X-26.4X less power than various state-of-the-art networks under a wide variety of traffic patterns and real workloads, for the scale of 1,024 server nodes. Baldur is also highly scalable, since its power per node stays relatively constant as we increase the network size to over 1 million server nodes, which corresponds to 14.6X-31.0X power improvements compared to state-of-the-art networks at this scale.

关键词： optical computing all-optical network exascale computing datacenter network

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Building Agile Workflow Microservice System for HPC Applications Based on Fast-start OSv

Building Agile Workflow Microservice System for HPC Applicat...

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international Conference on Parallel and Distributed Systems (ICPADS)

作者： Qiang Hu Lixian Ma En Shao Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Science Beijing China

ISBN: (纸本)9781665408790

the advances of containers have significantly promoted the development of microservice architecture. this architecture splits a monolithic application into multiple independent components and the container orchestrator manages these components by the container in the cloud environment. the feasibility of deploying high performance computing(HPC) applications as microservices has been proven, but the existing container orchestrator incurs a large performance overhead as there is interference between different containers on the same physical host. In this paper, we design an agile workflow microservice system for HPC applications with fast-start OSv. We consider improving HPC workflow performance from two aspects: single OSv startup time optimization and workflow orchestration optimization. For single OSv startup time optimization, we design a fast-start OSv by analyzing the process of OSv startup and finding an optimization by modifying OSv source code. In this way, we get nearly 50% improvement of startup time. For workflow orchestration optimization, we propose four optimization techniques to speed up the execution of workflow by jointly considering OSv and workflow features, namely: node fusion, node merge, image preload, boot delay. Furthermore, we utilize our fast startup OSv to design an orchestration system for efficiently building an agile HPC workflow microservice by Kubevirt. Our experimental results optimization microservice system reduces the execution time by 30% compared with the original deployment with docker.

关键词： Cloud computing Conferences Buildings Microservice architectures computer architecture Interference Containers

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SOFF: An OpenCL high-Level Synthesis Framework for FPGAs 20

SOFF: An OpenCL High-Level Synthesis Framework for FPGAs

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47th ACM/ieee Annual international symposium on computer architecture (ISCA)

作者： Jo, Gangwon Kim, Heehoon Lee, Jeesoo Lee, Jaejin ManyCoreSoft Seoul 08826 South Korea Seoul Natl Univ Dept Comp Sci & Engn Seoul 08826 South Korea

ISBN: (纸本)9781728146614

Recently, OpenCL has been emerging as a programming model for energy-efficient FPGA accelerators. However, the state-of-the-art OpenCL frameworks for FPGAs suffer from poor performance and usability. this paper proposes a high-level synthesis framework of OpenCL for FPGAs, called SOFF. It automatically synthesizes a datapath to execute many OpenCL kernel threads in a pipelined manner. It also synthesizes an efficient memory subsystem for the datapath based on the characteristics of OpenCL kernels. Unlike previous high-level synthesis techniques, we propose a formal way to handle variable-latency instructions, complex control flows, OpenCL barriers, and atomic operations that appear in real-world OpenCL kernels. SOFF is the first OpenCL framework that correctly compiles and executes all applications in the SPEC ACCEL benchmark suite except three applications that require more FPGA resources than are available. In addition, SOFF achieves the speedup of 1.33 over Intel FPGA SDK for OpenCL without any explicit user annotation or source code modification.

关键词： Accelerator architectures FPGAs high level synthesis parallel programming pipeline processing

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Optimization Techniques for Scheduling IoT tasks in Fog-based Environments

Optimization Techniques for Scheduling IoT tasks in Fog-base...

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international symposium on high Capacity Optical Networks and Enabling Technologies, HONET

作者： Rija Tariq Hareem Ashraf Maira Sohail Hasan Ali Khattak School of Electrical Engineering and Computer Science National University of Sciences and Technology (NUST) Islamabad Pakistan

ISBN: (纸本)9781665461986

Cloud computing has been around us for a while now, and everywhere we look around, data surrounds us. Data is transferred over a network and computed over some cloud platform. the concept of the fog layer has also been around, and there have been multiple implementations of how these two sets of layers can work together and implement an excellent and optimized structure. Numerous factors are involved in creating an architecture like that, including time, energy, network bandwidth, etc. Every solution presented tries to cater to most of these factors and gives the best possible outcome. But there has been a trade-off always. Such architecture has been here for many years. these solutions and many new ones are implemented to find a common optimal point. Such solutions can be divided into categories like bio-inspired algorithms, evolution-based algorithms, etc. there can also be a division based on these algorithms' heuristic and metaheuristic nature. this paper focuses on all these techniques and compares the objectives and limitations of previous implementations. this paper also pointed out majorly used algorithms repeatedly seen during this research and simulated on the same set of parameters to determine which solution presents a more efficient performance.

关键词： Cloud computing Costs Processor scheduling Smart cities Heuristic algorithms Metaheuristics computer architecture

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Fulcrum: a Simplified Control and Access Mechanism toward Flexible and Practical In-situ Accelerators 26

Fulcrum: a Simplified Control and Access Mechanism toward Fl...

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26th ieee international symposium on high performance computer architecture (HPCA)

作者： Lenjani, Marzieh Gonzalez, Patricia Sadredini, Elaheh Li, Shuangchen Xie, Yuan Akel, Ameen Eilert, Sean Stan, Mircea R. Skadron, Kevin Univ Virginia Charlottesville VA 22904 USA Univ Calif Santa Barbara Santa Barbara CA 93106 USA Micron Technol Inc Boise ID USA

ISBN: (纸本)9781728161495

In-situ approaches process data very close to the memory cells, in the row buffer of each subarray. this minimizes data movement costs and affords parallelism across subarrays. However, current in-situ approaches are limited to only row-wide bitwise (or few-bit) operations applied uniformly across the row buffer. they impose a significant overhead of multiple row activations for emulating 32-bit addition and multiplications using bitwise operations and cannot support operations with data dependencies or based on predicates. Moreover, with current peripheral logic, communication among subarrays is inefficient, and with typical data layouts, bits in a word are not physically adjacent. the key insight of this work is that in-situ, single-word ALUs outperform in-situ, parallel, row-wide, bitwise ALUs by reducing the number of row activations and enabling new operations and optimizations. Our proposed lightweight access and control mechanism, Fulcrum, sequentially feeds data into the single-word ALU and enables operations with data dependencies and operations based on a predicate. For algorithms that require communication among subarrays, we augment the peripheral logic with broadcasting capabilities and a previously-proposed method for low-cost inter-subarray data movement. the sequential processor also enables overlapping of broadcasting and computation, and reuniting bits that are physically adjacent. In order to realize true subarray-level parallelism, we introduce a lightweight column-selection mechanism through shifting one-hot encoded values. this technique enables independent column selection in each sub array. We integrate Fulcrum with Compress Express Link (CXL), a new interconnect standard. Fulcrum with one memory stack delivers on average (up to) 23.4 (76) x speedup over a server-class GPU, NVIDIA P100, with three stacks of HBM2 memory, (ii) 70 (228)x speedup per memory stack over the GPU, and (iii) 19 (178.9) x speedup per memory stack over an ideal model of

关键词： processing in memory (PIM) in-situ computing DRAM

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A Study of APIs for Graph Analytics Workloads 16

A Study of APIs for Graph Analytics Workloads

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16th ieee international symposium on Workload Characterization (IISWC)

作者： Lee, Hochan Wong, David Hoang, Loc Dathathri, Roshan Gill, Gurbinder Jatala, Vishwesh Kuck, David Pingali, Keshav Univ Texas Austin Austin TX 78712 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728176451

Traditionally, parallel graph analytics workloads have been implemented in systems like Pregel, GraphLab, Galois, and Ligra that support graph data structures and graph operations directly. An alternative approach is to express graph workloads in terms of sparse matrix kernels such as sparse matrix-vector and matrix-matrix multiplication. An API for these kernels has been defined by the GraphBLAS project. the SuiteSparse project has implemented this API on shared-memory platforms, and the LAGraph project is building a library of graph algorithms using this API. How does the matrix-based approach perform compared to the graph-based approach? Our experiments on a 56 core CPU show that for representative graph workloads, LAGraph/SuiteSparse solutions are 5x slower on the average than Galois solutions. We argue that this performance gap arises from inherent limitations of a matrix-based API: regardless of which architecture a matrixbased algorithm is run on, it is subject to the same inherent limitations of the matrix-based API.

关键词： graph analytics performance study Graph-BLAS high performance computing

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Large-scale and high-throughput QR Decomposition on an FPGA 27

Large-scale and High-throughput QR Decomposition on an FPGA

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Lee, Dajung Hagiescu, Andrei Pritsker, Dan Intel Corp San Diego CA 92131 USA Intel Corp Toronto ON Canada

ISBN: (纸本)9781728111315

the QR decomposition, also called the QR factorization, is one of core matrix operations that is used to solve a linear inverse/solver problem. We develop a high-throughput QR decomposition for large-scale matrices on FPGA. We refine the modified Gram-Schmit QRD algorithm into a hardware-friendly algorithmic flow and describe the core architecture in C. We synthesize our code using an Intel FPGA SDK for OpenCL targeting an Intel Arria 10 FPGA device.

关键词： Field programmable gate arrays Matrix decomposition performance evaluation throughput computer architecture Hardware Graphics processing units

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