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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Deep Reinforcement Agent for Failure-aware Job scheduling in high-performance computing

Deep Reinforcement Agent for Failure-aware Job scheduling in...

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international Conference on Parallel and Distributed Systems (ICPADS)

作者： Kang Yang Rongyu Cao Yueyuan Zhou Jiawei Zhang En Shao Guangming Tan State Key Laboratory of Computer Architecture Institute of Computing Technology CAS Beijing China University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781665408790

Job scheduling is crucial in high-performance computing (HPC), which is dedicated to deciding when and which jobs are allocated to the system and placing the jobs on which resources, by considering multiple scheduling goals. Along with the incremental of various resources and dazzling deep learning training (DLT) workloads, job failure becomes a quite common issue in HPC, which will affect user satisfaction and cluster utilization. To alleviate the influence of hardware and software errors as much as possible, in this paper, we aim to tackle the problem of failure-aware job scheduling in HPC clusters. Inspired by the success of previous studies of deep reinforcement learning-driven job scheduling, we propose a novel HPC scheduling agent named FARS (Failure-aware RL-based scheduler) by considering the effects of job failures. On the one hand, a neural network is applied to map the information of raw cluster and job states to job placement decisions. On the other hand, to consider the influence of job failure for user satisfaction and cluster utilization, FARS leverages make-span of the entire workload as the training objective. Additionally, effective exploration and experience replay techniques are applied to obtain effectively converged agent. To evaluate the capability of FARS, we design extensive trace-based simulation experiments with the popular DLT workloads. the experimental results show that, compared with the best baseline model, FARS obtains 5.69% improvement of average make-span under different device error rates. Together, our FARS is an ideal candidate for failure-aware job scheduler in HPC clusters.

关键词： Training Deep learning Processor scheduling Error analysis Computational modeling Conferences Neural networks

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EdgeIso: Effective performance Isolation for Edge Devices 34

EdgeIso: Effective Performance Isolation for Edge Devices

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34th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Nam, Yoonsung Choi, Yongjun Yoo, Byeonghun Eom, Hyeonsang Son, Yongseok Seoul Natl Univ Dept Comp Sci & Engn Seoul South Korea Chung Ang Univ Sch Comp Sci & Engn Seoul South Korea

ISBN: (纸本)9781728168760

Edges enable cloud services to be provided at low-latency and efficiently reduce the amount of transferred data by placing latency-critical tasks close to users. However, multi-tasking results in resource contention on edge devices, making it challenging to meet the service level objectives (SLOs) of tasks. Compared to the clouds, edges have relatively limited resources, but their tasks are required to meet a higher level of SLOs than clouds. Furthermore, modern edge devices equipped with additional accelerators (e.g., GPU) may worsen the resource contention due to the edge's integrated architecture, sharing the memory bandwidth between CPUs and accelerators. To address these challenges, we present EdgeIso, a light-weight scheduler that dynamically isolates the performance of tasks on edges. EdgeIso periodically monitors the resource contention and mitigates the contention to meet the SLOs of tasks by efficiently enforcing several isolation techniques (e.g., DVFS and core allocation) in an incremental manner. Moreover, it detects the changes of task executions or offered loads for tasks, thus handling high load fluctuations adaptively. We implement EdgeIso as a user-level scheduler on the Linux integrates into an NVIDIA Jetson TX2. Our experimental results show that EdgeIso improves the performance of the low-latency tasks significantly while improving resource efficiency compared with both the offloading and reservation scheme used in clouds.

关键词： edge computing resource management performance isolation latency-critical workloads

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Efficient FPGA Floorplanning for Partial Reconfiguration-Based Applications 27

Efficient FPGA Floorplanning for Partial Reconfiguration-Bas...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Deak, Norbert Cret, Octavian Hedesiu, Horia Natl Instruments Cluj Napoca Branch Cluj Napoca Romania Tech Univ Cluj Napoca Dept Comp Sci Cluj Napoca Romania Tech Univ Cluj Napoca Dept Elect Machines Cluj Napoca Romania

ISBN: (纸本)9781728111315

this paper introduces an efficient automatic floorplanning algorithm, which takes into account the heterogeneous architectures of modern FPGA families, as well as partial reconfiguration (PR) constraints, introducing the aspect ratio (AR) constraint to optimize routing. the algorithm generates possible placements of the partial modules, and then applies a recursive pseudo-bipartitioning heuristic search to find the best floorplan. the experiments show that its performance is significantly better than the one of other algorithms in this field.

关键词： Field programmable gate arrays computer architecture Heuristic algorithms Routing Linear programming Complexity theory computer science

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Scalable P4 Deparser for Speeds Over 100 Gbps 27

Scalable P4 Deparser for Speeds Over 100 Gbps

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Cabal, Jakub Benacek, Pavel Foltova, Jana Holub, Juraj CESNET ALE Zikova 4 Prague 16000 Czech Republic Brno Univ Technol Fac Informat Technol Bozetechova 2 Brno Czech Republic

ISBN: (纸本)9781728111315

the P4 language is a language suitable for the description of packet processing inside a network device. the typical P4 device consists of three main building blocks: Parser, Match+Action Tables and Deparser. the deparsing is the most challenging block because the main task of this block is to assemble the output packet based on changes in Match+Action Tables. this operation can be quite complicated in the case of high-speed networks. In this work, we present the scalable architecture (in term of the throughput) of a deparsing circuit which is suitable for implementation in FPGAs.

关键词： Field programmable gate arrays throughput computer architecture Clocks Resource management Switches Pipelines

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A high throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor 27

A High Throughput and Energy-Efficient Retina-Inspired Tone ...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Liu, Lili Xiang, Xiaoqiang Xie, Yuxiang Li, Yongjie Yan, Bo Zhou, Jun Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China

ISBN: (纸本)9781728111315

this paper presents a high throughput and energy-efficient retina inspired tone mapping processor. Several hardware design techniques have been proposed to achieve high throughput and high energy efficiency, including data partition based parallel processing with S-shape sliding, adjacent frame feature sharing, multi-layer convolution pipelining and convolution filter compression with zero skipping convolution. Compared with several state-of-the-art tone mapping processors, the proposed processor achieves higher throughput and energy efficiency. It is suitable for high-speed and energy-constrained video enhancement applications such as autonomous vehicle and drone monitoring.

关键词： throughput Energy efficiency Hardware Convolution computer architecture Retina Software

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Wire-Speed Multirate Accelerator for Aggregation Operations on Sorted Data 27

Wire-Speed Multirate Accelerator for Aggregation Operations ...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Jun, Sang-Woo Arvind Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA

ISBN: (纸本)9781728111315

We present an accelerator architecture for wire-speed aggregation of sorted key-value pairs on a wide datapath, in a bump-in-the-wire fashion. the presented accelerator is capable of maintaining wire-speed regardless of data distribution, even when (1) the aggregation function has multiple-cycle latency, and (2) the input stream is multi-rate, i.e., multiple elements arrive every cycle. To the best of our knowledge, it is the first accelerator architecture that satisfies both properties.

关键词： Aggregates computer science Accelerator architectures Electrical engineering Wires Arrays

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An Evaluation of the Communication performance of MEC-Dependent Services in 5G Networks

An Evaluation of the Communication Performance of MEC-Depend...

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ieee international symposium on Network computing and Applications

作者： Matthias Frei thomas Deinlein Reinhard German Anatoli Djanatliev Fraunhofer Institute for Integrated Circuits IIS Erlangen Germany Computer Networks and Communication Systems University of Erlangen-Nürnberg Germany

ISBN: (纸本)9781665495516

Remote infrastructure is going to assist prospective mobile services, but requires reliable and efficient network resources. Multi-Access Edge computing (MEC) and cellular networks starting from the fifth generation (5G) are two of the enabling technologies that are necessary to meet strong service level requirements. When service constraints cannot be met all the time, the service may be malfunctioning or even impossible. Impact factors can be user mobility, the network architecture, flexible topology changes, and orchestration decisions. We discuss these challenges while considering the technical integration possibilities. Mainly, we develop a MEC network simulation with a 5G cellular network and user mobility. Our aim is to respect and focus on network conditions for MEC-dependent services and to generate performance indicators for an example task offloading application. We vary the available 5G resources, the number of involved MEC nodes, and application-level behavior like the offloaded task complexity, i.e., computing duration and offloading interval. Additionally, we examine connection-oriented and stateless communication. Our results show that a dense MEC network is able to improve round-trip time (RTT) and jitter in high-load situations and can have a positive impact on service availability and reliability.

关键词： Cellular networks Multi-access edge computing 5G mobile communication Network architecture Jitter Topology Complexity theory

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Mocarabe: high-performance Time-Multiplexed Overlays for FPGAs

Mocarabe: High-Performance Time-Multiplexed Overlays for FPG...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Frederick Tombs Alireza Mellat Nachiket Kapre University of Waterloo Ontario Canada

Coarse-grained reconfigurable array (CGRA) overlays can improve dataflow kernel throughput by an order of magnitude over Vivado HLS. this is possible with a combination of carefully floorplanned high-frequency (645-768 MHz) design and a scalable, communication-aware compiler. Our 2D torus CGRA architecture supports versatile processing element (PE) functionality and a configurable number of communication channels to match application demands. Compared to recent FPGA overlays like CGRA-ME's ADRES and HyCUBE implementations, our design operates at 1.8-3.4× faster clock frequency, while scaling to an orders-of-magnitude larger array size of 19×69 on Xilinx Alveo U280. Our communication-aware compiler targets HLS objectives such as initiation interval (II) and minimizes communication cost using an integer linear programming (ILP) formulation. Unlike SDC schedulers in FPGA HLS tools, we treat data movement as a first-class citizen by encoding the space and time resources communication network of the overlay in the ILP formulation. Given the same constraints on operational resources as Vivado HLS, we can retain our target II and achieve up to 9.2× higher frequency. Our ILP scheduler outperforms a PathFinder space-time router implementation in quality of result by up to nearly 2×.

关键词： Program processors computer architecture Tools Integer linear programming throughput Encoding Communication networks

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A Research Retrospective on AMD's Exascale computing Journey 23

A Research Retrospective on AMD's Exascale Computing Journey

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Proceedings of the 50th Annual international symposium on computer architecture

作者： Gabriel H. Loh Michael J. Schulte Mike Ignatowski Vignesh Adhinarayanan Shaizeen Aga Derrick Aguren Varun Agrawal Ashwin M. Aji Johnathan Alsop Paul Bauman Bradford M. Beckmann Majed Valad Beigi Sergey Blagodurov Travis Boraten Michael Boyer William C. Brantley Noel Chalmers Shaoming Chen Kevin Cheng Michael L. Chu David Cownie Nicholas Curtis Joris Del Pino Nam Duong Alexandru Duțu Yasuko Eckert Christopher Erb Chip Freitag Joseph L. Greathouse Sudhanva Gurumurthi Anthony Gutierrez Khaled Hamidouche Sachin Hossamani Wei Huang Mahzabeen Islam Nuwan Jayasena John Kalamatianos Onur Kayiran Jagadish Kotra Alan Lee Daniel Lowell Niti Madan Abhinandan Majumdar Nicholas Malaya Srilatha Manne Susumu Mashimo Damon McDougall Elliot Mednick Michael Mishkin Mark Nutter Indrani Paul Matthew Poremba Brandon Potter Kishore Punniyamurthy Sooraj Puthoor Steven E. Raasch Karthik Rao Gregory Rodgers Marko Scrbak Mohammad Seyedzadeh John Slice Vilas Sridharan René van Oostrum Eric van Tassell Abhinav Vishnu Samuel Wasmundt Mark Wilkening Noah Wolfe Mark Wyse Adithya Yalavarti Dmitri Yudanov Advanced Micro Devices Inc. Bellevue WA USA Advanced Micro Devices Inc. Austin TX USA Advanced Micro Devices Inc. Santa Clara CA USA Advanced Micro Devices Inc. Boxborough MA USA Advanced Micro Devices Inc. Santa Clara WA USA Advanced Micro Devices Inc Bellevue WA USA Advanced Micro Devices Inc. Rochester NY USA Advanced Micro Devices Inc. Orlando FL USA Advanced Micro Devices Inc. San Diego CA USA Advanced Micro Devices Inc. Folsom CA USA

ISBN: (纸本)9798400700958

the pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale *** had the opportunity to contribute to the so-called "*Forward" programs from the DOE, which were a series of public-private partnerships focused on research and co-design activities covering compute architectures, interconnects, memory systems, chiplets and packaging, software stacks, applications, and more. Some of the research from these programs can now be found in the world's first exascale supercomputer, some were a little ahead of their time and may have an impact in the coming years, and others simply did not pan out. In this paper, we provide a retrospective of AMD's nearly decade-long research journey covering how we tried to predict the architecture of a supercomputer a decade into the future, what we got right, what we got wrong, and some of the insights and learnings that we discovered along the way.

关键词： exascale

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T2S-Tensor: Productively Generating high-performance Spatial Hardware for Dense Tensor Computations 27

T2S-Tensor: Productively Generating High-Performance Spatial...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Srivastava, Nitish Rong, Hongbo Barua, Prithayan Feng, Guanyu Cao, Huanqi Zhang, Zhiru Albonesi, David Sarkar, Vivek Chen, Wenguang Petersen, Paul Lowney, Geoff Herr, Adam Hughes, Christopher Mattson, Timothy Dubey, Pradeep Cornell Univ Ithaca NY 14853 USA Intel Santa Clara CA USA Georgia Inst Technol Atlanta GA 30332 USA Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781728111315

We present a language and compilation framework for productively generating high-performance systolic arrays for dense tensor kernels on spatial architectures, including FPGAs and CGRAs. It decouples a functional specification from a spatial mapping, allowing programmers to quickly explore various spatial optimizations for the same function. the actual implementation of these optimizations is left to a compiler. thus, productivity and performance are achieved at the same time. We used this framework to implement several important dense tensor kernels. We implemented dense matrix multiply for an Arria-10 FPGA and a research CGRA, achieving 88% and 92% of the performance of manually written, and highly optimized expert ("ninja") implementations in just 3% of their engineering time. three other tensor kernels, including MTTKRP, TTM and TTMc, were also implemented with high performance and low design effort, and for the first time on spatial architectures.

关键词： Optimization computer architecture Kernel Field programmable gate arrays Programming Hardware

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