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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata 27

Deep Packet Inspection in FPGAs via Approximate Nondetermini...

引用

27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Ceska, Milan Havlena, Vojtech Holik, Lukas Korenek, Jan Lengal, Ondrej Matousek, Denis Matousek, Jiri Semric, Jakub Vojnar, Tomas Brno Univ Technol Fac Informat Technol IT4I Ctr Excellence Brno Czech Republic

ISBN: (纸本)9781728111315

Deep packet inspection via regular expression (RE) matching is a crucial task of network intrusion detection systems (IDSes), which secure Internet connection against attacks and suspicious network traffic. Monitoring high-speed computer networks (100 Gbps and faster) in a single-box solution demands that the RE matching, traditionally based on finite automata (FAs), is accelerated in hardware. In this paper, we describe a novel FPGA architecture for RE matching that is able to process network traffic beyond 100 Gbps. the key idea is to reduce the required FPGA resources by leveraging approximate nondeterministic FAs (NFAs). the NFAs are compiled into a multi-stage architecture starting with the least precise stage with a high throughput and ending with the most precise stage with a low throughput. To obtain the reduced NFAs, we propose new approximate reduction techniques that take into account the profile of the network traffic. Our experiments showed that using our approach, we were able to perform matching of large sets of REs from SNORT, a popular IDS, on unprecedented network speeds.

关键词： Field programmable gate arrays computer architecture throughput Automata architecture Acceleration Hardware

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Pliant: Leveraging Approximation to Improve Datacenter Resource Efficiency 25

Pliant: Leveraging Approximation to Improve Datacenter Resou...

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Kulkarni, Neeraj Qi, Feng Delimitrou, Christina Cornell Univ Ithaca NY 14853 USA

ISBN: (纸本)9781728114446

Cloud multi-tenancy is typically constrained to a single interactive service colocated with one or more batch, low-priority services, whose performance can be sacrificed when deemed necessary. Approximate computing applications offer the opportunity to enable tighter colocation among multiple applications whose performance is important. We present Pliant, a lightweight cloud runtime that leverages the ability of approximate computing applications to tolerate some loss in their output quality to boost the utilization of shared servers. During periods of high resource contention, Pliant employs incremental and interference-aware approximation to reduce contention in shared resources, and prevent QoS violations for co-scheduled interactive, latency-critical services. We evaluate Pliant across different interactive and approximate computing applications, and show that it preserves QoS for all co-scheduled workloads, while incurring a 2.1% loss in output quality, on average.

关键词： Quality of service Approximate computing Runtime Cloud computing Interference Optimization Synchronization

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the Importance of Being X-Drop: high performance Genome Alignment on Reconfigurable Hardware

The Importance of Being X-Drop: High Performance Genome Alig...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Alberto Zeni Guido Walter Di Donato Lorenzo Di Tucci Marco Rabozzi Marco D. Santambrogio Informazione e Bioingegneria Politecnico di Milano Milan Italy Huxelerate S.r.l.

Pairwise sequence alignment accounts for the majority of key genome analysis applications' runtime. Because of the quadratic time complexity of exact alignment algorithms, the community is moving away from exact algorithms in favor of heuristics that only compute high-quality results. However, the state of the art lacks hardware-accelerated versions of these heuristic algorithms as the vast majority of the available solutions still rely on implementing exact alignment algorithms. Moreover, hardware-based implementations lack high-level APIs that can simplify their integration in commonly used genomic pipelines, hindering their applicability in real-world scenarios. In this context, we present the first high-performance FPGA implementation of the popular X-drop heuristic alignment algorithm and provide an easy-to-use API for its integration. On a Xilinx Alveo U280, our FPGA design achieves up to 5× speed-up over SeqAn, the state-of-the-art software version of the algorithm, running on two Intel Xeon processors using 80 CPU threads. Moreover, our design is also 3.45× faster than ksw2, a state-of-the-art vectorized alignment algorithm that performs a similar heuristic to the one employed in the X-drop algorithm. Finally, our implementation also outperforms LOGAN, a recently published GPU implementation of X-drop running on an Nvidia Tesla V100, by a factor of 1.5×.

关键词： Proteins Runtime Heuristic algorithms Software algorithms Genomics Graphics processing units computer architecture

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Initial Experiments with Duet Benchmarking: performance Testing Interference in the Cloud 27

Initial Experiments with Duet Benchmarking: Performance Test...

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ieee 27th international symposium on Modeling, Analysis, and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Bulej, Lubomir Horky, Vojtech Tuma, Petr Charles Univ Prague Fac Math & Phys Dept Distributed & Dependable Syst Malostranske Namesti 25 Prague 11800 1 Czech Republic

ISBN: (纸本)9781728149516;9781728149509

Accurate performance testing may require many measurements and therefore many machines to execute on. When many machines are needed, the cloud offers a tempting solution, however, measurements conducted in the cloud are generally considered unstable. In the context of comparing performance of two workloads, we propose a measurement procedure that improves accuracy by executing the workloads concurrently and using the measurements to filter outside interference. Depending on the platform used, experiments show average accuracy improvement ranging from 114% to 683% over sequential measurements on workloads running the ScalaBench suite with the Graal compiler.

关键词： Interference Cloud computing Virtual machining Task analysis Benchmark testing Time measurement

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Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator

Host Bypassing: Direct Data Piping from the Network to the H...

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ieee international symposium on Embedded Multicore Socs (MCSoC)

作者： Ralf Kundel Kadir Eryigit Jonas Markussen Carsten Griwodz Osama Abboud Rhaban Hark Ralf Steinmetz Multimedia Communications Lab Technical University of Darmstadt Germany Zoi TechCon GmbH Stuttgart Germany University of Oslo Norway Dolphin Interconnect Solutions AS Oslo Norway Huawei Technologies Munich Germany

ISBN: (纸本)9781728187525

computer networks have become very important and influential over the last years for many common services such as Internet connectivity as well as time-sensitive applications such as videotelephony. Furthermore, approaches like in-network computing enable the offloading of latency-critical and high-performance network functions into the network, e.g. 5G network functions, to enable such time-sensitive applications. In this work, we show how FPGAs in PCIe-based systems, which are typically used as hardware accelerators for latency-critical in-network functions, can be integrated into the data path. Our approach, named host bypassing, allows direct data transfer from the network interface to the accelerator and accomplishes substantial performance benefits over existing state-of-the-art approaches. Our detailed evaluation results demonstrate the possibility of achieving deterministic low latency while operating under heavy load without any packet loss. In addition, fewer CPU resources are required.

关键词： performance evaluation architecture Memory management Packet loss throughput Peer-to-peer computing Network interfaces

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A Scalable OpenCL-Based FPGA Accelerator For YOLOv2 27

A Scalable OpenCL-Based FPGA Accelerator For YOLOv2

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Xu, Ke Wang, Xiaoyun Wang, Dong Beijing Jiaotong Univ Inst Informat Sci Beijing 100044 Peoples R China Beijing Key Lab Adv Informat Sci & Network Techno Beijing 100044 Peoples R China

ISBN: (纸本)9781728111315

this paper implements an OpenCL-based FPGA accelerator for YOLOv2 on Arria-10 GX1150 FPGA board. the hardware architecture adopts a scalable pipeline design to support multi-resolution input image, and improves resource utilization by full 8-bit fixed-point computation and CONV+BN+Leaky-ReLU layer fusion technology. the proposed design achieves a peak throughput of 566 GOPs under 190 MHz working frequency. the accelerator could run YOLOv2 inference with 288 x 288 input resolution and tiny YOLOv2 with 416 x 416 input resolution at the speed of 35 and 71 FPS, respectively.

关键词： Field programmable gate arrays Kernel Convolution Hardware computer architecture Object detection Pipelines

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Optimizing Validation Phase of Hyperledger Fabric 27

Optimizing Validation Phase of Hyperledger Fabric

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ieee 27th international symposium on Modeling, Analysis, and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Javaid, Haris Hu, Chengchen Brebner, Gordon Xilinx Singapore Singapore Xilinx San Jose CA USA

ISBN: (纸本)9781728149516;9781728149509

Blockchain technologies are on the rise, and Hyperledger Fabric is one of the most popular permissioned blockchain platforms. In this paper, we re-architect the validation phase of Fabric based on our analysis from fine-grained breakdown of the validation phase's latency. Our optimized validation phase uses a chaincode cache during validation of transactions, initiates state database reads in parallel with validation of transactions, and writes to the ledger and databases in parallel. Our experiments reveal performance improvements of 2x for CouchDB and 1.3x for LevelDB. Notably, our optimizations can be adopted in a future release of Hyperledger Fabric.

关键词： Databases Peer-to-peer computing Fabrics throughput Optimization Blockchain

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Maverick: A Stand-alone CAD Flow for Partially Reconfigurable FPGA Modules 27

Maverick: A Stand-alone CAD Flow for Partially Reconfigurabl...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Glick, Dallon Grigg, Jesse Nelson, Brent Wirthlin, Michael Brigham Young Univ Dept Elect & Comp Engn NSF Ctr Space High Performance & Resilient Comp S Provo UT 84602 USA

ISBN: (纸本)9781728111315

this paper presents Maverick, a proof-of-concept computer-aided design (CAD) flow for generating reconfigurable modules (RMs) which target partial reconfiguration (PR) regions in field-programmable gate array (FPGA) designs. After an initial static design and PR region are created with Xilinx's Vivado PR flow, the Maverick flow can then compile and configure RMs onto that PR region-without the use of vendor tools. Maverick builds upon existing open source tools (Yosys, RapidSmith2, and Project X-Ray) to form an end-to-end compilation flow. this paper describes the Maverick flow and shows the results of it running on a PYNQ-Z1's ARM processor to compile a set of HDL designs to partial bitstreams. the resulting bitstreams were configured onto the PYNQ-Z1's FPGA fabric, demonstrating the feasibility of a single-chip embedded system which can both compile HDL designs to bitstreams and then configure them onto its own programmable fabric.

关键词： Field-programmable gate arrays Partial reconfiguration Electronic design automation and methodology RapidSmith

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Towards Robust Data-driven Parallel Loop Scheduling Using Bayesian Optimization 27

Towards Robust Data-driven Parallel Loop Scheduling Using Ba...

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ieee 27th international symposium on Modeling, Analysis, and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Kim, Khu-rai Kim, Youngjae Park, Sungyong Sogang Univ Elect Engn Dept Seoul South Korea Sogang Univ Comp Sci & Engn Dept Seoul South Korea

ISBN: (纸本)9781728149516;9781728149509

Efficient parallelization of loops is critical to improving the performance of high-performance computing applications. Many classical parallel loop scheduling algorithms have been developed to increase parallelization efficiency. Recently, workload-aware methods were developed to exploit the structure of workloads. However, both classical and workload-aware scheduling methods lack what we call robustness. that is, most of these scheduling algorithms tend to be unpredictable in terms of performance or have specific workload patterns they favor. this causes application developers to spend additional efforts in finding the best suited algorithm or tune scheduling parameters. this paper proposes Bayesian Optimization augmented Factoring Self-Scheduling (BO FSS), a robust data-driven parallel loop scheduling algorithm. BO FSS is powered by Bayesian Optimization (BO), a machine learning based optimization algorithm. We augment a classical scheduling algorithm, Factoring Self-Scheduling (FSS), into a robust adaptive method that will automatically adapt to a wide range of workloads. To compare the performance and robustness of our method, we have implemented BO FSS and other loop scheduling methods on the OpenMP framework. A regret-based metric called performance regret is also used to quantify robustness. Extensive benchmarking results show that BO FSS performs fairly well in most workload patterns and is also very robust relative to other scheduling methods. BO FSS achieves an average of 4% performance regret. this means that even when BO FSS is not the best performing algorithm on a specific workload, it stays within a 4 percentage points margin of the best performing algorithm.

关键词： Parallel Loop Scheduling Bayesian Optimization Parallel computing OpenMP

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Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks 25

Bit Prudent In-Cache Acceleration of Deep Convolutional Neur...

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Wang, Xiaowei Yu, Jiecao Augustine, Charles Iyer, Ravi Das, Reetuparna Univ Michigan Ann Arbor MI 48109 USA Intel Corp Santa Clara CA 95051 USA

ISBN: (纸本)9781728114446

We propose Bit Prudent In-Cache Acceleration of Deep Convolutional Neural Networks - an in-SRAM architecture for accelerating Convolutional Neural Network (CNN) inference by leveraging network redundancy and massive parallelism. the network redundancy is exploited in two ways. First, we prune and fine-tune the trained network model and develop two distinct methods - coalescing and overlapping to run inferences efficiently with sparse models. Second, we propose an architecture for network models with a reduced bit width by leveraging bit-serial computation. Our proposed architecture achieves a 17.7x/3.7x speedup over server class CPU/GPU, and a 1.6x speedup compared to the relevant in-cache accelerator, with 2% area overhead each processor die, and no loss on top-1 accuracy for AlexNet. With a relaxed accuracy limit, our tunable architecture achieves higher speedups.

关键词： In-Memory computing Cache Neural Network Pruning Low Precision Neural Network

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