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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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2d-3d Hierarchical Feature Fusion Network For Segmentation Of Bone Structure In Knee Mr Image

2d-3d Hierarchical Feature Fusion Network For Segmentation O...

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ieee international symposium on Biomedical Imaging

作者： Hui Wang Demin Yao Jiayi Chen Yanjing Liu Wensheng Li Yonghong Shi Digital Medical Research Center School of Basic Medical Sciences Fudan University Shanghai China Shanghai Key Laboratory of Medical Image Computing and Computer Assisted Intervention Fudan University Shanghai China. Histology and Embryology School of Basic Medical Sciences Fudan University Shanghai China.

ISBN: (纸本)9781665412469;9781665429474

Automatic segmentation of knee bone structures is an important task in orthopedics diagnosis of knee disease based on MRI images. Inspired by doctors' diagnosis of knee in sagittal plane of MR image, we propose to first calculate the sagittal maximum intensity projection (MIP) of MR image, then construct a high precision 2D-3D hierarchical feature fusion network for automatic segmentation of knee based on convolutional encoding and decoding architecture. It includes: 1) A 2D bypass network extracting global features based on MIP; 2) A 3D backbone network calculating local details based on MR volume; 3) A feature fusion module integrating 2D global context and 3D local details hierarchically. Particularly, the global features as anchor points will be fused with the local details at each level of the encoding path to enrich the context of local details and improve the segmentation accuracy. Our method is verified on SKI10 dataset. the average dice coefficients of femur, femoral cartilage, tibia and tibia cartilage are 0.978, 0.848, 0.979 and 0.848, respectively, and the segmentation performance is far better than the state-of-the-art methods.

关键词： Image segmentation three-dimensional displays Image coding Magnetic resonance imaging Semantics Medical services Feature extraction

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Yosys+nextpnr: An open source framework from verilog to bitstream for commercial FPGAS 27

Yosys+nextpnr: An open source framework from verilog to bits...

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27th Annual ieee international symposium on Field-Programmable Custom computing Machines, FCCM 2019

作者： Shah, David Hung, Eddie Wolf, Clifford Bazanski, Serge Gisselquist, Dan Milanovic, Miodrag Symbiotic EDA Vienna Austria Dept. of Electrical and Electronic Engineering Imperial College London United Kingdom Dept. of Electrical and Computer Engineering University of British Columbia Canada

ISBN: (纸本)9781728111315

this paper introduces a fully free and open source software (FOSS) architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement, routing, and bitstream generation. Currently, this flow supports two commercially available FPGA families, Lattice iCE40 (up to 8K logic elements) and Lattice ECP5 (up to 85K elements) and has been hardware-proven for custom-computing machines including a low-power neural-network accelerator and an OpenRISC system-on-chip capable of booting Linux. Both Yosys and nextpnr have been engineered in a highly flexible manner to support many of the features present in modern FPGAs by separating architecture-specific details from the common mapping *** framework is demonstrated on a longest-path case study to find an atypical single source-sink path occupying up to 45% of all on-chip wiring. © 2019 ieee.

关键词： Field programmable gate arrays (FPGA)

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GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Framework 27

GhostSZ: A Transparent FPGA-Accelerated Lossy Compression Fr...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Xiong, Qingqing Patel, Rushi Yang, Chen Geng, Tong Skjellum, Anthony Herbordt, Martin C. Boston Univ Dept Elect & Comp Engn Boston MA 02215 USA Univ Tennessee Simctr Chattanooga TN USA Univ Tennessee Dept Comp Sci & Engn Chattanooga TN USA

ISBN: (纸本)9781728111315

high-performance computing (HPC) applications often generate enormous amounts of data that must be transferred for check-pointing, in situ processing, or post-execution analysis. To reduce the related network traffic and storage consumption, lossy compression schemes that target scientific data are often used. SZ compression emerged three years ago and has gained much attention because of its high compression ratio. However, performing SZ compression can take half a day per Terabyte of data;this could be a drawback to adoption. We propose GhostSZ an FPGA framework for accelerating tasks in SZ at line rate, and so transparently. the critical problem to be overcome is the tight data dependence central to SZ. GhostSZ solves this with a data transfer path having novel staged hardware. We test our implementation with both synthetic and real HPC application data and show 9.5x-80x core versus pipeline speedup over the optimized production version running on a state-of-the-art CPU and 8.2x per chip. Much of the variance in performance is due to the FPGA already running at line rate and so benefiting less from optimizations applicable to the CPU only on the most favorable data sets. the significance of this work is the possibility of a major reduction in required networking and storage in HPC installations. For example, using GhostSZ, fewer than 10 FPGAs would be sufficient to handle the entire I/O bandwidth of the top entry on the latest IO-500 list.

关键词： Lossy Compression In-Line Acceleration FPGAs high-performance computing

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Analyzing the Impact of Operating System Activity of different Linux Distributions in a Distributed Environment 27

Analyzing the Impact of Operating System Activity of differe...

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27th Euromicro international Conference on Parallel, Distributed and Network-Based Processing (PDP)

作者： Giorgi, Roberto Procaccini, Marco Khalili, Farnam Univ Siena Dept Informat Engn & Math Siena Italy Univ Florence Dept Informat Engn Florence Italy

ISBN: (纸本)9781728116440

A rise in the number of threads in large-scale applications running on multi-node architectures makes operating system activity increasingly more relevant. therefore, evaluation methodologies need to account for these activities. We decided to build our evaluation environment through the COTSon simulator. Moreover, our environment permits flexible Design Space Exploration (DSE) by making easy the management of many experiments and the characterizations of Operating System (OS) activity. In this paper, we show the result analysis tool flow and the OS impact of different Linux distributions running on a distributed environment consisting of several nodes with a full OS. In order to quantify our results, we use matrix multiplication benchmark executed through a DataFlow model, named DataFlow-threads(DF-threads). We analyze key metrics like L2 cache miss rate, execution cycles, data access latency, and kernel cycles showing up to 60% performance variations among the different OS distributions.

关键词： performance evaluation computer architecture computer simulation Matrix Multiply Distributed computing high performance computing Operating systems

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Approximation with Error Bounds in Spark 27

Approximation with Error Bounds in Spark

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ieee 27th international symposium on Modeling, Analysis, and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Hu, Guangyan Rigo, Sandro Zhang, Desheng thu Nguyen Rutgers State Univ New Brunswick NJ 08854 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781728149516;9781728149509

Many decision-making queries are based on aggregating massive amounts of data, where sampling is an important approximation technique for reducing execution times. It is important to estimate error bounds when sampling to help users balance between precision and performance. However, error bound estimation is challenging because data processing pipelines often transform the input dataset in complex ways before computing the final aggregated values. In this paper, we introduce a sampling framework to support approximate computing with estimated error bounds in Spark. Our framework allows sampling to be performed at multiple arbitrary points within a sequence of transformations preceding an aggregation operation. the framework constructs a data provenance tree to maintain information about how transformations are clustering output data items to be aggregated. It then uses the tree and multi-stage sampling theories to compute the approximate aggregate values and corresponding error bounds. When information about output keys are available early, the framework can also use adaptive stratified reservoir sampling to avoid (or reduce) key losses in the final output and to achieve more consistent error bounds across popular and rare keys. Finally, the framework includes an algorithm to dynamically choose sampling rates to meet user-specified constraints on the CDF of error bounds in the outputs. We have implemented a prototype of our framework called ApproxSpark and used it to implement five approximate applications from different domains. Evaluation results show that ApproxSpark can (a) significantly reduce execution time if users can tolerate small amounts of uncertainties and, in many cases, loss of rare keys, and (b) automatically find sampling rates to meet user-specified constraints on error bounds. We also explore and discuss extensively tradeoffs between sampling rates, execution time, accuracy and key loss.

关键词： approximate computing error bounds data processing multi-stage sampling stratified sampling Spark

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Dynamic Control-as-a-Service provisioning in Fog computing 27

Dynamic Control-as-a-Service provisioning in Fog computing

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27th international Conference on Software, Telecommunications and computer Networks (SoftCOM)

作者： Souza Costa, Marcus Vinicius Souza, Vitor Barbosa Araujo Junior, Socrates S. Univ Fed Vicosa Informat Dept DPI Vicosa MG Brazil

ISBN: (纸本)9789532900880

the Internet of things is a technological revolution that is transforming several application domains. It has brought a number of solutions and alternatives and is one of the pillars of Industry 4.0. Since several current and future IoT applications will require near-zero communication latency, Fog computing was recently proposed as an extension of the Cloud paradigm to the edge of the network. In the collaborative scenario envisioned by Fog computing, a fog controller is an entity responsible for mapping end-user service requests into the most suitable resources at the edge of the network. However, given the high dinamicity and heterogeneity perceived in this scenario, we argue for the benefits of the dynamic deployment of fog controllers (Control-as-a-Service) according to, for instance, the amount of underlying resources and their characteristics. this work introduces a rank-based weighted distributed algorithm that considers distinct characteristics of interest to select nodes capable of playing the controller's role at the edge of the network. In the performed experiments, we analyze the convergence time of the proposed algorithm and compare the frequency on controller changes in our approach with an adapted version of the well-known LEACH protocol, which was tailored to fulfill our scenarios' demands. In four distinct scenarios, the results show a reduction range varying from 68% to 95% on the frequency for selecting new controllers when comparing our proposal to the comparative method. Furthermore, the average latency for selecting the controller is low even in scenarios with increased number of candidates.

关键词： Fog computing Ranking Dynamic controller selection IoT Control-as-a-Service

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Cost-effective Energy Monitoring of a Zynq-based Real-time System including dual Gigabit Ethernet 27

Cost-effective Energy Monitoring of a Zynq-based Real-time S...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Geier, Martin Faller, Dominik Braendle, Marian Chakraborty, Samarjit Tech Univ Munich Chair Real Time Comp Syst Munich Germany

ISBN: (纸本)9781728111315

Recent FPGA architectures integrate various power management features already established in CPU-driven SoCs to reach more energy-sensitive application domains such as, e.g., automotive and robotics. this also qualifies hybrid Programmable SoCs (pSoCs) that combine fixed-function SoCs with configurable FPGA fabric for heterogeneous Real-time Systems (RTSs), which operate under predefined latency and power constraints in safety-critical environments. their complex application-specific computation and communication (incl. I/O) architectures result in highly varying power consumption, which requires precise voltage and current sensing on all relevant supply rails to enable dependable evaluation of available and novel power management techniques. In this paper, we propose a low-cost 18-channel 16-bit-resolution measurement system capable of over 200 kSPS (kilo-samples per second) for instrumentation of current pSoC development boards. In addition, we propose to include crucial I/O components such as Ethernet PHYs into the power monitoring to gain a holistic view on the RTS's temporal behavior covering not only computation on FPGA and CPUs, but also communication in terms of, e.g., reception of sensor values and transmission of actuation signals. We present an FMC-sized implementation of our measurement system combined with two Gigabit Ethernet PHYs and one HDMI input. Paired with Xilinx' ZC702 development board, we are able to synchronously acquire power traces of a Zynq pSoC and the two PHYs precise enough to identify individual Ethernet frames. [GRAPHICS] .

关键词： Ethernet Field programmable gate arrays Monitoring Real-time systems computer architecture Rails Current measurement

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An Intelligent Game theory Framework for Detecting Advanced Persistent threats

An Intelligent Game Theory Framework for Detecting Advanced ...

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international Conference on Parallel and Distributed Systems (ICPADS)

作者： Hao Yan Qianzhen Zhang Junjie Xie Ziyue Lu Sheng Chen Deke Guo College of Intelligence and Computing Tianjin University Tianjin China Science and Technology on Information Systems Engineering Laboratory National University of Defense Technology Changsha Hunan China Institute of Systems Engineering AMS Beijing China

ISBN: (纸本)9781665408790

the advanced persistent threat (APT) is a stealthy cyber attack perpetrated by a group that gains unauthorized access to a computer network and remains undiscovered to steal specific data and resources. Fast detection and defense of APT attacks are critical tasks in cyber security. Previous works use simple feature extraction and classification methods to distinguish APT information flow from the normal one. However, APT attacks are latent, with very little flow and mixed in many normal information flows. Moreover, APT attacks can adjust their behavior according to the environment, making it challenging to be discovered and extract features. Meanwhile, dynamic information flow tracking (DIFT) is a tool for tracking information flow, which can also adjust the marking strategy according to the environment and is often used to track and detect APT information flow. On the other hand, game theory is a mathematical model that expresses the game of two or more parties. therefore, this motivates us to model a game theory to solve the above challenge. In this paper, to solve the above obstacles, we propose an intelligent game theory framework named DPS, which models the strategic interaction between APTs and DIFT and aims to get a high reward for DIFT. Our proposed DPS framework utilizes deep reinforcement learning to find the Nash equilibrium. the game model is a nonzero-sum, average reward stochastic game. Specifically, we design a subgraph pruning strategy and deep Q-network to guide the player in exploring new strategies in the information flow graph. Finally, we implement our framework to compute an optimal defender strategy to defend cyber security. Based on 2 real-world datasets, the experiment results demonstrate that the DPS framework can delay APT intrusions under equilibrium in 3 epochs and get a better reward than the Uniform policy.

关键词： Training performance evaluation Stochastic processes Games Reinforcement learning Feature extraction Nash equilibrium

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SparsePipe: Parallel Deep Learning for 3D Point Clouds

SparsePipe: Parallel Deep Learning for 3D Point Clouds

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international Conference on high performance computing

作者： Keke Zhai Pan He Tania Banerjee Anand Rangarajan Sanjay Ranka Department of Computer and Information Science and Engineering University of Florida University of Florida

We propose SparsePipe, an efficient and asynchronous parallelism approach for handling 3D point clouds with multi-GPU training. SparsePipe is built to support 3D sparse data such as point clouds. It achieves this by adopting generalized convolutions with sparse tensor representation to build expressive high-dimensional convolutional neural networks. Compared to dense solutions, the new models can efficiently process irregular point clouds without densely sliding over the entire space, significantly reducing the memory requirements and allowing higher resolutions of the underlying 3D volumes for better performance. SparsePipe exploits intra-batch parallelism that partitions input data into multiple processors and further improves the training throughput with inter-batch pipelining to overlap communication and computing. Besides, it suitably partitions the model when the GPUs are heterogeneous such that the computing is load-balanced with reduced communication overhead. Using experimental results on an eight-GPU platform, we show that SparsePipe can parallelize effectively and obtain better performance on current point cloud benchmarks for both training and inference, compared to its dense solutions.

关键词： Training three-dimensional displays Tensors Program processors Computational modeling Memory management Distributed databases

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HyPar: Towards Hybrid Parallelism for Deep Learning Accelerator Array 25

HyPar: Towards Hybrid Parallelism for Deep Learning Accelera...

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Song, Linghao Mao, Jiachen Zhuo, Youwei Qian, Xuehai Li, Hai Chen, Yiran Duke Univ Durham NC 27706 USA Univ Southern Calif Los Angeles CA 90089 USA

ISBN: (纸本)9781728114446

With the rise of artificial intelligence in recent years, Deep Neural Networks (DNNs) have been widely used in many domains. To achieve high performance and energy efficiency, hardware acceleration (especially inference) of DNNs is intensively studied both in academia and industry. However, we still face two challenges: large DNN models and datasets, which incur frequent off-chip memory accesses;and the training of DNNs, which is not well-explored in recent accelerator designs. To truly provide high throughput and energy efficient acceleration for the training of deep and large models, we inevitably need to use multiple accelerators to explore the coarse-grain parallelism, compared to the fine-grain parallelism inside a layer considered in most of the existing architectures. It poses the key research question to seek the best organization of computation and dataflow among accelerators. In this paper, we propose a solution HYPAR to determine layer-wise parallelism for deep neural network training with an array of DNN accelerators. HYPAR partitions the feature map tensors (input and output), the kernel tensors, the gradient tensors, and the error tensors for the DNN accelerators. A partition constitutes the choice of parallelism for weighted layers. the optimization target is to search a partition that minimizes the total communication during training a complete DNN. To solve this problem, we propose a communication model to explain the source and amount of communications. then, we use a hierarchical layer-wise dynamic programming method to search for the partition for each layer. HYPAR is practical: the time complexity for the partition search in HYPAR is linear. We apply this method in an HMC-based DNN training architecture to minimize data movement. We evaluate HYPAR with ten DNN models from classic Lenet to large-size model VGGs, and the number of weighted layers of these models range from four to nineteen. Our evaluation finds that: the default Model Parallelism

关键词： Parallel processing Training Data models Neural networks computer architecture Acceleration

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