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46th international symposium on computer architecture (ISCA) / Workshop on computer architecture Education (WCAE)

作者： Cai, Ruizhe Ren, Ao Chen, Olivia Liu, Ning Ding, Caiwen Qian, Xuehai Han, Jie Luo, Wenhui Yoshikawa, Nobuyuki Wang, Yanzhi Northeastern Univ Boston MA 02115 USA Yokohama Natl Univ Yokohama Kanagawa Japan Univ Southern Calif Los Angeles CA 90089 USA Univ Alberta Edmonton AB Canada

ISBN: (纸本)9781450366694

the Adiabatic Quantum-Flux-Parametron (AQFP) superconducting technology has been recently developed, which achieves the highest energy efficiency among superconducting logic families, potentially 104-105 gain compared with state-of-the-art CMOS. In 2016, the successful fabrication and testing of AQFP-based circuits with the scale of 83,000 JJs have demonstrated the scalability and potential of implementing largescale systems using AQFP. As a result, it will be promising for AQFP in high-performance computing and deep space applications, with Deep Neural Network (DNN) inference acceleration as an important example. Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature since each AQFP logic gate is connected with an AC clock signal, which increases the difficulty to avoid RAW hazards;the second is the unique opportunity of true random number generation (RNG) using a single AQFP buffer, far more efficient than RNG in CMOS. We point out that these two characteristics make AQFP especially compatible with the stochastic computing (SC) technique, which uses a time-independent bit sequence for value representation, and is compatible with the deep pipelining nature. Further, the application of SC has been investigated in DNNs in prior work, and the suitability has been illustrated as SC is more compatible with approximate computations. this work is the first to develop an SC-based DNN acceleration framework using AQFP technology. the deep-pipelining nature of AQFP circuits translates into the difficulty in designing accumulators/counters in AQFP, which makes the prior design in SC-based DNN not suitable. We overcome this limitation taking into account different properties in CONV and FC layers: (i) the inner product calculation in FC layers has more number of inputs than that in CONV layers;(ii) accurate activation function is critical in CONV rather than FC layers. Based on these observations, we propose (i) accurate inte

关键词： Stochastic computing Deep Learning Adiabatic Quantum-Flux-Parametron Superconducting

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A Scalable Priority-Aware Approach to Managing Data Center Server Power 25

A Scalable Priority-Aware Approach to Managing Data Center S...

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Li, Yang Lefurgy, Charles R. Rajamani, Karthick Allen-Ware, Malcolm S. Silva, Guillermo J. Heimsoth, Daniel D. Ghose, Saugata Mutlu, Onur IBM Corp Armonk NY 10504 USA Carnegie Mellon Univ Pittsburgh PA 15213 USA Swiss Fed Inst Technol Zurich Switzerland

ISBN: (纸本)9781728114446

Power management is a key component of modern data center design. Power managers must (1) ensure the cost- and energy-efficient utilization of the data center infrastructure, (2) maintain availability of the services provided by the center, and (3) address environmental concerns associated with the center's power consumption. While several power management techniques have been proposed and deployed in production data centers, there are still many challenges to comprehensive data center power management. this is particularly true in public cloud environments, where different jobs have different priority levels, and where high availability is critical. One example of the challenges facing public cloud data centers involves power capping. As power delivery must be highly reliable and tolerate wide variation in the load drawn by the data center components, the power infrastructure (e.g., power supplies, circuit breakers, UPS) has high redundancy and overprovisioning. During normal operation (i.e., typical server power demands, and no failures in the center), the power infrastructure is significantly underutilized. Power capping is a common solution to reduce this underutilization, by allowing more servers to be added safely (i.e., without power shortfalls) to the existing power infrastructure, and throttling power consumption in the infrequent cases where the demanded power exceeds the provisioned power capacity to avoid shortfalls. However, state-of-the-art power capping solutions are (1) not directly applicable to the redundant power infrastructure used in highly-available data centers;and (2) oblivious to differing workload priorities across the entire center when power consumption needs to be throttled, which can unnecessarily slow down high prioritywork. To address this need, we develop CapMaestro, a new power management architecture with three key features for public cloud data centers. First, CapMaestro is designed to work with multiple power feeds (i.e., sources

关键词： Servers Power demand Cloud computing Power system management Data center power Feeds

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performance Comparison of Terraform and Cloudify as Multicloud Orchestrators

Performance Comparison of Terraform and Cloudify as Multiclo...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Leonardo Rebouças de Carvalho Aleteia Patricia Favacho de Araujo Dept. of Computer Science University of Brasília Brasília Brazil

ISBN: (数字)9781728160955

Studies indicate that by 2022 multicloud models will reach 75% of the cloud computing market. To handle the high-featured set of computing capability on this paradigm, often called "Sky computing", infrastructure tools such as cloud orchestrators has emerged. this paper analyzes the most referenced tools in the literature such as Cloudify, Heat, CloudFormation, Terraform and Cloud Assembly, as well as the TOSCA standard. the literature review, complemented by a practical experiment, revealed that Terraform and Cloudify presents great affinity with Sky computing scenarios. In the experiment Terraform outperformed Cloudify in several aspects.

关键词： Cloud computing Heating systems Tools Organizations Object oriented modeling Computational modeling computer architecture

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WarpCore: A Library for fast Hash Tables on GPUs

WarpCore: A Library for fast Hash Tables on GPUs

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international Conference on high performance computing

作者： Daniel Jünger Robin Kobus André Müller Christian Hundt Kai Xu Weiguo Liu Bertil Schmidt Institute of Computer Science Johannes Gutenberg University Mainz Germany Institute of Computer Science Johannes Gutenberg University Mainz Germany NVIDIA AI Technology Center Luxembourg School of Software Shandong University Jinan China

Hash tables are ubiquitous. Properties such as an amortized constant time complexity for insertion and querying as well as a compact memory layout make them versatile associative data structures with manifold applications. the rapidly growing amount of data emerging in many fields motivated the need for accelerated hash tables designed for modern parallel architectures. In this work, we exploit the fast memory interface of modern GPUs together with a parallel hashing scheme tailored to improve global memory access patterns, to design WarpCore - a versatile library of hash table data structures. Unique device-sided operations allow for building high performance data processing pipelines entirely on the GPU. Our implementation achieves up to 1.6 billion inserts and up to 4.3 billion retrievals per second on a single GV100 GPU thereby outperforming the state-of-the-art solutions cuDPP, SlabHash, and NVIDIA RAPIDS cuDF. this performance advantage becomes even more pronounced for high load factors of over 90%. To overcome the memory limitation of a single GPU, we scale our approach over a dense NVLink topology which gives us close-to-optimal weak scaling on DGX servers. We further show how WarpCore can be used for accelerating a real world bioinformatics application (metagenomic classification) with speedups of over two orders-of-magnitude against state-of-the-art CPU-based solutions. WarpCore is open source software written in C++/CUDA-C and can be downloaded at https://***/sleeepyjack/warpcore.

关键词： performance evaluation Graphics processing units Optical wavelength conversion Data structures throughput Libraries Parallel architectures

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Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks 13

Many Universal Convolution Cores for Ensemble Sparse Convolu...

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ieee 13th international symposium on Embedded Multicore/Many-Core Systems-on-Chip (MCSoC)

作者： Kuramochi, Ryosuke Sada, Youki Shimoda, Masayuki Sato, Shimpei Nakahara, Hiroki Tokyo Inst Technol Tokyo Japan

ISBN: (纸本)9781728148823

A convolutional neural network (CNN) is one of the most successfully used neural networks and it is widely used for many embedded computer vision tasks. However, it requires a massive number of multiplication and accumulation (MAC) computations with high-power consumption to realize it, and higher recognition accuracy is desired for modern tasks. In the paper, we apply a sparseness technique to generate a weak classifier to build an ensemble CNN. there is a trade-off between recognition accuracy and inference speed, and we control sparse (zero weight) ratio to make an excellent performance and better recognition accuracy. We use P sparse weight CNNs with a dataflow pipeline architecture that hides the performance overhead for multiple CNN evaluation on the ensemble CNN. We set an adequate sparse ratio to adjust the number of operation cycles in each stage. the proposed ensemble CNN depends on the dataset quality and it has different layer configurations. We propose a universal convolution core to realize variations of modern convolutional operations, and extend it to many cores with pipelining architecture to achieve high-throughput operation. therefore, while computing efficiency is poor on GPUs which is unsuitable for a sparseness convolution, on our universal convolution cores can realize an architecture with excellent pipeline efficiency. We measure the trade-off between recognition accuracy and inference speed using existing benchmark datasets and CNN models. By setting the sparsity ratio and the number of predictors appropriately, high-speed architectures are realized on the many universal covers while the recognition accuracy is improved compared to the conventional single CNN realization. We implemented the prototype of many universal convolution cores on the Xilinx Kintex UltraScale+ FPGA, and compared with the desktop GPU realization of the ensembling, the proposed many core based accelerator for the ensemble sparse CNN is 3.09 times faster, 4.20 times low

关键词： Convolution Pipeline processing computer architecture Graphics processing units Task analysis Two dimensional displays Acceleration

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Cambricon-F: Machine Learning computers with Fractal von Neumann architecture 19

Cambricon-F: Machine Learning Computers with Fractal von Neu...

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46th international symposium on computer architecture (ISCA) / Workshop on computer architecture Education (WCAE)

作者： Zhao, Yongwei Du, Zidong Guo, Qi Liu, Shaoli Li, Ling Xu, Zhiwei Chen, Tianshi Chen, Yunji Chinese Acad Sci Inst Comp Technol SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Beijing Peoples R China Cambricon Tech Ltd Beijing Peoples R China Chinese Acad Sci Inst Software Beijing Peoples R China

ISBN: (纸本)9781450366694

Machine learning techniques are pervasive tools for emerging commercial applications and many dedicated machine learning computers on different scales have been deployed in embedded devices, servers, and data centers. Currently, most machine learning computer architectures still focus on optimizing performance and energy efficiency instead of programming productivity. However, with the fast development in silicon technology, programming productivity, including programming itself and software stack development, becomes the vital reason instead of performance and power efficiency that hinders the application of machine learning computers. In this paper, we propose Cambricon-F, which is a series of homogeneous, sequential, multi-layer, layer-similar, machine learning computers with the same ISA. A Cambricon-F machine has a fractal von Neumann architecture to iteratively manage its components: it is with von Neumann architecture and its processing components (sub-nodes) are still Cambricon-F machines with von Neumann architecture and the same ISA. Since different Cambricon-F instances with different scales can share the same software stack on their common ISA, Cambricon-Fs can significantly improve the programming productivity. Moreover, we address four major challenges in Cambricon-F architecture design, which allow Cambricon-F to achieve a high efficiency. We implement two Cambricon-F instances at different scales, i.e., Cambricon-F100 and Cambricon-F1. Compared to GPU based machines (DGX-1 and 1080Ti), Cambricon-F instances achieve 2.82x, 5.14x better performance, 8.37x, 11.39x better efficiency on average, with 74.5%, 93.8% smaller area costs, respectively.

关键词： computer architecture fractals learning (artificial intelligence) power aware computing power aware computing computer architecture Fractals Artificial Intelligence Machine Learning computers Programming different scale Building construction architecture Si technology Embedded device

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PIM-VR: Erasing Motion Anomalies In highly-Interactive Virtual Reality World With Customized Memory Cube 25

PIM-VR: Erasing Motion Anomalies In Highly-Interactive Virtu...

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25th ieee international symposium on high performance computer architecture (HPCA)

作者： Xie, Chenhao Zhang, Xingyao Li, Ang Fu, Xin Song, Shuaiwen Leon Univ Houston ECE Dept ECMOS Lab Houston TX 77204 USA Pacific Northwest Natl Lab HPC Grp Richland WA 99352 USA

ISBN: (纸本)9781728114446

With the revolutionary innovations emerging in the computer graphics domain, virtual reality (VR) has become increasingly popular and shown great potential for entertainment, medical simulation and education. In the highly interactive VR world, the motion-to-photon delay (MPD) which represents the delay from users' head motion to the responded image displayed on their head devices, is the most critical factor for a successful VR experience. Long MPD may cause users to experience significant motion anomalies: judder, lagging and sickness. In order to achieve the short MPD and alleviate the motion anomalies, asynchronous time warp (ATW) which is known as an image re-projection technique, has been proposed by VR vendors to map the previously rendered frame to the correct position using the latest head-motion information. However, after a careful investigation on the efficiency of the current GPU-accelerated ATW through executing real VR applications on modern VR hardware, we observe that the state-of-the-art ATW technique cannot deliver the ideal MPD and often misses the refresh deadline, resulting in reduced frame rate and motion anomalies. this is caused by two major challenges: inefficient VR execution model and intensive off-chip memory accesses. To tackle these, we propose a preemption-free Processing-In-Memory based ATW design which asynchronously executes ATW within a 3D-stacked memory, without interrupting the rendering tasks on the host GPU. We also identify a redundancy reduction mechanism to further simplify and accelerate the ATW operation. A comprehensive evaluation of our proposed design demonstrates that our PIM-based ATW can achieve the ideal MPD and provide superior user experience. Finally, we provide a design space exploration to showcase different design choices for the PIM-based ATW design, and the results show that our design scales well in future VR scenarios with higher frame resolution and even lower ideal MPD.

关键词： Rendering (computer graphics) Graphics processing units Resists Head Hardware Photonics Task analysis

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Cataloging the visible universe through Bayesian inference in Julia at petascale

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JOURNAL OF PARALLEL AND DISTRIBUTED computing 2019年 127卷 89-104页

作者： Regier, Jeffrey Fischer, Keno Pamnany, Kiran Noack, Andreas Revels, Jarrett Lam, Maximilian Howard, Steve Giordano, Ryan Schlegel, David McAuliffe, Jon thomas, Rollin Prabhat Univ Calif Berkeley Dept Elect Engn & Comp Sci Berkeley CA 94720 USA Julia Comp Boston MA USA Intel Corp Parallel Comp Lab Santa Clara CA USA MIT Comp Sci & AI Labs 77 Massachusetts Ave Cambridge MA 02139 USA Univ Calif Berkeley Dept Stat Berkeley CA 94720 USA Lawrence Berkeley Natl Lab Berkeley CA USA

A key task in astronomy is to locate astronomical objects in images and to characterize them according to physical parameters such as brightness, color, and morphology. this task, known as cataloging, is challenging for several reasons: many astronomical objects are much dimmer than the sky background, labeled data is generally unavailable, overlapping astronomical objects must be resolved collectively, and the datasets are enormous - terabytes now, petabytes soon. In this work, we infer an astronomical catalog from 55 TB of imaging data using Celeste, a Bayesian variational inference code written entirely in the high-productivity programming language Julia. Using over 1.3 million threads on 650,000 Intel Xeon Phi cores of the Cori Phase II supercomputer, Celeste achieves a peak rate of 1.54 DP PFLOP/s. Celeste is able to jointly optimize parameters for 188 M stars and galaxies, loading and processing 178 TB across 8192 nodes in 14.6 min. To achieve this, Celeste exploits parallelism at multiple levels (cluster, node, and thread) and accelerates I/O through Cori's burst buffer. Julia's native performance enables Celeste to employ high-level constructs without resorting to hand-written or generated low-level code (C/C++/Fortran) while still achieving petascale performance. (C) 2019 Elsevier Inc. All rights reserved.

关键词： Astronomy Bayesian Distributed optimization Variational inference Julia high-performance computing

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Module-per-object: A human-driven methodology for c++-based high-level synthesis design 27

Module-per-object: A human-driven methodology for c++-based ...

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27th Annual ieee international symposium on Field-Programmable Custom computing Machines, FCCM 2019

作者： Santiago Da Silva, Jeferson Boyer, Francois-Raymond Langlois, J.M. Pierre Polytechnique Montreal Canada

ISBN: (纸本)9781728111315

high-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware design. However, achieving the highest Quality-of-Results (QoR) with HLS is still unattainable for most programmers. this requires detailed knowledge of FPGA architecture and hardware design in order to produce FPGA-friendly codes. Moreover, these codes are normally in conflict with best coding practices, which favor code reuse, modularity, and conciseness. To overcome these limitations, we propose Module-per-Object (MpO), a human-driven HLS design methodology intended for both hardware designers and software developers with limited FPGA expertise. MpO exploits modern C++ to raise the abstraction level while improving QoR, code readability and modularity. To guide HLS designers, we present the five characteristics of MpO classes. Each characteristic exploits the power of HLS-supported modern C++ features to build C++-based hardware modules. these characteristics lead to high-quality software descriptions and efficient hardware generation. We also present a use case of MpO, where we use C++ as the intermediate language for FPGA-Targeted code generation from P4, a packet processing domain specific language. the MpO methodology is evaluated using three design experiments: A packet parser, a flow-based traffic manager, and a digital up-converter. Based on experiments, we show that MpO can be comparable to handwritten VHDL code while keeping a high abstraction level, humanreadable coding style and modularity. Compared to traditional C-based HLS design, MpO leads to more efficient circuit generation, both in terms of performance and resource utilization. Also, the MpO approach notably improves software quality, augmenting parameterization while eliminating the incidence of code duplication. © 2019 ieee.

关键词： Field programmable gate arrays (FPGA)

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On the testing of special memories in GPGPUs

On the testing of special memories in GPGPUs

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ieee symposium on On-Line Testing (IOLTS)

作者： Josie E. Rodriguez Condia Matteo Sonza Reorda Dept. of Control and Computer Engineering Politecnico di Torino Torino Italy

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181882

Nowadays, data-intensive processing applications, such as multimedia, high-performance computing and safety-critical ones (e.g., in automotive) employ General Purpose Graphics Processing Units (GPGPUs) due to their parallel processing capabilities and high performance. In these devices, multiple levels of memories are employed in GPGPUs to hide latency and increase the performance during the operation of a kernel. Moreover, modern GPGPU architectures implement cutting-edge semiconductor technologies, reducing their size and power consumption. However, some studies proved that these technologies are prone to faults during the operative life of a device, so compromising reliability. In this work, we developed functional test techniques based on parallel Software-Based Self-Test routines to test memory structures in the memory hierarchy of a GPGPU (FlexGripPlus) implementing the G80 architecture of Nvidia.

关键词： Instruction sets Registers Radio frequency Kernel performance evaluation computer architecture Power demand

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