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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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PLEXUS: A Pattern-Oriented Runtime System architecture for Resilient Extreme-Scale high-performance computing Systems

PLEXUS: A Pattern-Oriented Runtime System Architecture for R...

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Pacific Rim international symposium on Dependable computing

作者： Saurabh Hukerikar Christian Engelmann Oak Ridge National Laboratory Oak Ridge TN USA

ISBN: (数字)9781728180038

ISBN: (纸本)9781728180045

For high-performance computing (HPC) system designers and users, meeting the myriad challenges of next-generation exascale supercomputing systems requires rethinking their approach to application and system software design. Among these challenges, providing resiliency and stability to the scientific applications in the presence of high fault rates requires new approaches to software architecture and design. As HPC systems become increasingly complex, they require intricate solutions for detection and mitigation for various modes of faults and errors that occur in these large-scale systems, as well as solutions for failure recovery. these resiliency solutions often interact with and affect other system properties, including application scalability, power and energy efficiency. therefore, resilience solutions for HPC systems must be thoughtfully engineered and deployed. In previous work, we developed the concept of resilience design patterns, which consist of templated solutions based on well-established techniques for detection, mitigation and recovery. In this paper, we use these patterns as the foundation to propose new approaches to designing runtime systems for HPC systems. the instantiation of these patterns within a runtime system enables flexible and adaptable end-to-end resiliency solutions for HPC environments. the paper describes the architecture of the runtime system, named Plexus, and the strategies for dynamically composing and adapting pattern instances under runtime control. this runtime-based approach enables actively balancing the cost-benefit trade-off between performance overhead and protection coverage of the resilience solutions. Based on a prototype implementation of PLEXUS, we demonstrate the resiliency and performance gains achieved by the pattern-based runtime system for a parallel linear solver application.

关键词： Resilience Runtime Libraries computer architecture Systems architecture Government Scalability

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KPynq: A Work-Efficient Triangle-Inequality Based K-Means on FPGA

KPynq: A Work-Efficient Triangle-Inequality Based K-Means on...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Yuke Wang Zhaorui Zeng Boyuan Feng Lei Deng Yufei Ding Department of Computer Science University of California Santa Barbara Department of Electrical and Computer Engineering University of California Santa Barbara

K-means is a popular but computation-intensive algorithm for unsupervised learning. To address this issue, we present KPynq, a work-efficient triangle-inequality based K-means on FPGA for handling large-size, high-dimension datasets. KPynq leverages an algorithm-level optimization to balance the performance and computation irregularity, and a hardware architecture design to fully exploit the pipeline and parallel processing capability of various FPGAs. In the experiment, KPynq consistently outperforms the CPU-based standard K-means in terms of its speedup (up to 4.2×) and significant energy efficiency (up to 218×).

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Automatic Generation of Warp-Level Primitives and Atomic Instructions for Fast and Portable Parallel Reduction on GPUs 2019

Automatic Generation of Warp-Level Primitives and Atomic Ins...

引用

17th ieee/ACM international symposium on Code Generation and Optimization (CGO)

作者： De Gonzalo, Simon Garcia Huang, Sitao Gomez-Luna, Juan Hammond, Simon Mutlu, Onur Hwu, Wen-mei UIUC CS & Coordinated Sci Lab Champaign IL 61820 USA UIUC ECE & Coordinated Sci Lab Champaign IL USA Swiss Fed Inst Technol Comp Sci Zurich Switzerland Sandia Natl Labs Scalable Comp Architecture Livermore CA 94550 USA

ISBN: (纸本)9781728114361

Since the advent of GPU computing, GPU hardware has evolved at a fast pace. Since application performance heavily depends on the latest hardware improvements, performance portability is extremely challenging for GPU application library developers. Portability becomes even more difficult when new low-level instructions are added to the ISA (e.g., warp shuffle instructions) or the microarchitectural support for existing instructions is improved (e.g., atomic instructions). Library developers, besides re-tuning the code for new hardware features, deal with the performance portability issue by hand-writing multiple algorithm versions that leverage different instruction sets and microarchitectures. high-level programming frameworks and Domain Specific Languages (DSLs) do not typically support low-level instructions (e.g., warp shuffle and atomic instructions), so it is painful or even impossible for these programming systems to take advantage of the latest architectural improvements. In this work, we design a new set of high-level APIs and qualifiers, as well as specialized Abstract Syntax Tree (AST) transformations for high-level programming languages and DSLs. Our transformations enable warp shuffle instructions and atomic instructions (on global and shared memories) to be easily generated. We show a practical implementation of these transformations by building on Tangram, a high-level kernel synthesis framework. Using our new language and compiler extensions, we implement parallel reduction, a fundamental building block used in a wide range of algorithms. Parallel reduction is representative of the performance portability challenge, as its performance heavily depends on the latest hardware improvements. We compare our synthesized parallel reduction to another high-level programming framework and a hand-written high-performance library across three generations of GPU architectures, and show up to 7.8x speedup (2x on average) over hand-written code.

关键词： Graphics processing units Programming computer architecture Libraries Hardware DSL Microarchitecture

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Cross Architectural Power Modelling

Cross Architectural Power Modelling

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Kai Chen Peter Kilpatrick Dimitrios S. Nikolopoulos Blesson Varghese Queen’s University Belfast UK Virginia Tech USA

ISBN: (数字)9781728160955

ISBN: (纸本)9781728196497

Existing power modelling research focuses on the model rather than the process for developing models. An automated power modelling process that can be deployed on different processors for developing power models with high accuracy is developed. For this, (i) an automated hardware performance counter selection method that selects counters best correlated to power on both ARM and Intel processors, (ii) a noise filter based on clustering that can reduce the mean error in power models, and (iii) a two stage power model that surmounts challenges in using existing power models across multiple architectures are proposed and developed. the key results are: (i) the automated hardware performance counter selection method achieves comparable selection to the manual method reported in the literature, (ii) the noise filter reduces the mean error in power models by up to 55%, and (iii) the two stage power model can predict dynamic power with less than 8% error on both ARM and Intel processors, which is an improvement over classic models.

关键词： Hardware Program processors Computational modeling Power measurement computer architecture Mathematical model Benchmark testing

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Reduced-Precision DWC for Mixed-Precision GPUs

Reduced-Precision DWC for Mixed-Precision GPUs

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ieee symposium on On-Line Testing (IOLTS)

作者： Fernando Fernandes dos Santos Marcelo Brandalero Pedro Martins Basso Michael Hubner Luigi Carro Paolo Rech Institute of Informatics Universidade Federal do Rio Grande do Sul (UFRGS) Porto Alegre Brazil Chair of Computer Engineering Brandenburg University of Technology (B-TU). Cottbus Germany

ISBN: (数字)9781728181875

ISBN: (纸本)9781728181882

Duplication with Comparison (DWC) is an effective software-level solution to improve the reliability of computing systems, including Graphics Processing Units (GPUs). DWC, however, introduces performance and energy consumption overheads that could be unacceptable for high-performance computing (HPC) or real-time safety-critical applications. In this work, we propose Reduced-Precision DWC (RP-DWC): an improvement over the traditional DWC approach that uses mixed-precision GPUs hardware resources to implement fault detection. We investigate, through both fault injection campaigns and accelerated neutron beam experiments, the impact of RPDWC onto performance, energy consumption, and its fault detection capabilites. We show that RP-DWC achieves on average 74% fault coverage (up to 86%) with very small overheads (0.1% time and 24% energy consumption overhead, in the best case).

关键词： Hardware Energy consumption computer architecture Transient analysis Reliability Graphics processing units

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An OpenCL-Based Acceleration for Canny Algorithm Using a Heterogeneous CPU-FPGA Platform

An OpenCL-Based Acceleration for Canny Algorithm Using a Het...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Samah Rahamneh Lina Sawalha Electrical and Computer Engineering Western Michigan University

Field programmable gate arrays (FPGAs) provide both performance and power benefits to heterogeneous systems. In this work, we used a closely-coupled CPU-FPGA heterogeneous system to accelerate Canny edge detector algorithm and compared the performance of the hybrid implementation with that of the optimized separate CPU and FPGA implementations. Our results show up to 4.8X speedup for the hybrid implementation over the CPU only implementation and up to 2.1X over the FPGA only implementation.

关键词： Field programmable gate arrays Acceleration computer architecture Partitioning algorithms Image edge detection Logic gates Detectors

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SOL: Effortless Device Support for AI Frameworks without Source Code Changes

SOL: Effortless Device Support for AI Frameworks without Sou...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Nicolas Weber Felipe Huici NEC Laboratories Europe

ISBN: (数字)9781728160955

ISBN: (纸本)9781728196497

Modern high performance computing clusters heavily rely on accelerators to overcome the limited compute power of CPUs. these supercomputers run various applications from different domains such as simulations, numerical applications or artificial intelligence (AI). As a result, vendors need to be able to efficiently run a wide variety of workloads on their *** the AI domain this is in particular exacerbated by the existance of a number of popular frameworks (e.g, PyTorch, TensorFlow, etc.) that have no common code base, and can vary in functionality. the code of these frameworks evolves quickly, making it expensive to keep up with all changes and potentially forcing developers to go through constant rounds of *** this paper we explore how to provide hardware support in AI frameworks without changing the framework's source code in order to minimize maintenance overhead. We introduce SOL, an AI acceleration middleware that provides a hardware abstraction layer that allows us to transparently support heterogenous hardware. As a proof of concept, we implemented SOL for PyTorch with three backends: CPUs, GPUs and vector processors.

关键词： Artificial intelligence Hardware Libraries computer architecture Optimization Layout Middleware

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high Precision, high performance FPGA Adders

High Precision, High Performance FPGA Adders

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Martin Langhammer Bogdan Pasca Gregg Baeckler Intel Corporation

FPGAs are now being commonly used in the datacenter as smart Network Interface Cards (NICs), with cryptography as one of the strategic application areas. Public key cryptography algorithms in particular require arithmetic with thousands of bits of precision. Even an operation as simple as addition can be difficult for the FPGA when dealing with large integers, because of the high resource count and high latency needed to achieve usable performance levels with known methods. this paper examines the architecture and implementation of high-performance integer adders on FPGAs for widths ranging from 1024 to 8192 bits, in both single-instance and many-core chip-filling configurations. For chip-filling designs the routing impact of these wide busses are assessed, as they often have an impact outside the immediate locality of the structures. the architectures presented in this work show 1 to 2 orders magnitude reduction in the area-latency product over commonly used approaches. Routing congestion is managed, with near 100% logic efficiency (packing) for the adder function. performance for these largely automatically placed designs are approximately the same as for carefully floor-planned non-arithmetic applications. In one example design, we show a 2048 bit adder in 5021 ALMs, with a latency of 6 clock cycles, at 628 MHz in a Stratix 10 E-2 device.

关键词： Adders Field programmable gate arrays Routing Pipeline processing performance evaluation Pipelines computer architecture

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ScoRD: A Scoped Race Detector for GPUs

ScoRD: A Scoped Race Detector for GPUs

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Annual international symposium on computer architecture, ISCA

作者： Aditya K. Kamath Alvin A. George Arkaprava Basu Department of Computer Science and Automation Indian Institute of Science Bangalore India

ISBN: (数字)9781728146614

ISBN: (纸本)9781728146621

GPUs have emerged as a key computing platform for an ever-growing range of applications. Unlike traditional bulk-synchronous GPU programs, many emerging GPU-accelerated applications, such as graph processing, have irregular interaction among the concurrent threads. Consequently, they need complex synchronization. To enable both high performance and adequate synchronization, GPU vendors have introduced scoped synchronization operations that allow a programmer to synchronize within a subset of concurrent threads (a.k. a., scope) that she deems adequate. Scoped-synchronization avoids the performance overhead of synchronization across thousands of GPU threads while ensuring correctness when used appropriately. this flexibility, however, could be a new source of incorrect synchronization where a race can occur due to insufficient scope of the synchronization operation, and not due to missing synchronization as in a typical race. We introduce ScoRD, a race detector that enables hardware support for efficiently detecting global memory races in a GPU program, including those that arise due to insufficient scopes of synchronization operations. We show that ScoRD can detect a variety of races with a modest performance overhead (on average, 35%). In the process of this study, we also created a benchmark suite consisting of seven applications and three categories of microbenchmarks that use scoped synchronization operations.

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Energy efficiency and performance modeling of stencil applications on manycore and GPU computing resources

Energy efficiency and performance modeling of stencil applic...

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ieee/ACM international symposium on Cluster computing and the Grid (CCGRID)

作者： Krzysztof Kurowski Miłosz Ciżnicki Jan Węglarz Poznań Supercomputing and Networking Center affiliated to IBCH PAS Poznań Poland Poznań University of Technology Poznań Poland

ISBN: (数字)9781728160955

One of the most critical application areas for many operational high-performance computing systems worldwide is a numerical weather prediction. Such complex predictions and corresponding computing models have to solve a large number of Partial Differential Equations using stencil computations on structured grids within tight production schedules. A stencil kernel within simulations is often the most demanding computing part and naturally may impact the energy consumption of the whole HPC system. In this paper, we introduce new functional extensions developed for DCworms and GSSIM simulators to predict the energy efficiency of extreme-scale stencil applications on heterogeneous computing resources, in particular consisting of a large number of many-core and GPUs. New energy-efficiency metrics for modeling of heterogeneous computing resources have been successfully added to the simulators thanks to their pluggable and extensible architectures. Our recent improvements related to application-specific performance models in simulators help users to take into account many relevant application parameters, in particular, those related to detailed energy consumption on heterogeneous HPC resources. We show in this paper how to extract stencil application-specific parameters based on real experiments. Moreover, we demonstrate how those parameters can be applied for modeling and simulation experiments to evaluate the overall performance and energy consumption of stencil computations on manycore CPUs and GPUs. Finally, we discuss new DCworms simulator capabilities and demonstrate added-values of performance analysis tools.

关键词： Computational modeling computer architecture Hardware Graphics processing units Energy consumption Predictive models

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