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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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A high throughput and Energy-Efficient Retina-Inspired Tone Mapping Processor

A High Throughput and Energy-Efficient Retina-Inspired Tone ...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Lili Liu Xiaoqiang Xiang Yuxiang Xie Yongjie Li Bo Yan Jun Zhou University of Electronic Science and Technology of China Chengdu China

this paper presents a high throughput and energy-efficient retina inspired tone mapping processor. Several hardware design techniques have been proposed to achieve high throughput and high energy efficiency, including data partition based parallel processing with S-shape sliding, adjacent frame feature sharing, multi-layer convolution pipelining and convolution filter compression with zero skipping convolution. the proposed processor has been implemented on a Xilinx's Virtex7 FPGA for demonstration. It is able to achieve a throughput of 189 frames per second for 1024*768 RGB images with 819 mW. Compared with several state-of-the-art tone mapping processors, the proposed processor achieves higher throughput and energy efficiency. It is suitable for high-speed and energy-constrained video enhancement applications such as autonomous vehicle and drone monitoring.

关键词： throughput Energy efficiency Hardware Convolution computer architecture Retina Software

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Deep Packet Inspection in FPGAs via Approximate Nondeterministic Automata

Deep Packet Inspection in FPGAs via Approximate Nondetermini...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Milan Ceška Vojtech Havlena Lukáš Holík Jan Korenek Ondrej Lengál Denis Matoušek Jirí Matoušek Jakub Semric Tomáš Vojnar Brno University of Technology IT4I Centre of Excellence Czech Republic

Deep packet inspection via regular expression (RE) matching is a crucial task of network intrusion detection systems (IDSes), which secure Internet connection against attacks and suspicious network traffic. Monitoring high-speed computer networks (100 Gbps and faster) in a single-box solution demands that the RE matching, traditionally based on finite automata (FAs), is accelerated in hardware. In this paper, we describe a novel FPGA architecture for RE matching that is able to process network traffic beyond 100 Gbps. the key idea is to reduce the required FPGA resources by leveraging approximate nondeterministic FAs (NFAs). the NFAs are compiled into a multi-stage architecture starting with the least precise stage with a high throughput and ending with the most precise stage with a low throughput. To obtain the reduced NFAs, we propose new approximate reduction techniques that take into account the profile of the network traffic. Our experiments showed that using our approach, we were able to perform matching of large sets of REs from SNORT, a popular IDS, on unprecedented network speeds.

关键词： Field programmable gate arrays computer architecture throughput Automata architecture Acceleration Hardware

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An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1 Decoder

An UHD 4K@60fps Deblocking Filter Hardware Targeting the AV1...

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ieee international Conference on Electronics, Circuits and Systems (ICECS)

作者： Eduardo Zummach Roberta Palau Jones Goebel Felipe Sampaio Guilherme Correa Luciano Agostini Marcelo Porto Video Technology Research Group (ViTech) Federal University of Pelotas (UFPel) - Pelotas Brazil Graduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) - Pelotas Brazil Federal Institute of Rio Grande do Sul (IFRS) - Farroupilha Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

this paper presents a hardware design for the Deblocking Filter (DBF) in the AOM Video 1 (AV1) decoder. the DBF is the first filter of the AV1 encoding loop, being used to attenuate blocking artifacts and to improve the subjective video quality. the presented hardware design is capable to process up to 56 samples per clock cycle, aiming at processing Ultra-high Definition (UHD) videos with 4098×2160 pixels (4K) at 60 frames per second when running at 16.2 MHz. the architecture was synthesized to ASIC using the 40nm TSMC library, requiring 39.35K gates and with a power dissipation of 3.96 mW. At the best of the authors' knowledge, this is the first hardware design targeting the AV1 DBF presented in the literature.

关键词： Finite impulse response filters Hardware computer architecture Streaming media Decoding Filter banks Encoding

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Towards Lightweight Serverless computing via Unikernel as a Function

Towards Lightweight Serverless Computing via Unikernel as a ...

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international Workshop on Quality of Service

作者： Bo Tan Haikun Liu Jia Rao Xiaofei Liao Hai Jin Yu Zhang National Engineering Research Center for Big Data Technology and System Services Computing Technology and System Lab/Cluster and Grid Computing Lab School of Computer Science and Technology Huazhong University of Science and Technology Wuhan China The University of Texas at Arlington

ISBN: (数字)9781728168876

ISBN: (纸本)9781728168883

Serverless computing, also known as “Function as a Service (FaaS)”, is emerging as an event-driven paradigm of cloud computing. In the FaaS model, applications are programmed in the form of functions that are executed and managed separately. Functions are triggered by cloud users and are provisioned dynamically through containers or virtual machines (VMs). the startup delays of containers or VMs usually lead to rather high latency of response to cloud users. Moreover, the communication between different functions generally relies on virtual net devices or shared memory, and may cause extremely high performance overhead. In this paper, we propose Unikernel-as-a-Function (UaaF), a much more lightweight approach to serverless computing. Applications are abstracted as a combination of different functions, and each function are built as an unikernel in which the function is linked with a specified minimum-sized library operating system (LibOS). UaaF offers extremely low startup latency to execute functions, and an efficient communication model to speed up inter-functions interactions. We exploit an new hardware technique (namely VMFUNC) to invoke functions in other unikernels seamlessly (mostly like inter-process communications), without suffering performance penalty of VM Exits. We implement our proof-of-concept prototype based on KVM and deploy UaaF in three unikernels (MirageOS, IncludeOS, and Solo5). Experimental results show that U aaF can significantly reduce the startup latency and memory usage of serverless cloud applications. Moreover, the VMFUNC-based communication model can also significantly improve the performance of function invocations between different unikernels.

关键词： Cloud computing FAA Libraries Containers Task analysis computer architecture Virtual machine monitors

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Initial Experiments with Duet Benchmarking: performance Testing Interference in the Cloud

Initial Experiments with Duet Benchmarking: Performance Test...

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international symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Lubomír Bulej Vojtěch Horký Petr Tůma Charles University Prague Czech Republic

Accurate performance testing may require many measurements and therefore many machines to execute on. When many machines are needed, the cloud offers a tempting solution, however, measurements conducted in the cloud are generally considered unstable. In the context of comparing performance of two workloads, we propose a measurement procedure that improves accuracy by executing the workloads concurrently and using the measurements to filter outside interference. Depending on the platform used, experiments show average accuracy improvement ranging from 114% to 683% over sequential measurements on workloads running the ScalaBench suite with the Graal compiler.

关键词： Interference Cloud computing Virtual machining Task analysis Benchmark testing Time measurement

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Global and semi-global communication on si-if special session paper 13

Global and semi-global communication on si-if special sessio...

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13th ieee/ACM international symposium on Networks-on-Chip, NOCS 2019

作者： Vaisband, Boris Iyer, Subramanian S. Department of Elecetrical and Computer Engineering University of California Los Angeles Los AngelesCA United States

ISBN: (纸本)9781450367004

On-chip scaling continues to pose significant technological and design challenges. Nonetheless, the key obstacle in on-chip scaling is the high fabrication cost of the state-of-the-Art technology nodes. An opportunity exists however, to continue scaling at the system level. Silicon interconnect fabric (Si-IF) is a platform that aims to replace both the package and printed circuit board to enable heterogeneous integration and high inter-chip performance. Bare dies are attached directly to the Si-IF at fine vertical interconnect pitch (2 to 10 um) and small inter-die spacing (100 um). the Si-IF is a singlehierarchy integration construct that supports dies of any process, technology, and dimensions. In addition to development of the fabrication and integration processes, system-level challenges need to be addressed to enable integration of heterogeneous systems on the Si-IF. Communication is a fundamental challenge on large Si-IF platforms (up to 300 mm diameter wafers). Different technological and design approaches for global and semi-global communication are discussed in this paper. the area overhead associated with global communication on the Si-IF is determined. © 2019 Association for computing Machinery.

关键词： Silicon wafers

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Improving the performance of Fog computing through the use of Data Locality 30

Improving the Performance of Fog Computing through the use o...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Steffenel, Luiz Angelo Univ Reims CReSTIC Lab CASH Team Reims France

ISBN: (纸本)9781538677698

Fog computing extends the Cloud computing paradigm to the edge of the network, developing a decentralized infrastructure in which services are distributed to locations that best meet the needs of the applications such as low communication latency, data caching or confidentiality. P2P-based platforms are good candidates to host Fog computing, but they usually lack important elements such as controlling where the data is stored and who will handle the computing tasks. As a consequence, controlling where the data is stored becomes as important as controlling who handle it. In this paper we propose different techniques to reinforce data-locality for P2P-based middlewares, and study how these techniques can be implemented. Experimental results demonstrate the interest of data locality on the data access performances.

关键词： fog computing P2P overlay data locality scheduling distributed hash table

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A Scalable OpenCL-Based FPGA Accelerator for YOLOv2

A Scalable OpenCL-Based FPGA Accelerator for YOLOv2

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Ke Xu Xiaoyun Wang Dong Wang Institute of Information Science Beijing Jiaotong University Beijing China Beijing Key Laboratory of Advanced Information Science and Network Technology Beijing China

this paper implements an OpenCL-based FPGA accelerator for YOLOv2 on Arria-10 GX1150 FPGA board. the hardware architecture adopts a scalable pipeline design to support multi-resolution input image, and improves resource utilization by full 8-bit fixed-point computation and CONV+BN+Leaky-ReLU layer fusion technology. the proposed design achieves a peak throughput of 566 GOPs under 190 MHz working frequency. the accelerator could run YOLOv2 inference with 288×288 input resolution and tiny YOLOv2 with 416×416 input resolution at the speed of 35 and 71 FPS, respectively.

关键词： Field programmable gate arrays Kernel Convolution Hardware computer architecture Object detection Pipelines

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A Kernel Unfolding Approach to Trade Data Movement with Computation Power for CNN Acceleration

A Kernel Unfolding Approach to Trade Data Movement with Comp...

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ieee Non-Volatile Memory Systems and Applications symposium (NVMSA)

作者： Yueh-Han Wu Tse-Yuan Wang Yuan-Hao Chang Tei-Wei Kuo Hung-Sheng Chang National Taiwan University Institute of Information Science Academia Sinica Hong Kong Institute for Advanced Study City University of Hong Kong Hong Kong Macronix Emerging System Lab Macronix International Co. Ltd.

ISBN: (数字)9781728184821

ISBN: (纸本)9781728184838

Convolutional neural networks (CNN) achieves human-level accuracy on the image classification applications. However, its complicated structure brings the large requirement on the MAC operations and result in huge cost on the data movement. In addition, this situation becomes worse when the asymmetric growth of the computing power and memory speed happens on the von Neumann-based architecture. Recently, processing in memory (PIM) design is adopted to reduce the data communication cost by storing parameters into memory. However, significant cost on feeding input feature map is a big challenge, especially for high bandwidth but long access latency PIM devices. thus, we explore an idea that how to trade the space in PIM to eliminate such cost. A kernel unfolding technique is proposed to eliminate the duplicated feeding on input feature map, and meanwhile, memory cells in PIM are highly utilized to achieve peak computing throughput. thus, the memory bandwidth could be utilized efficiently and the corresponding execution time could be reduced significantly. the results show that the proposed design could achieve up to 16.2× cycle improvement compared to traditional PIM designs.

关键词： Kernel computer architecture Sensors Convolution Bandwidth Feature extraction performance evaluation

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ASNet: Introducing Approximate Hardware to high-Level Synthesis of Neural Networks

ASNet: Introducing Approximate Hardware to High-Level Synthe...

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international symposium on Multiple-Valued Logic

作者： Saman Froehlich Lucas Klemmer Daniel Große Rolf Drechsler DFKI GmbH and Group of Computer Architecture University of Bremen Germany

ISBN: (数字)9781728154060

ISBN: (纸本)9781728154077

Approximate computing is a design paradigm which makes use of error tolerance inherent to many applications in order to trade off accuracy for performance. One classic example for such an application is machine learning with Neural Networks (NNs). Recently, LeFlow, a high-Level Synthesis (HLS) flow for mapping Tensorflow NNs into hardware has been proposed. the main steps of LeFlow are to compile the Tensorflow models into the LLVM Intermediate Representation (IR), perform several transformations and feed the result into a HLS tool. In this work we take HLS-based NN synthesis one step further by integrating hardware approximation. To achieve this goal, we upgrade LeFlow such that (a) the user can specify hardware approximations, and (b) the user can analyze the impact of hardware approximation already at the SW level. Based on the exploration results which satisfy the NN quality expectations, we import the chosen approx. HW components into an extended version of the HLS tool to finally synthesize the NN to Verilog. the experimental evaluation demonstrates the advantages of our proposed ASNet for several NNs. Significant area reductions as well as improvements in operation frequency are achieved.

关键词： Artificial neural networks Tools Hardware design languages Generators Libraries Hardware Complexity theory

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