检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

1,861 篇 会议
9 篇 期刊文献

馆藏范围

1,870 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,162 篇 工学
- 1,098 篇 计算机科学与技术...
- 479 篇 软件工程
- 285 篇 电气工程
- 138 篇 信息与通信工程
- 126 篇 电子科学与技术（可...
- 52 篇 控制科学与工程
- 33 篇 动力工程及工程热...
- 21 篇 机械工程
- 17 篇 生物医学工程（可授...
- 16 篇 仪器科学与技术
- 15 篇 生物工程
- 14 篇 网络空间安全
- 12 篇 环境科学与工程（可...
- 10 篇 光学工程
- 8 篇 力学（可授工学、理...
- 8 篇 建筑学
- 7 篇 化学工程与技术
218 篇 理学
- 161 篇 数学
- 33 篇 物理学
- 32 篇 系统科学
- 18 篇 生物学
- 17 篇 统计学（可授理学、...
- 9 篇 化学
- 9 篇 地球物理学
196 篇 管理学
- 156 篇 管理科学与工程(可...
- 79 篇 工商管理
- 44 篇 图书情报与档案管...
14 篇 经济学
- 14 篇 应用经济学
10 篇 法学
- 9 篇 社会学
10 篇 医学
- 8 篇 基础医学(可授医学...
6 篇 农学
5 篇 教育学

主题

547 篇 computer archite...
187 篇 hardware
122 篇 high performance...
109 篇 field programmab...
108 篇 computational mo...
83 篇 grid computing
80 篇 cloud computing
73 篇 concurrent compu...
73 篇 application soft...
73 篇 distributed comp...
72 篇 computer science
71 篇 parallel process...
71 篇 resource managem...
71 篇 graphics process...
70 篇 kernel
63 篇 throughput
59 篇 bandwidth
59 篇 benchmark testin...
58 篇 optimization
56 篇 runtime

机构

8 篇 school of comput...
8 篇 intel corp santa...
7 篇 univ chicago dep...
7 篇 mathematics and ...
6 篇 georgia inst tec...
6 篇 university of ch...
6 篇 mathematics and ...
6 篇 college of compu...
5 篇 univ wisconsin m...
5 篇 barcelona superc...
5 篇 univ calif santa...
5 篇 northeastern uni...
5 篇 carnegie mellon ...
5 篇 intel corporatio...
5 篇 univ fed rio gra...
4 篇 univ politecn ca...
4 篇 univ toronto on
4 篇 univ illinois ur...
4 篇 georgia institut...
4 篇 oak ridge nation...

作者

11 篇 navaux philippe ...
8 篇 prasanna viktor ...
8 篇 mutlu onur
7 篇 borin edson
7 篇 chong frederic t...
7 篇 guedes dorgival
6 篇 dongarra jack
6 篇 patt yale n.
6 篇 xie yuan
6 篇 torrellas josep
6 篇 schwan karsten
6 篇 ferreira renato
6 篇 i. foster
5 篇 franca felipe m....
5 篇 hwu wen-mei
5 篇 nam sung kim
5 篇 martonosi margar...
5 篇 loh gabriel h.
5 篇 kim nam sung
5 篇 zhou huiyang

语言

1,856 篇 英文
11 篇 中文
2 篇 其他
1 篇 葡萄牙文

检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

共 1870 条记录，以下是411-420 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Assessing Time Predictability Features of ARM *** Multicores 30

Assessing Time Predictability Features of ARM *** Multicores

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Fernandez, Gabriel Cazorla, Francisco J. Abella, Jaume Girbal, Sylvain BSC Barcelona Spain CSIC IAAA Madrid Spain UPC Barcelona Spain THALES Res & Technol TRT Palaiseau France

ISBN: (纸本)9781538677698

the increasing performance needs in critical real-time embedded systems (CRTES), such as for instance the automotive domain, push for the adoption of high-performance hardware from the consumer electronics domain. However, their time-predictability features are quite unexplored. the ARM *** architecture is a good candidate for adoption in the CRTES market (i.e. in the automotive market it has already started being used). In this paper we study ARM ***'s capabilities to meet CRTES requirements. In particular, we perform a qualitative and quantitative assessment of its timing characteristics, focusing on shared multicore resources, and how this architecture can be reliably used in CRTES.

关键词： Program processors computer architecture Timing Real-time systems Monitoring Task analysis Benchmark testing

来源：评论

学校读者我要写书评

暂无评论

echofs: A Scheduler-guided Temporary Filesystem to leverage Node-local NVMs 30

echofs: A Scheduler-guided Temporary Filesystem to leverage ...

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Miranda, Alberto Nou, Ramon Cortes, Toni BSC Barcelona Spain Univ Politecn Cataluna BSC Barcelona Spain

ISBN: (纸本)9781538677698

the growth in data-intensive scientific applications poses strong demands on the HPC storage subsystem, as data needs to be copied from compute nodes to I/O nodes and vice versa for jobs to run. the emerging trend of adding denser, NVM-based burst buffers to compute nodes, however, offers the possibility of using these resources to build temporary filesystems with specific I/O optimizations for a batch job. In this work, we present echofs, a temporary filesystem that coordinates with the job scheduler to preload a job's input files into node-local burst buffers. We present the results measured with NVM emulation, and different FS backends with DAX/FUSE on a local node, to show the benefits of our proposal and such coordination.

关键词： Buffer storage Metadata Fuses Nonvolatile memory Hardware computer architecture Random access memory

来源：评论

学校读者我要写书评

暂无评论

Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs

Yosys+nextpnr: An Open Source Framework from Verilog to Bits...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： David Shah Eddie Hung Clifford Wolf Serge Bazanski Dan Gisselquist Miodrag Milanovic Symbiotic EDA Vienna Austria Dept. of Electrical and Computer Engineering University of British Columbia Canada

this paper introduces a fully free and open source software (FOSS) architecture-neutral FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement, routing, and bitstream generation. Currently, this flow supports two commercially available FPGA families, Lattice iCE40 (up to 8K logic elements) and Lattice ECP5 (up to 85K elements) and has been hardware-proven for custom-computing machines including a low-power neural-network accelerator and an OpenRISC system-on-chip capable of booting Linux. Both Yosys and nextpnr have been engineered in a highly flexible manner to support many of the features present in modern FPGAs by separating architecture-specific details from the common mapping *** framework is demonstrated on a longest-path case study to find an atypical single source-sink path occupying up to 45% of all on-chip wiring.

关键词： Field programmable gate arrays Routing Table lookup Hardware design languages Video recording Tools Wires

来源：评论

学校读者我要写书评

暂无评论

Active Stereo Vision with high Resolution on an FPGA

Active Stereo Vision with High Resolution on an FPGA

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Marc Pfeifer Philipp M. Scholl Rainer Voigt Bernd Becker Chair of Computer Architecture University of Freiburg Germany Ensenso GmbH Freiburg Germany

We present a novel FPGA based active stereo vision system, tailored for the use in a mobile 3D stereo camera. For the generation of a single 3D map the matching algorithm is based on a correlation approach, where multiple stereo image pairs instead of a single one are processed to guarantee an improved depth resolution. To efficiently handle the large amounts of incoming image data we adapt the algorithm to the underlying FPGA structures, e.g. by making use of pipelining and *** demonstrate that our approach provides high-quality 3D maps at least three times more energy-efficient (5.5 fps/W) than comparable approaches executed on CPU and GPU platforms. Implemented on a Xilinx Zynq-7030 SoC our system provides a computation speed of 12.2 fps, at a resolution of 1.3 megapixel and a 128 pixel disparity search space. As such it outperforms the currently best passive stereo systems of the Middlebury Stereo Evaluation in terms of speed and accuracy. the presented approach is therefore well suited for mobile applications, that require a highly accurate and energy-efficient active stereo vision system.

关键词： Stereo vision Field programmable gate arrays Correlation Cameras Speckle three-dimensional displays Hardware

来源：评论

学校读者我要写书评

暂无评论

Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU

Hardware Acceleration of Long Read Pairwise Overlapping in G...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Licheng Guo Jason Lau Zhenyuan Ruan Peng Wei Jason Cong Computer Science Department University of California Los Angeles

In genome sequencing, it is a crucial but time-consuming task to detect potential overlaps between any pair of the input reads, especially those that are ultra-long. the state-of-the-art overlapping tool Minimap2 outperforms other popular tools in speed and accuracy. It has a single computing hot-spot, chaining, that takes 70% of the time and needs to be accelerated. there are several crucial issues for hardware acceleration because of the nature of chaining. First, the original computation pattern is poorly parallelizable and a direct implementation will result in low utilization of parallel processing units. We propose a method to reorder the operation sequence that transforms the algorithm into a hardware-friendly form. Second, the large but variable sizes of input data make it hard to leverage task-level parallelism. therefore, we customize a fine-grained task dispatching scheme which could keep parallel PEs busy while satisfying the on-chip memory restriction. Based on these optimizations, we map the algorithm to a fully pipelined streaming architecture on FPGA using HLS, which achieves significant performance improvement. the principles of our acceleration design apply to both FPGA and GPU. Compared to the multi-threading CPU baseline, our GPU accelerator achieves 7x acceleration, while our FPGA accelerator achieves 28x acceleration. We further conduct an architecture study to quantitatively analyze the architectural reason for the performance difference. the summarized insights could serve as a guide on choosing the proper hardware acceleration platform.

关键词： Field programmable gate arrays Graphics processing units Task analysis Acceleration Tools Heuristic algorithms Genomics

来源：评论

学校读者我要写书评

暂无评论

PIR-DSP: An FPGA DSP Block architecture for Multi-precision Deep Neural Networks

PIR-DSP: An FPGA DSP Block Architecture for Multi-precision ...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： SeyedRamin Rasoulinezhad Hao Zhou Lingli Wang Philip H.W. Leong School of Electrical and Information Engineering The University of Sydney Australia State Key Lab of ASIC and System Fudan University Shanghai China

Quantisation is a key optimisation strategy to improve the performance of floating-point deep neural network (DNN) accelerators. Digital signal processing (DSP) blocks on field-programmable gate arrays are not efficiently utilised when the accelerator precision is much lower than the DSP precision. through three modifications to Xilinx DSP48E2 DSP blocks, we address this issue for important computations in embedded DNN accelerators, namely the standard, depth-wise, and pointwise convolutional layers. First, we propose a flexible precision, run-time decomposable multiplier architecture for CNN implementations. Second, we propose a significant upgrade to DSPDSP interconnect, providing a semi-2D low precision chaining capability which supports our low-precision multiplier. Finally, we improve data reuse via a register file which can also be configured as FIFO. Compared with the 27 × 18-bit mode in the Xilinx DSP48E2, our Precision, Interconnect, and Reuseoptimised DSP (PIR-DSP) offers a 6× improvement in multiplyaccumulate operations per DSP in the 9 × 9-bit case, 12× for 4 × 4 bits, and 24× for 2 × 2 bits. We estimate that PIR-DSP decreases the run time energy to 31/19/13% of the original value in a 9/4/2-bit MobileNet-v2 DNN implementation.

关键词： computer architecture Field programmable gate arrays Standards Convolution Integrated circuit interconnections Digital signal processing Neural networks

来源：评论

学校读者我要写书评

暂无评论

SimAcc: A Configurable Cycle-Accurate Simulator for Customized Accelerators on CPU-FPGAs SoCs

SimAcc: A Configurable Cycle-Accurate Simulator for Customiz...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Konstantinos Iordanou Oscar Palomar John Mawer Cosmin Gorgovan Andy Nisbet Mikel Luján School of Computer Science The University of Manchester UK

this paper describes a flexible infrastructure for fast computer architecture simulation and prototyping of accelerator IP. A trend for System-on-Chips is to include application specific accelerators on the die. However, there is still a key research problem that needs to be addressed: How do hardware accelerators interact with the processors of a system and what is the impact on overall performance? To solve this problem, we propose an infrastructure that can directly simulate unmodified application executables with FPGA hardware accelerators. Unmodified application binaries are dynamically instrumented to generate processor load/store and program counter events and any memory accesses generated by accelerators, that are sent to an FPGA-based out-of-order pipeline model. the key features of our infrastructure are the ability to code exclusively at the user level, to dynamically discover and use available hardware models at run time, to test and simultaneously optimize hardware accelerators in an heterogeneous system. In terms of evaluation, we present a comparison between our system and Gem5 to demonstrate accuracy and relative performance, using the SPEC CPU benchmarks; even though our system is implemented on Zynq XC7045 which integrates dual 667MHz Arm Cortex-A9s with substantial FPGA resources, it outperforms Gem5 running on a Xeon E3 3.2 GHz with 32GBs of RAM. We also evaluate our infrastructure in simulating the interaction of accelerators with processors using accelerators taken from the Mach Benchmark Suite and other custom accelerators from computer vision applications.

关键词： Hardware Field programmable gate arrays Timing Program processors Pipelines Load modeling Computational modeling

来源：评论

学校读者我要写书评

暂无评论

A Fault-Tolerant Agent-based architecture for Transient Servers in Fog computing 30

A Fault-Tolerant Agent-based Architecture for Transient Serv...

引用

30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： de Araujo Neto, Jose Pergentino Pianto, Donald M. Ralha, Celia G. Univ Brasilia UnB Dept Comp Sci CIC Brasilia DF Brazil Univ Brasilia UnB Dept Stat EST Brasilia DF Brazil

ISBN: (纸本)9781538677698

Cloud datacenters are exploring their idle resources and offering virtual machine as transient servers without availability guarantees. Spot instances are transient servers offered by Amazon AWS, with rules that define prices according to supply and demand. these instances will run for as long as the current price is lower than the maximum bid price given by users. Spot instances have been increasingly used for executing computation and memory intensive applications. By using dynamic fault tolerant mechanisms and appropriate strategies, users can effectively use spot instances to run applications at a cheaper price. this paper presents a resilient multi-strategy agent-based cloud computing architecture. the architecture combines machine learning and a statistical model to predict instance survival times, refine fault tolerance parameters and reduce total execution time. We evaluate our strategies and the experiments demonstrate high levels of accuracy, reaching a 94% survival prediction success rate, which indicates that the model can be effectively used to define execution strategies to prevent failures at revocation events under realistic working conditions.

关键词： Agent-based architecture Resilient Cloud computing Spot Instance Fault Tolerance Checkpoint

来源：评论

学校读者我要写书评

暂无评论

Exploiting Irregular Memory Parallelism in Quasi-Stencils through Nonlinear Transformation

Exploiting Irregular Memory Parallelism in Quasi-Stencils th...

引用

Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Juan Escobedo Mingjie Lin School of Electrical and Computer Engineering University of Central Florida Orlando Florida

Non-stencil kernels with irregular memory accesses pose unique challenges to achieving high computing performance and hardware efficiency in high-level synthesis (HLS) of FPGA. We present a highly versatile and systematic approach to effectively synthesizing a special and important subset of non-stencil computing kernels, quasi-stencils, which possess the mathematical property that, if studied in a particular kind of high-dimensional space corresponding to the prime factorization space, the distance between the memory accesses during each kernel iteration becomes constant and such an irregular non-stencil can be considered as a stencil. this opens the door to exploiting a vast array of existing memory optimization algorithms, such as memory partitioning/banking and data reuse, originally designed for the standard stencil-based kernel computing, therefore offering totally new opportunity to effectively synthesizing irregular non-stencil kernels. We show the feasibility of our approach implementing our methodology in a KC705 Xilinx FPGA board and tested it with several custom code segments that meet the quasi-stencil requirement vs some of the state-of the art methods in memory partitioning. We achieve significant reduction in partition factor, and perhaps more importantly making it proportional to the number of memory accesses instead of depending on the problem size with the cost of some wasted space.

关键词： Kernel Hardware Memory management Geometry Layout Parallel processing Field programmable gate arrays

来源：评论

学校读者我要写书评

暂无评论

performance and Energy Efficiency Trade-Offs in Single-ISA Heterogeneous Multi-Processing for Parallel Applications

Performance and Energy Efficiency Trade-Offs in Single-ISA H...

引用

IFIP international Conference on Very Large Scale Integration (VLSI-SoC)

作者： Demetrios A. M. Coutinho Kyriakos Georgiou Kerstin I. Eder Jose Nunez-Yanez Samuel Xavier-de-Souza Instituto Federal do Rio Grande do Norte - IFRN Natal-RN Brazil University of Bristol Bristol United Kingdom

this work proposes a novel methodology to predict the optimal performance and energy efficiency trade-off configurations of parallel applications running on a two-cluster Heterogeneous Multi-Processing (HMP) system. we propose an analytic performance and power model that are generated offline using data measurements. these models are then used to estimate the whole configuration space to predict the application's performance and energy consumption. then, we use these off-line predictions to choose Pareto-optimal configurations, which is the most efficient among all configurations for the given architecture and multi-threaded application. We validated our methodology on an ODROID XU3 board on several PARSEC and Phoronix Test Suite applications.

关键词： Energy consumption computer architecture Linux Optimization Predictive models Semiconductor device measurement high performance computing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共187页 << < 38 39 40 41 42 43 44 45 46 47 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：