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FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh Refinement Applications

FP-AMR: A Reconfigurable Fabric Framework for Adaptive Mesh ...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Tianqi Wang Tong Geng Xi Jin Martin Herbordt Department of Physics University of Science and Technology of China Hefei China Department of Electrical and Computer Engineering Boston University Boston MA USA

Adaptive mesh refinement (AMR) is one of the most widely used methods in high performance computing accounting a large fraction of all supercomputing cycles. AMR operates by dynamically and adaptively applying computational resources non-uniformly to emphasize regions of the model as a function of their complexity. Because AMR generally uses dynamic and pointer-based data structures, acceleration is challenging, especially in hardware. As far as we are aware there has been no previous work published on accelerating AMR with FPGAs. In this paper, we introduce a reconfigurable fabric framework called FP-AMR. the work is in two parts. In the first FP-AMR offloads the bulk per-timestep computations to the FPGA; analogous systems have previously done this with GPUs. In the second part we show that the rest of the CPU-based tasks-including particle mesh mapping, mesh refinement, and coarsening-can also be mapped efficiently to the FPGA. We have evaluated FP-AMR using the widely used program AMReX and found that a single FPGA outperforms a Xeon E5-2660 CPU server (8 cores) by from 21x -23x depending on problem size and data distribution.

关键词： Field programmable gate arrays Data structures Adaptation models Acceleration Particle accelerators Clustering algorithms Computational modeling

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high-performance GPU Transactional Memory via Eager Conflict Detection 24

High-performance GPU Transactional Memory via Eager Conflict...

引用

24th ieee international symposium on high performance computer architecture (HPCA)

作者： Ren, Xiaowei Lis, Mieszko Univ British Columbia Vancouver BC Canada

ISBN: (纸本)9781538636596

GPUs transactional memory (TM) proposals to date have relied on lazy, value-based conflict detection, assuming that GPUs can amortize the latency by executing other warps. In practice, however, concurrency must be throttled to a few warps per core to avoid high abort rates, and TM performance has remained far below that of fine-grained locks. We trace this to the latency cost of validating transactions: two round trips across the crossbar required for most commits and aborts. With limited concurrency, the warp scheduler cannot amortize this, and leaves the core idle most of the time. In this paper, we show that value-based validation does not scale to high thread counts, and eager conflict detection becomes more efficient as the number of threads grows. We leverage this insight to propose GETM, a GPU TM with eager conflict detection. GETM relies on a novel distributed logical clock scheme to implement eager conflict detection without the need for cache coherence or signature broadcasts. GETM is up to 2.1 times faster than the state-of-the art prior work WarpTM (gmean 1.2 times), with 3.6 times lower silicon area overheads and 2.2 times lower power overheads.

关键词： Graphics processing units Proposals Concurrent computing Clocks Coherence Hardware Message systems

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Exploring Power Budget Scheduling Opportunities and Tradeoffs for AMR-based Applications 30

Exploring Power Budget Scheduling Opportunities and Tradeoff...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Qin, Yubo Rodero, Ivan Subedi, Pradeep Parashar, Manish Rigo, Sandro Rutgers State Univ Rutgers Discovery Informat Inst RDI2 Piscataway NJ 08854 USA Univ Estadual Campinas Campinas SP Brazil

ISBN: (纸本)9781538677698

Computational demand has brought major changes to Advanced Cyber-Infrastructure (ACI) architectures. It is now possible to run scientific simulations faster and obtain more accurate results. However, power and energy have become critical concerns. Also, the current roadmap toward the new generation of ACI includes power budget as one of the main constraints. Current research efforts have studied power and performance tradeoffs and how to balance these (e.g., using Dynamic Voltage and Frequency Scaling (DVFS) and power capping for meeting power constraints, which can impact performance). However, applications may not tolerate degradation in performance, and other tradeoffs need to be explored to meet power budgets (e.g., involving the application in making energy-performance-quality tradeoff decisions). this paper proposes using the properties of AMR-based algorithms (e.g., dynamically adjusting the resolution of a simulation in combination with power capping techniques) to schedule or re-distribute the power budget. It specifically explores the opportunities to realize such an approach using checkpointing as a proof-of-concept use case and provides a characterization of a representative set of applications that use Adaptive Mesh Refinement (AMR) methods, including a Low-Mach-Number Combustion (LMC) application. It also explores the potential of utilizing power capping to understand power-quality tradeoffs via simulation.

关键词： Power demand Task analysis Degradation Power system management Power measurement Two dimensional displays computer architecture

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An Efficient Hardware Accelerator for Sparse Convolutional Neural Networks on FPGAs

An Efficient Hardware Accelerator for Sparse Convolutional N...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Liqiang Lu Jiaming Xie Ruirui Huang Jiansong Zhang Wei Lin Yun Liang Center for Energy-efficient Computing and Applications Peking University Beijing China Alibaba Group

Deep convolutional neural networks (CNN) have achieved remarkable performance with the cost of huge computation. As the CNN model becomes more complex and deeper, compressing CNN to sparse by pruning the redundant connection in networks has emerged as an attractive approach to reduce the amount of computation and memory requirement. In recent years, FPGAs have been demonstrated to be an effective hardware platform to accelerate CNN inference. However, most existing FPGA architectures focus on dense CNN models. the architecture designed for dense CNN models are inefficient when executing sparse models as most of the arithmetic operations involve addition and multiplication with zero operands. On the other hand, recent sparse FPGA accelerators only focus on FC layers. In this work, we aim to develop an FPGA accelerator for sparse CNNs. To efficiently deal with the irregular connection in the sparse convolutional layer, we propose a weight-oriented dataflow that processes each weight individually. then we design an FPGA architecture which can handle input-weight connection and weight-output connection efficiently. For input-weight connection, we design a tile look-up table to eliminate the runtime indexing match of compressed weights. Moreover, we develop a weight layout to enable high on-chip memory access. To cooperate with the weight layout, a channel multiplexer is inserted to locate the address which can ensure no data access conflict. Experiments demonstrate that our accelerator can achieve 223.4-309.0 GOP/s for the modern CNNs on Xilinx ZCU102, which provides a 3.6x-12.9x speedup over previous dense CNN FPGA accelerators.

关键词： Field programmable gate arrays Kernel Convolution Computational modeling Table lookup Layout

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Tensile: Auto-tuning GEMM GPU Assembly for All Problem Sizes 32

Tensile: Auto-tuning GEMM GPU Assembly for All Problem Sizes

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Tanner, David E. Adv Micro Devices Inc Austin TX 78735 USA

ISBN: (纸本)9781538655559

Generic matrix matrix multiplication (GEMM) on graphics processors (GPU) has long been the target of both tuning to find a fastest kernel for a GPU and hand-written assembly to achieve highest possible efficiency. Tensile is an open source (https://***/ROCmSoftwarePlatform/Tensile) tool which builds on both of these, by auto generating assembly kernels, auto benchmarking the kernels against a range of problem sizes, then auto generating library C code which selects the optimal kernel for a given problem size. Not only can the kernels achieve near-peak efficiency for the best problem sizes, but the size-tuned kernels can achieve speedups of 2X to 350X compared to any single-tuned kernel optimized for a given GPU architecture.

关键词： Kernel Graphics processing units Tensile stress computer architecture throughput Instruction sets Bandwidth"

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Templatised Soft Floating-Point for high-Level Synthesis

Templatised Soft Floating-Point for High-Level Synthesis

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： David B. thomas Department of Electrical and Electronic Engineering Imperial College London

high-level Synthesis (HLS) tools have greatly increased the productivity of FPGA application development, making it possible to easily create highly-parallel application-accelerators. However, while FPGAs are known for the ability to customise the number representation of data-paths, most HLS work only uses custom-precision for fixed-point representations, and for floating-point relies on the 64-, 32-, and 16-bitformats provided by vendors. this paper presents a solution for parametrised floating-point in HLS via C++ templates, allowing for compile-time selection of exponent and fraction widths, including the use of mixed precisions for input arguments and result types. By using arbitrary width integers and compile-time logic the resulting operators describe the same data-path as an external floating-point IP generator, while still allowing the HLS tool to perform detailed optimisation and scheduling of the internal components. We show that the resulting custom-width HLS cores provide similar area and performance to platform-native vendor IP blocks, while adding full support for heterogeneous precision floating-point data-paths to HLS tools.

关键词： IP networks Tools Libraries C++ languages Field programmable gate arrays Standards Generators

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LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Des...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Ecenur Ustun Shaojie Xiang Jinny Gui Cunxi Yu Zhiru Zhang School of Electrical and Computer Engineering Cornell University Ithaca NY USA

A primary barrier to rapid hardware specialization with FPGAs stems from weak guarantees of existing CAD tools on achieving design closure. Current methodologies require extensive manual efforts to configure a large set of options across multiple stages of the toolflow, intended to achieve high quality-of-results. Due to the size and complexity of the design space spanned by these options, coupled with the time-consuming evaluation of each design point, exploration for reconfigurable computing has become remarkably challenging. To tackle this challenge, we present a learning-assisted autotuning framework called LAMDA, which accelerates FPGA design closure by utilizing design-specific features extracted from early stages of the design flow to guide the tuning process with significant runtime savings. LAMDA automatically configures logic synthesis, technology mapping, placement, and routing to achieve design closure efficiently. Compared with a state-of-the-art FPGA-targeted autotuning system, LAMDA realizes faster timing closure on various realistic benchmarks using Intel Quartus Pro.

关键词： Tools Timing Field programmable gate arrays Estimation Databases Tuning Runtime

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SmarCo: An Efficient Many-Core Processor for high-throughput Applications in Datacenters 24

SmarCo: An Efficient Many-Core Processor for High-Throughput...

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Fan, Dongrui Li, Wenming Ye, Xiaochun Wang, Da Zhang, Hao Tang, Zhimin Sun, Ninghui Chinese Acad Sci ICT SKL Comp Architecture Beijing Peoples R China Univ Chinese Acad Sci Sch Comp & Control Engn Beijing Peoples R China SmarCo Co Ltd Beijing Peoples R China

ISBN: (纸本)9781538636596

Fast-growing high-throughput applications, such as web services, are characterized by high-concurrency processing, hard real-time response, and high-bandwidth memory access. the newly-born applications bring severe challenges to processors in datacenters, both in concurrent processing performance and energy efficiency. To offer a satisfactory quality of services, it is of critical importance to meet these newly emerging demands of high-throughput applications in the future datacenters in a more efficient way. In this paper, we propose a novel architecture, called SmarCo, which allows high-throughput applications to be processed more efficiently in datacenters. Based on the dominant characteristics of high-throughput applications, we implement large-scale many-core architecture with in-pair threads to support high-concurrency processing;we also introduce a hierarchical ring topology and laxity-aware task scheduler to guarantee hard real-time response;furthermore, we propose high-throughput datapath to improve memory access efficiency. We verify the efficiency of SmarCo by using simulators, large-scale FPGA and prototype with TSMC 40-nm technology node. the experimental results show that, compared to Intel Xeon E7-8890V4, SmarCo achieves 10.11X performance improvement and 6.95X energy-efficiency improvement with higher throughput and a better guarantee of real-time response.

关键词： Instruction sets Task analysis Indexes Real-time systems Memory management throughput

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Module-per-Object: A Human-Driven Methodology for C++-Based high-Level Synthesis Design

Module-per-Object: A Human-Driven Methodology for C++-Based ...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Jeferson Santiago da Silva François-Raymond Boyer J.M. Pierre Langlois Polytechnique Montréal Canada

high-Level Synthesis (HLS) brings FPGAs to audiences previously unfamiliar to hardware design. However, achieving the highest Quality-of-Results (QoR) with HLS is still unattainable for most programmers. this requires detailed knowledge of FPGA architecture and hardware design in order to produce FPGA-friendly codes. Moreover, these codes are normally in conflict with best coding practices, which favor code reuse, modularity, and conciseness. To overcome these limitations, we propose Module-per-Object (MpO), a human-driven HLS design methodology intended for both hardware designers and software developers with limited FPGA expertise. MpO exploits modern C++ to raise the abstraction level while improving QoR, code readability and modularity. To guide HLS designers, we present the five characteristics of MpO classes. Each characteristic exploits the power of HLS-supported modern C++ features to build C++-based hardware modules. these characteristics lead to high-quality software descriptions and efficient hardware generation. We also present a use case of MpO, where we use C++ as the intermediate language for FPGA-targeted code generation from P4, a packet processing domain specific language. the MpO methodology is evaluated using three design experiments: a packet parser, a flow-based traffic manager, and a digital up-converter. Based on experiments, we show that MpO can be comparable to handwritten VHDL code while keeping a high abstraction level, humanreadable coding style and modularity. Compared to traditional C-based HLS design, MpO leads to more efficient circuit generation, both in terms of performance and resource utilization. Also, the MpO approach notably improves software quality, augmenting parameterization while eliminating the incidence of code duplication.

关键词： C++ languages Field programmable gate arrays Tools Hardware Design methodology DSL Software

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Exploring the Vision Processing Unit as Co-processor for Inference 32

Exploring the Vision Processing Unit as Co-processor for Inf...

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Rivas-Gomez, Sergio Pena, Antonio J. Moloney, David Laure, Erwin Markidis, Stefano KTH Royal Inst Technol Stockholm Sweden Barcelona Supercomp Ctr BSC Barcelona Spain Intel Ireland Ltd Collinstown Ireland

ISBN: (纸本)9781538655559

the success of the exascale supercomputer is largely debated to remain dependent on novel breakthroughs in technology that effectively reduce the power consumption and thermal dissipation requirements. In this work, we consider the integration of co-processors in high-performance computing (HPC) to enable low-power, seamless computation offloading of certain operations. In particular, we explore the so-called Vision Processing Unit (VPU), a highly-parallel vector processor with a power envelope of less than 1W. We evaluate this chip during inference using a pre-trained GoogLeNet convolutional network model and a large image dataset from the ImageNet ILSVRC challenge. Preliminary results indicate that a multiVPU configuration provides similar performance compared to reference CPU and GPU implementations, while reducing the thermal-design power (TDP) up to 8 x in comparison.

关键词： Vision Processing Unit high-performance computing Machine Learning

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