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Towards Green Scientific Data Compression through high-Level I/O Interfaces 30

Towards Green Scientific Data Compression Through High-Level...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Alforov, Yevhen Novikova, Anastasiia Kuhn, Michael Kunkel, Julian Ludwig, thomas Deutsch Klimarechenzentrum GmbH Hamburg Germany Univ Hamburg Hamburg Germany Univ Reading Reading Berks England

ISBN: (纸本)9781538677698

Every HPC system today has to cope with a deluge of data generated by scientific applications, simulations or large-scale experiments. the upscaling of supercomputer systems and infrastructures, generally results in a dramatic increase of their energy consumption. In this paper, we argue that techniques like data compression can lead to significant gains in terms of power efficiency by reducing both network and storage requirements. However, any data reduction is highly data specific and should comply with established requirements. therefore, unsuitable or inappropriate compression strategy can utilize more resources and energy than necessary. To that end, we propose a novel methodology for achieving on-the-fly intelligent determination of energy efficient data reduction for a given data set by leveraging state-of-the-art compression algorithms and meta data at application-level I/O. We motivate our work by analyzing the energy and storage saving needs of data sets from real-life scientific HPC applications, and review the various lossless compression techniques that can be applied. We find that the resulting data reduction can decrease the data volume transferred and stored by as much as 80% in some cases, consequently leading to significant savings in storage and networking costs.

关键词： HPC I/O interfaces data reduction compression energy consumption

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Perception-Oriented 3D Rendering Approximation for Modern Graphics Processors 24

Perception-Oriented 3D Rendering Approximation for Modern Gr...

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Xie, Chenhao Fu, Xin Song, Shuaiwen Leon Univ Houston ECMOS Lab ECE Dept Houston TX 77004 USA PNNL High Performance Comp Grp Richland WA USA

ISBN: (纸本)9781538636596

Anisotropic filtering enabled by modern rasterization-based GPUs provides users with extremely authentic visualization experience, but significantly limits the performance and energy efficiency of 3D rendering process due to its large texture data requirement. To improve 3D rendering efficiency, we build a bridge between anisotropic filtering process and human visual system by analyzing users' perception on image quality. We discover that anisotropic filtering does not impact user perceived image quality on every pixel. this motives us to approximate the anisotropic filtering process for non-perceivable pixels in order to improve the overall 3D rendering performance without damaging user experience. To achieve this goal, we propose a perception-oriented runtime approximation model for 3D rendering by leveraging the inner-relationship between anisotropic and isotropic filtering. We also provide a low-cost texture unit design for enabling this approximation. Extensive evaluation on modern 3D games demonstrates that, under a conservative tuning point, our design achieves a significant average speedup of 17% for the overall 3D rendering along with 11% total GPU energy reduction, without visible image quality loss from users' perception. It also reduces the texture filtering latency by an average of 29%. Additionally, it creates a unique perception-based tuning space for performance-quality tradeoffs on graphics processors.

关键词： GPU Approximate computing 3D Rendering User-Oriented Study

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HyperSpace: Distributed Bayesian Hyperparameter Optimization 30

HyperSpace: Distributed Bayesian Hyperparameter Optimization

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Young, M. Todd Hinkle, Jacob Ramanathan, Arvind Kannan, Ramakrishnan Oak Ridge Natl Lab Computat Sci & Engn Div Oak Ridge TN 37830 USA Oak Ridge Natl Lab Comp Sci & Math Div Oak Ridge TN USA

ISBN: (纸本)9781538677698

As machine learning models continue to increase in complexity, so does the potential number of free model parameters commonly known as hyperparameters. While there has been considerable progress toward finding optimal configurations of these hyperparameters, many optimization procedures are treated as black boxes. We believe optimization methods should not only return a set of optimized hyperparameters, but also give insight into the effects of model hyperparameter settings. To this end, we present HyperSpace, a parallel implementation of Bayesian sequential model-based optimization. HyperSpace leverages high performance computing (HPC) resources to better understand unknown, potentially non-convex hyperparameter search spaces. We show that it is possible to learn the dependencies between model hyperparameters through the optimization process. By partitioning large search spaces and running many optimization procedures in parallel, we also show that it is possible to discover families of good hyperparameter settings over a variety of models including unsupervised clustering, regression, and classification tasks.

关键词： Bayesian optimization SMBO parallel computing HPC

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In-situ AI: Towards Autonomous and Incremental Deep Learning for IoT Systems 24

In-situ AI: Towards Autonomous and Incremental Deep Learning...

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Song, Mingcong Zhong, Kan Zhang, Jiaqi Hu, Yang Liu, Duo Zhang, Weigong Wang, Jing Li, Tao Univ Florida Gainesville FL 32611 USA Chongqing Univ Chongqing Peoples R China Univ Texas Dallas Richardson TX 75083 USA Capital Normal Univ Beijing Peoples R China

ISBN: (纸本)9781538636596

Recent years have seen an exploration of data volumes from a myriad of IoT devices, such as various sensors and ubiquitous cameras. the deluge of IoT data creates enormous opportunities for us to explore the physical world, especially with the help of deep learning techniques. Traditionally, the Cloud is the option for deploying deep learning based applications. However, the challenges of Cloud-centric IoT systems are increasing due to significant data movement overhead, escalating energy needs, and privacy issues. Rather than constantly moving a tremendous amount of raw data to the Cloud, it would be beneficial to leverage the emerging powerful IoT devices to perform the inference task. Nevertheless, the statically trained model could not efficiently handle the dynamic data in the real in-situ environments, which leads to low accuracy. Moreover, the big raw IoT data challenges the traditional supervised training method in the Cloud. To tackle the above challenges, we propose In-situ AI, the first Autonomous and Incremental computing framework and architecture for deep learning based IoT applications. We equip deep learning based IoT system with autonomous IoT data diagnosis (minimize data movement), and incremental and unsupervised training method (tackle the big raw IoT data generated in ever-changing in-situ environments). To provide efficient architectural support for this new computing paradigm, we first characterize the two In-situ AI tasks (i.e. inference and diagnosis tasks) on two popular IoT devices (i.e. mobile GPU and FPGA) and explore the design space and tradeoffs. Based on the characterization results, we propose two working modes for the In-situ AI tasks, including Single-running and Co-running modes. Moreover, we craft analytical models for these two modes to guide the best configuration selection. We also develop a novel two-level weight shared In-situ AI architecture to efficiently deploy In-situ tasks to IoT node. Compared with traditional IoT sy

关键词： Task analysis Machine learning Cloud computing Data models Training computer architecture

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DUO: Exposing On-chip Redundancy to Rank-Level ECC for high Reliability 24

DUO: Exposing On-chip Redundancy to Rank-Level ECC for High ...

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Gong, Seong-Lyong Kim, Jungrae Lym, Sangkug Sullivan, Michael David, Howard Erez, Mattan UT Austin Austin TX 78712 USA Microsoft Albuquerque NM USA NVIDIA Santa Clara CA USA Huawei Shenzhen Peoples R China

ISBN: (纸本)9781538636596

DRAM row and column sparing cannot efficiently tolerate the increasing inherent fault rate caused by continued process scaling. In-DRAM ECC (IECC), an appealing alternative to sparing, can resolve inherent faults without significant changes to DRAM, but it is inefficient for highly-reliable systems where rank-level ECC (RECC) is already used against operational faults. In addition, DRAM design in the near future (possibly as early as DDR5) may transfer data in longer bursts, which complicates high-reliability RECC due to fewer devices being used per rank and increased fault granularity. We propose dual use of on-chip redundancy (DUO), a mechanism that bypasses the IECC module and transfers on-chip redundancy to be used directly for RECC. Due to its increased redundancy budget, DUO enables a strong and novel RECC for highly-reliable systems, called DUO SDDC. the long codewords of DUO SDDC provide fundamentally higher detection and correction capabilities, and several novel secondary-correction techniques integrate together to further expand its correction capability. According to our evaluation results, DUO shows performance degradation on par with or better than IECC (average 2-3%), while consuming less DRAM energy than IECC (average 4-14% overheads). DUO provides higher reliability than either IECC or the state-of-the-art ECC technique. We show the robust reliability of DUO SDDC by comparing it to other ECC schemes using two different inherent fault-error models.

关键词： DRAM reliability scaling errors ECC

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ADeLe: Rapid Architectural Simulation for Approximate Hardware 30

ADeLe: Rapid Architectural Simulation for Approximate Hardwa...

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30th international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Felzmann, Isaias B. Susin, Matheus M. Duenha, Liana Azevedo, Rodolfo Wanner, Lucas F. Univ Estadual Campinas Inst Comp Campinas SP Brazil Univ Fed Mato Grosso do Sul Fac Comp FACOM Campo Grande Brazil

ISBN: (纸本)9781538677698

Recent research has introduced approximate hardware units that produce incorrect outputs deterministically or probabilistically for some small subset of inputs but allow significantly higher throughput or lower power than their error-free counterparts. the integration, validation, and evaluation of these approximate units in architectures and processors, however, remains challenging. In this paper, we introduce ADeLe, a high-level language for the description, configuration, and integration of approximate hardware units into processors. ADeLe reduces the design effort for approximate hardware by modeling approximations at a high level of abstraction and automatically injecting them into a processor model for architectural simulation. Approximations in ADeLe may modify or completely replace the functional behavior of instructions according to user-defined policies. Instructions may be approximated deterministically or probabilistically (e.g., based on operating voltage and frequency). To allow for controlled testing, approximations may be enabled and disabled from software. Energy is automatically accounted based on customizable models that consider the potential power savings of the approximations that are enabled in the system. ADeLe provides designers with a generic and flexible verification framework, allowing them to easily evaluate the energy-quality trade-offs of their designs in applications. We demonstrate the language and corresponding framework by introducing different approximation techniques into a processor model, on top of which we run selected applications. We demonstrate ADeLe using 6 approximate designs with 4 image processing and 2 floating point applications. Our experiments show how ADeLe may be used to generate approximate CPUs and to evaluate energy-quality trade-offs for different applications with reduced effort.

关键词： Computational modeling Hardware Data models computer architecture Registers Integrated circuit modeling Software

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Cost-Effective Energy Monitoring of a Zynq-Based Real-Time System Including Dual Gigabit Ethernet

Cost-Effective Energy Monitoring of a Zynq-Based Real-Time S...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Martin Geier Dominik Faller Marian Brändle Samarjit Chakraborty Chair of Real-Time Computer Systems Technical University of Munich

Recent FPGA architectures integrate various power management features already established in CPU-driven SoCs to reach more energy-sensitive application domains such as, e.g., automotive and robotics. this also qualifies hybrid Programmable SoCs (pSoCs) that combine fixed-function SoCs with configurable FPGA fabric for heterogeneous Real-time Systems (RTSs), which operate under predefined latency and power constraints in safety-critical environments. their complex application-specific computation and communication (incl. I/O) architectures result in highly varying power consumption, which requires precise voltage and current sensing on all relevant supply rails to enable dependable evaluation of available and novel power management techniques. In this paper, we propose a low-cost 18-channel 16-bit-resolution measurement system capable of over 200 kSPS (kilo-samples per second) for instrumentation of current pSoC development boards. In addition, we propose to include crucial I/O components such as Ethernet PHYs into the power monitoring to gain a holistic view on the RTS's temporal behavior covering not only computation on FPGA and CPUs, but also communication in terms of, e.g., reception of sensor values and transmission of actuation signals. We present an FMC-sized implementation of our measurement system combined with two Gigabit Ethernet PHYs and one HDMI input. Paired with Xilinx' ZC702 development board, we are able to synchronously acquire power traces of a Zynq pSoC and the two PHYs precise enough to identify individual Ethernet frames.

关键词： Ethernet Field programmable gate arrays Monitoring Real-time systems computer architecture Rails Current measurement

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Accelerate GPU Concurrent Kernel Execution by Mitigating Memory Pipeline Stalls 24

Accelerate GPU Concurrent Kernel Execution by Mitigating Mem...

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Dai, Hongwen Lin, Zhen Li, Chao Zhao, Chen Wang, Fei Zheng, Nanning Zhou, Huiyang North Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA Xi An Jiao Tong Univ Sch Elect & Informat Engn Xian Shaanxi Peoples R China

ISBN: (纸本)9781538636596

Following the advances in technology scaling, graphics processing units (GPUs) incorporate an increasing amount of computing resources and it becomes difficult for a single GPU kernel to fully utilize the vast GPU resources. One solution to improve resource utilization is concurrent kernel execution (CKE). Early CKE mainly targets the leftover resources. However, it fails to optimize the resource utilization and does not provide fairness among concurrent kernels. Spatial multitasking assigns a subset of streaming multiprocessors (SMs) to each kernel. Although achieving better fairness, the resource underutilization within an SM is not addressed. thus, intra-SM sharing has been proposed to issue thread blocks from different kernels to each SM. However, as shown in this study, the overall performance may be undermined in the intra-SM sharing schemes due to the severe interference among kernels. Specifically, as concurrent kernels share the memory subsystem, one kernel, even as computing-intensive, may starve from not being able to issue memory instructions in time. Besides, severe L1 D-cache thrashing and memory pipeline stalls caused by one kernel, especially a memory-intensive one, will impact other kernels, further hurting the overall performance. In this study, we investigate various approaches to overcome the aforementioned problems exposed in intra-SM sharing. We first highlight that cache partitioning techniques proposed for CPUs are not effective for GPUs. then we propose two approaches to reduce memory pipeline stalls. the first is to balance memory accesses of concurrent kernels. the second is to limit the number of inflight memory instructions issued from individual kernels. Our evaluation shows that the proposed schemes significantly improve the weighted speedup of two state-of-the-art intra-SM sharing schemes, Warped-Slicer and SMK, by 24.6% and 27.2% on average, respectively, with lightweight hardware overhead.

关键词： Kernel Graphics processing units Pipelines Instruction sets Resource management Benchmark testing computer architecture

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Making Memristive Neural Network Accelerators Reliable 24

Making Memristive Neural Network Accelerators Reliable

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24th ieee international symposium on high performance computer architecture (HPCA)

作者： Feinberg, Ben Wang, Shibo Ipek, Engin Univ Rochester Dept Elect & Comp Engn 601 Elmwood Ave Rochester NY 14627 USA Univ Rochester Dept Comp Sci Rochester NY 14627 USA

ISBN: (纸本)9781538636596

Deep neural networks (DNNs) have attracted substantial interest in recent years due to their superior performance on many classification and regression tasks as compared to other supervised learning models. DNNs often require a large amount of data movement, resulting in performance and energy overheads. One promising way to address this problem is to design an accelerator based on in-situ analog computing that leverages the fundamental electrical properties of memristive circuits to perform matrix-vector multiplication. Recent work on analog neural network accelerators has shown great potential in improving both the system performance and the energy efficiency. However, detecting and correcting the errors that occur during in-memory analog computation remains largely unexplored. the same electrical properties that provide the performance and energy improvements make these systems especially susceptible to errors, which can severely hurt the accuracy of the neural network accelerators. this paper examines a new error correction scheme for analog neural network accelerators based on arithmetic codes. the proposed scheme encodes the data through multiplication by an integer, which preserves addition operations through the distributive property. Error detection and correction are performed through a modulus operation and a correction table lookup. this basic scheme is further improved by data-aware encoding to exploit the state dependence of the errors, and by knowledge of how critical each portion of the computation is to overall system accuracy. By leveraging the observation that a physical row that contains fewer 1s is less susceptible to an error, the proposed scheme increases the effective error correction capability with less than 4.5% area and less than 4.7% energy overheads. When applied to a memristive DNN accelerator performing inference on the MNIST and ILSVRC-2012 datasets, the proposed technique reduces the respective misclassification rates by 1.5x and 1.

关键词： computer architecture Accelerator architectures

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Charm: A Language for Closed-form high-level architecture Modeling 18

Charm: A Language for Closed-form High-level Architecture Mo...

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45th ACM/ieee Annual international symposium on computer architecture (ISCA)

作者： Cui, Weilong Ding, Yongshan Dangwal, Deeksha Holmes, Adam McMahan, Joseph Javadi-Abhari, Ali Tzimpragos, Georgios Chong, Frederic T. Sherwood, Timothy Univ Calif Santa Barbara Santa Barbara CA 93106 USA Univ Chicago Chicago IL 60637 USA IBM Res New York NY USA

ISBN: (纸本)9781538659847

As computer architecture continues to expand beyond software-agnostic microarchitecture to data center organization, reconfigurable logic, heterogeneous systems, application-specific logic, and even radically different technologies such as quantum computing, detailed cycle-level simulation is no longer presupposed. Exploring designs under such complex interacting relationships (e.g., performance, energy, thermal, cost, voltage, frequency, cooling energy, leakage, etc.) calls for a more integrative but higher-level approach. We propose Charm, a domain specific language supporting Closed-form high-level architecture Modeling. Charm enables mathematical representations of mutually dependent architectural relationships to be specified, composed, checked, evaluated and reused. the language is interpreted through a combination of symbolic evaluation (e.g., restructuring) and compiler techniques (e.g., memoization and invariant hoisting), generating executable evaluation functions and optimized analysis procedures. Further supporting reuse, a type system constrains architectural quantities and ensures models operate only in a validated domain. through two case studies, we demonstrate that Charm allows one to define high-level architecture models concisely, maximize reusability, capture unreasonable assumptions and inputs, and significantly speed-up design space exploration.

关键词： abstraction modeling DSL

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