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Improvement of the Log Pattern Extracting Algorithm Using Text Similarity 32

Improvement of the Log Pattern Extracting Algorithm Using Te...

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Zhao, Yining Wang, Xiaodong Xiao, Haili Chi, Xuebin Chinese Acad Sci Comp Network Informat Ctr Beijing Peoples R China Chinese Acad Sci Univ Chinese Acad Sci Comp Network Informat Ctr Beijing Peoples R China

ISBN: (纸本)9781538655559

Log processing and analysis are key jobs that can obtain information about system status and alerts, and log classification is the fundamental step. We have previously proposed the LARGE system and the algorithm of log pattern extraction to transfer system logs into a set of log pattern to help system maintainers find messages hidden in logs. But the proposed algorithm has the limitation that it cannot deal with log length differences. In this paper we will introduce the way of improving log pattern extracting algorithm by involving the idea of text similarity. Experiment results prove that the new algorithm shows obvious improvement than the original one. We also illustrate a modified log comparing model that fits real time log processing systems.

关键词： log processing big-data analysis text similarity high-performance computing environment

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POSTER: An intelligent framework to parallelize hadoop phases 18

POSTER: An intelligent framework to parallelize hadoop phase...

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27th ACM international symposium on high-performance Parallel and Distributed computing, HPDC 2018

作者： Maleki, Neda Rahmani, Amir Masoud Conti, Mauro Department of Computer Engineering Science and Research Branch Islamic Azad University Tehran Iran Department of Mathematics University of Padua Padua Italy

ISBN: (纸本)9781450358996

Hadoop-stock is a reliable, scalable, and open source implementation of the MapReduce framework to process data-intensive applications in a distributed and parallel environment. In a common environment between multiple users with various types of applications, due to the lower number of resources than the number of jobs, there will be multi-wave jobs. Shuffling as the longest phase of running a job has the most adverse effect (network traffic) on the job execution time. On one hand, due to the dependency of shuffle phase to reduce task, the shuffle phase could not start until the reduce task being scheduled. On the other hand, the static scheduling of reduce tasks results in loss of reduce slots. this paper presents our ongoing effort in the designing an intelligent service in which the sort/merge and shuffle phases are completely independent of map and reduce phases and could act in parallel with map and reduce phases. this parallelism mitigates the job completion time. © 2018 Association for computing Machinery.

关键词： MapReduce

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Development and application of a hybrid programming environment on an ARM/DSP system for high performance computing 32

Development and application of a hybrid programming environm...

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Mitra, Gaurav Bohmann, Jonathan Gauthier, thea-Martine O. Rendell, Alistair P. Texas Instruments Inc Dallas TX 75265 USA Southwest Res Inst San Antonio TX USA nCore HPC Petaluma CA USA Australian Natl Univ Canberra ACT Australia

ISBN: (纸本)9781538643686

the nCore Brown-Dwarf system has a unique architecture where each node is comprised of two different low-power System-on-Chip (LPSoC) processors from Texas Instruments;the ARM/DSP Keystone II SoC and the DSP based Keystone I SoC. these LPSoC processors have, through use of the C66x multi-core DSP, been shown to be capable of running floating-point intensive HPC application codes. However, it is non-trivial to run such codes across all processing elements of a node simultaneously. this paper demonstrates a hybrid programming environment that combines OpenMP, OpenCL and MPI to enable application execution across multiple Brown-Dwarf nodes. this environment is evaluated using two diverse application codes. the first is Level-3 BLAS matrix multiplication (GEMM), which is a standard HPC floating-point intensive benchmark. the second is a unique real-world scientific code for biostructure based drug design developed by the Southwest Research Institute called Rhodium (TM). performance and energy-efficiency of Rhodium (TM) is presented alongside comparisons with conventional x86 based HPC systems with attached accelerators. Results indicate that the Brown-Dwarf system remains competitive with contemporary systems for memory-bound computations.

关键词： ARM C66x DSP Keystone II Brown-Dwarf Protein Docking Drug Design Protein Engineering Accelerator OpenMP OpenCL Energy Efficiency

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Asymmetric-ReRAM: A Low Latency and high Reliability Crossbar Resistive Memory architecture 16

Asymmetric-ReRAM: A Low Latency and High Reliability Crossba...

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16th ieee ISPA / 17th ieee IUCC / 8th ieee BDCloud / 11th ieee SocialCom / 8th ieee SustainCom

作者： Zhang, Yang Feng, Dan Tan, Zhipeng Liu, Jingning Tong, Wei Wang, Chengning Huazhong Univ Sci & Technol Minist Educ China Key Lab Informat Storage Syst Wuhan Natl Lab OptoelectSch Comp Sci & Technol Wuhan Hubei Peoples R China

ISBN: (纸本)9781728111414

Resistive Memory (ReRAM) is promising to be used as the storage-class memory due to its good scalability, high density, low standby power and non-volatility. By employing the unique crossbar structure, ReRAM can be constructed with extremely high density. However, ReRAM's crossbar structure suffers from an IR drop issue, which causes the asymmetric access latency in crossbar arrays. Moreover, without access transistors in the crossbar structure, read and write disturbances lead to serious data reliability problem. In this paper, we propose Asymmetric-ReRAM (A-ReRAM) to overcome the challenges of crossbar ReRAM. By reducing the IR drops along both wordlines and bitlines, leveraging the asymmetric access latency in crossbar arrays and exposing the most appropriate write latency to the memory controller, A-ReRAM effectively reduces the access latency. By applying the circuit-architecture level solutions, A-ReRAM addresses the read and write disturbances, and significantly improves the reliability. the experimental results show that, A-ReRAM improves system performance by 29.7% and 19.2%, and reduces the energy consumption by 21.1% and 11.3% on average, compared to the baseline and the state-of-the-art crossbar ReRAM design. Meanwhile, A-ReRAM significantly improves the reliability of ReRAM-based memory systems.

关键词： ReRAM crossbar IR drop asymmetric access latency read and write disturbances

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Accelerating Lattice QCD on Sunway Many-core Processor 16

Accelerating Lattice QCD on Sunway Many-core Processor

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16th ieee ISPA / 17th ieee IUCC / 8th ieee BDCloud / 11th ieee SocialCom / 8th ieee SustainCom

作者： Zhang Zengxiao Luan Zhongzhi Xu Chongyang Gong Ming Xu Shun Beihang Univ Sch Comp Sci & Engn Beijing Peoples R China Chinese Acad Sci Inst High Energy Phys Beijing Peoples R China Chinese Acad Sci Comp Network Informat Ctr Beijing Peoples R China

ISBN: (纸本)9781728111414

Lattice quantum chromodynamics (lattice QCD) is a mainstream non-perturbative theoretical calculation method. It's for studying quantum chromodynamics (QCD) using lattice quantum field theory, by defining field variables at discrete time-space points and large-scale Monte Carlo numerical simulation calculation. It's computing results can directly compare with the experimental results, but the conventional computing platform is difficult to meet the large-scale and high-precision lattice QCD computational simulation demand. Sunway TaihuLight is the first supercomputer with peak performance over 100Pflops in the world, which provides a new platform for the calculation of lattice QCD. But the efficient large-scale parallel lattice QCD computing faces many difficult problems in implement. In order to realize the efficient calculation of the lattice QCD in Sunway many-core processor, we designs a parallel acceleration calculation method of lattice QCD on Sunway architecture in this paper. A new parallel computing method is put forward, and the method of data segmentation, data transmission and parallel computing is improved and optimized. Finally, the test data is used to test the optimized parallelization computing method proposed in this paper and the original serial computing method. Experiments show that the parallel optimized computing method can achieve 63 times performance improvement compared with the original serial computing method.

关键词： Sunway many-core processor lattice QCD Parallel computing Super computer

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Streaming architecture for Large-Scale Quantized Neural Networks on an FPGA-Based Dataflow Platform 32

Streaming Architecture for Large-Scale Quantized Neural Netw...

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Baskin, Chaim Zheltonozhskii, Evgenii Bronstein, Alex M. Mendelson, Avi Liss, Natan Technion Israel Inst Technol Dept Comp Sci Haifa Israel Technion Israel Inst Technol Dept Elect Engn Haifa Israel

ISBN: (纸本)9781538655559

Deep neural networks (DNNs) are used by different applications that are executed on a range of computer architectures, from IoT devices to supercomputers. the footprint of these networks is huge as well as their computational and communication needs. In order to ease the pressure on resources, research indicates that in many cases a low precision representation (1-2 bit per parameter) of weights and other parameters can achieve similar accuracy while requiring less resources. Using quantized values enables the use of FPGAs to run NNs, since FPGAs are well fitted to these primitives;e.g., FPGAs provide efficient support for bitwise operations and can work with arbitrary-precision representation of numbers. this paper presents a new streaming architecture for running QNNs on FPGAs. the proposed architecture scales out better than alternatives, allowing us to take advantage of systems with multiple FPGAs. We also included support for skip connections, that are used in state-of-the art NNs, and shown that our architecture allows to add those connections almost for free. All this allowed us to implement an 18-layer ResNet for 224 x 224 images classification, achieving 57.5% top-1 accuracy. In addition, we implemented a full-sized quantized AlexNet. In contrast to previous works, we use 2-bit activations instead of 1-bit ones, which improves AlexNet's top-1 accuracy from 41.8% to 51.03% for the ImageNet classification. Both AlexNet and ResNet can handle 1000-class real-time classification on an FPGA. Our implementation of ResNet-18 consumes 5x less power and is 4x slower for ImageNet, when compared to the same NN on the latest Nvidia GPUs. Smaller NNs, that fit a single FPGA, are running faster then on GPUs on small (32 x 32) inputs, while consuming up to 20 x less energy and power.

关键词： Field programmable gate arrays computer architecture Artificial neural networks Kernel high level languages Computational modeling Optimization"

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Sonar: Writing Testbenches through Python

Sonar: Writing Testbenches through Python

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Varun Sharma Naif Tarafdar Paul Chow Department of Electrical and Computer Engineering University of Toronto Toronto Ontario

Design verification is an important though time-consumingaspect of hardware design. A good testbench should supportperforming functional coverage of a design by making it easy to implement tests and determine which tests are being performed. However, for complex designs, creating and main-taining effective testbenches can take increasing amounts of time away from actual design. A further complication is there may be two development flows: conventional hardware written in a hardware description language (HDL) such as Verilog orVHDL and high-level synthesis (HLS). In the HLS approach, the hardware is specified in a higher-level language (HLL) and then converted to an HDL through HLS tools. In this flow, testbenches for the design are written in the same HLLand cosimulation is used to verify the generated HDL. Due totool restrictions, cosimulation may not always work. In VivadoHLS [1] for example, the design must contain control signals to define when to start and stop the module or the initiation interval for new data must be one cycle. Without cosimulation, the user must write an HDL testbench manually in addition to a testbench in the HLL for preliminary verification. To simplify writing testbenches, we present Sonar: an open-source Python library to write cross-language testbenches. From a common source script, Sonar can generate testbenches written in SystemVerilog (SV) and C++. these files can then be imported into standard simulation tools such as ModelSim[2] or Vivado HLS and run. the use of Python makes it easy to extend Sonar with higher layers of abstraction for testbenches and integrate it with other software *** is available at https://***/UofT-HPRC/sonar.

关键词： Sonar Hardware Field programmable gate arrays Hardware design languages Tools Machine learning Neural networks

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Scalable Collectives for Distributed Asynchronous Many-Task Runtimes 32

Scalable Collectives for Distributed Asynchronous Many-Task ...

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27th international Heterogeneity in computing Workshop in conjunction with 32nd ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Whitlock, Matthew Kolla, Hemanth Treichler, Sean Pebay, Philippe Bennett, Janine C. Oklahoma State Univ Stillwater OK 74078 USA Sandia Natl Labs Livermore CA 94550 USA Stanford Univ Stanford CA 94305 USA NexGen Analyt Sheridan WY USA

ISBN: (纸本)9781538655559

Global collectives (reductions/aggregations) are ubiquitous and feature in nearly every application of distributed high-performance computing (HPC). While it is advisable to devise algorithms by placing collectives off the critical path of execution, they are sometimes unavoidable for correctness, numerical convergence and analyses purposes. Scalable algorithms for distributed collectives are well studied and have become an integral part of MPI, but new and emerging distributed computing frameworks and paradigms such as Asynchronous Many-Task (AMT) models lack the same sophistication for distributed collectives. Since the central promise of AMT runtimes is that they automatically discover, and expose, task dependencies in the underlying program and can schedule work optimally to minimize idle time and hide data movement, a naively designed collectives protocol can completely offset any gains made from asynchronous execution. In this study we demonstrate that scalable distributed collectives are indispensable for performance in AMT models. We design, implement and test the performance of a scalable collective algorithm in Legion, an exemplar data-centric AMT programming model. Our results show that AMT systems contain the necessary primitives that allow for fully scalable collectives without breaking the transparent data movement abstractions. Scalabiity tests of an integrated Legion 1D stencil mini-application show the clear benefit of implementing scalable collectives and the performance degradation when a naive collectives alternative is used instead.

关键词： Programming Models Asynchronous Many-Task Parallel computing Distributed Collectives Computational Statistics

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A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Floating-Point Unit for a 64 bit RISC-V Processor in 22nm FD-SOI

A 0.80pJ/flop, 1.24Tflop/sW 8-to-64 bit Transprecision Float...

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IFIP international Conference on Very Large Scale Integration (VLSI-SoC)

作者： Stefan Mach Fabian Schuiki Florian Zaruba Luca Benini Integrated Systems Laboratory (IIS) Swiss Federal Institute of Technology Zurich Switzerland

the crisis of Moore's law and new dominant Machine Learning workloads require a paradigm shift towards finely tunable-precision (a.k.a. transprecision) computing. More specifically, we need floating-point circuits that are capable to operate on many formats with high flexibility. We present the first silicon implementation of a 64-bit transprecision floating-point unit. It fully supports the standard double, single, and half precision, alongside custom bfloat and 8 bit formats. Operations occur on scalars or 2, 4, or 8-way SIMD vectors. We have integrated the 247 kGE unit into a 64 bit application-class RISC-V processor core, where the added transprecision support accounts for an energy and area overhead of merely 11% and 9%, respectively; yet achieving speedups and per-datum energy gains of 7.3x and 7.94x. We implemented the design in a 22 nm FD-SOI technology. the unit achieves energy efficiencies between 75 Gflop/sW and 1.24 Tflop/sW, and a performance between 1.85 Gflop/s and 14.83 Gflop/s, across formats.

关键词： Clocks computer architecture Pipelines Registers Silicon Hardware Open area test sites

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Towards Affordable Fault-Tolerant Nanosatellite computing with Commodity Hardware 27

Towards Affordable Fault-Tolerant Nanosatellite Computing wi...

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27th ieee Asian Test symposium (ATS)

作者： Fuchs, Christian M. Murillo, Nadia M. Plaat, Aske van der Kouwe, Erik Wang, Peng Leiden Univ Leiden Inst Adv Comp Sci Leiden Netherlands Leiden Univ Leiden Observ Leiden Netherlands

ISBN: (纸本)9781538694664

Modern embedded and mobile-market processor technology is a cornerstone of miniaturized satellite design. this type of lighter, cheaper, and rapidly developed spacecraft has enabled a variety of new commercial and scientific missions. However micro- and nanosatellites (<= 100kg) currently are not considered suitable for critical, high-priority, and complex multi-phased missions, due to their low reliability. the hardware fault tolerance (FT) concepts used aboard larger spacecraft can usually not be used, due to tight energy and mass constraints, as well as disproportional costs. thus, we developed a hardware-software hybrid FT-approach, which enables FT through software-side coarse-grain lockstep, FPGA reconfiguration, and thread-level mixed criticality. this allows our FPGA-based proof-of-concept implementation to deliver strong fault coverage even for missions with a long duration, but also to adapt to varying performance requirements during the mission. In this paper, we present the implementation results on a tiled multiprocessor system-on-a-chip (MPSoC) design we developed as an ideal platform for our approach. We provide details on the validation of our approach through fault injection, which show that our lockstep implementation is effective and efficient for providing FDIR within our system, and show in direct comparison that our results are consistent with related work. these results show that our architecture is effective, overhead efficient, and remains within the tight energy, complexity, and cost limitations of even very small spacecraft such as CubeSats. To our knowledge, this is the first fault mitigation approach offering strong fault tolerance, which can uphold computational correctness viable for miniaturized spacecraft and is not dependent on proprietary processor cores.

关键词： Space vehicles Circuit faults Field programmable gate arrays Instruction sets computer architecture Satellites Fault detection

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