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there and Back Again: Optimizing the Interconnect in Networks of Memory Cubes 17

There and Back Again: Optimizing the Interconnect in Network...

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44th Annual international symposium on computer architecture (ISCA)

作者： Poremb, Matthew Akgun, Itir Yin, Jieming Kayiran, Onur Xie, Yuan Loh, Gabriel H. Adv Micro Devices Inc Sunnyvale CA 94088 USA Univ Calif Santa Barbara Santa Barbara CA 93106 USA

ISBN: (纸本)9781450348928

high-performance computing, enterprise, and datacenter servers are driving demands for higher total memory capacity as well as memory performance. Memory "cubes" with high per-package capacity (from 3D integration) along with high-speed point-to-point interconnects provide a scalable memory system architecture with the potential to deliver both capacity and performance. Multiple such cubes connected together can form a "Memory Network" (MN), but the design space for such MNs is quite vast, including multiple topology types and multiple memory technologies per memory cube. In this work, we first analyze several MN topologies with different mixes of memory package technologies to understand the key tradeoffs and bottlenecks for such systems. We find that most of a MN's performance challenges arise from the interconnection network that binds the memory cubes together. In particular, arbitration schemes used to route through MNs, ratio of NVM to DRAM, and specific topologies used have dramatic impact on performance and energy results. Our initial analysis indicates that introducing non-volatile memory to the MN presents a unique tradeoff between memory array latency and network latency. We observe that placing NVM cubes in a specific order in the MN improves performance by reducing the network size/diameter up to a certain NVM to DRAM ratio. Novel MN topologies and arbitration schemes also provide performance and energy deltas by reducing the hop count of requests and response in the MN. Based on our analyses, we introduce three techniques to address MN latency issues: (1) Distance-based arbitration scheme to improve queuing latencies throughout the network, (2) skip-list topology, derived from the classic data structure, to improve network latency and link usage, and (3) the MetaCube, a denser memory cube that leverages advanced packaging technologies to improve latency by reducing MN size.

关键词： high-performance computing memory cube memory network nonvolatile memory

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Towards a Dataflow Runtime Environment for Edge, Fog and In-Situ computing 29

Towards a Dataflow Runtime Environment for Edge, Fog and In-...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Carvalho, Caio B. G. Ferreira, Victor C. Franca, Felipe M. G. Bentes, Cristiana Alves, Tiago A. O. Sena, Alexandre C. Marzulo, Leandro A. J. PESC COPPE UFRJ Rio De Janeiro Brazil DESC FEN UERJ Rio De Janeiro Brazil DICC IME UERJ Rio De Janeiro Brazil

ISBN: (纸本)9781538648193

In the dataflow computation model, instructions or tasks are fired according to their data dependencies, instead of following program order, thus allowing natural parallelism exploitation. Dataflow has been used, in different flavors and abstraction levels (from processors to runtime libraries), as an interesting alternative for harnessing the potential of modern computing systems. Sucuri is a dataflow library for Python that allows users to specify their application as a dependency graph and execute it transparently at clusters of multicores, while taking care of scheduling issues. Recent trends in Fog and In-situ computing assumes that storage and network devices will be equipped with processing elements that usually have lower power consumption and performance. An important decision on such system is whether to move data to traditional processors (paying the communication costs), or performing computation where data is sitting, using a potentially slower processor. Hence, runtime environments that deal with that trade-off are extremely necessary. this work takes a first step towards a solution that considers Edge/Fog/In-situ in a dataflow runtime. We use Sucuri to manage the execution in a small system with a regular PC and a Parallella board. Experiments with text processing applications running with different input sizes, network latency and packet loss rates allow a discussion of scenarios where this approach would be fruitful.

关键词： Program processors Libraries computer architecture Runtime environment performance evaluation Field programmable gate arrays

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Strategies to Improve the performance of a Geophysics Model for Different Manycore Systems 29

Strategies to Improve the Performance of a Geophysics Model ...

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Serpa, Matheus S. Cruz, Eduardo H. M. Diener, Matthias Krause, Arthur M. Navaux, Philippe O. A. Farres, Albert Rosas, Claudia Hanzich, Mauricio Panetta, Jairo Fed Univ Rio Grande do Sul UFRGS Informat Inst Porto Alegre RS Brazil BSC Barcelona Spain Aeronaut Inst Technol ITA Comp Sci Div Sao Jose Dos Campos SP Brazil

ISBN: (纸本)9781538648193

Many software mechanisms for geophysics exploration in Oil & Gas industries are based on wave propagation simulation. To perform such simulations, state-of-art HPC architectures are employed, generating results faster and with more accuracy at each generation. the software must evolve to support the new features of each design to keep performance scaling. Furthermore, it is important to understand the impact of each change applied to the software, in order to improve the performance as most as possible. In this paper, we propose several optimization strategies for a wave propagation model for five architectures: Intel Haswell, Intel Knights Corner, Intel Knights Landing, NVIDIA Kepler and NVIDIA Maxwell. We focus on improving the cache memory usage, vectorization, and locality in the memory hierarchy. We analyze the hardware impact of the optimizations, providing insights of how each strategy can improve the performance. the results show that NVIDIA Maxwell improves over Intel Haswell, Intel Knights Corner, Intel Knights Landing and NVIDIA Kepler performance by up to 17.9x.

关键词： Optimization computer architecture Program processors Mathematical model Acoustic waves Hardware Cache memory

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Stochastic-Based Multi-Stage Streaming Realization of Deep Convolutional Neural Network 18

Stochastic-Based Multi-Stage Streaming Realization of Deep C...

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18th international symposium on Quality Electronic Design (ISQED)

作者： Alawad, Mohammed Lin, Mingjie Univ Cent Florida Dept Elect & Comp Engn Orlando FL 32816 USA

ISBN: (纸本)9781509054046

Large-scale convolutional neural network (CNN), conceptually mimicking the operational principle of visual perception in human brain, has been widely applied to tackle many challenging computer vision and artificial intelligence applications. Unfortunately, despite of its simple architecture, a typically-sized CNN is well known to be computationally intensive. this work presents a novel stochastic-based and scalable hardware architecture and circuit design that computes a large-scale CNN with FPGA. the key idea is to implement all key components of a deep learning CNN, including multi-dimensional convolution, activation, and pooling layers, completely in the probabilistic computing domain in order to achieve high computing robustness, high performance, and low hardware usage. Most importantly, through both theoretical analysis and FPGA hardware implementation, we demonstrate that stochastic-based deep CNN can achieve superior hardware scalability when compared with its conventional deterministic-based FPGA implementation by allowing a stream computing mode and adopting efficient random sample manipulations. Overall, being highly scalable and energy efficient, our stochastic-based convolutional neural network architecture is well-suited for a modular vision engine with the goal of performing real-time detection, recognition and segmentation of mega-pixel images, especially those perception-based computing tasks that are inherently fault-tolerant, while still requiring high energy efficiency.

关键词： Hardware Convolution Kernel computer architecture Field programmable gate arrays Probability density function Biological neural networks

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FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks

FlexiGAN: An End-to-End Solution for FPGA Acceleration of Ge...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Amir Yazdanbakhsh Michael Brzozowski Behnam Khaleghi Soroush Ghodrati Kambiz Samadi Nam Sung Kim Hadi Esmaeilzadeh Alternative Computing Technologies (ACT) Lab University of California San Diego Georgia Institute of Technology Qualcomm Technologies Inc. University of Illinois at Urbana-Champaign

Generative Adversarial Networks (GANs) are a frontier in deep learning. GANs consist of two models: generative and discriminative. While the discriminative model uses the conventional convolution, the generative model depends on a fundamentally different operator, called transposed convolution. this operator initially inserts a large number of zeros in its input and then slides a window over this expanded input. this zero-insertion step leads to a large number of ineffectual operations and creates distinct patterns of computation across the sliding windows. the ineffectual operations along with the variation in computation patterns lead to significant resource underutilization when using conventional convolution hardware. To alleviate these sources of inefficiency, this paper devises FlexiGAN, an end-to-end solution, that generates an optimized synthesizable FPGA accelerator from a high-level GAN specification. FlexiGAN is coupled with a novel template architecture that aims to harness the benefits of both MIMD and SIMD execution models to avoid ineffectual operations. To this end, the proposed architecture separates data retrieval and data processing units at the finest granularity of each compute engine. Leveraging this separation enables the architecture to use a succinct set of operations to cope with the irregularities of transposed convolution. At the same time, it significantly reduces the on-chip memory usage, which is generally limited in FPGAs. We evaluate our end-to-end solution by generating FPGA accelerators for a variety of GANs. these generated accelerators provide 2.4× higher performance than an optimized conventional convolution design. In addition, FlexiGAN, on average, yields 2.8× (up to 3.7×) improvements in performance-per-Watt over a Titan X GPU.

关键词： Gallium nitride Convolution Field programmable gate arrays computer architecture Acceleration Generative adversarial networks Microsoft Windows

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Parallel Algorithm for Dynamic Community Detection 29

Parallel Algorithm for Dynamic Community Detection

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8th international symposium on computer architecture and high performance computing (SBAC-PADW)

作者： Resende, Hugo Fazenda, Alvaro Luiz Quiles, Marcos Goncalves Fed Inst Educ Sci & Technol South Minas Gerais Pouso Alegre MG Brazil Univ Fed Sao Paulo Sao Paulo SP Brazil

ISBN: (纸本)9781538648193

Many real systems can be naturally modeled by complex networks. A complex network represents an abstraction of the system regarding its components and their respective interactions. thus, by scrutinizing the network, interesting properties of the system can be revealed. Among them, the presence of communities, which consists of groups of densely connected nodes, is a significant one. For instance, a community might reveal patterns, such as the functional units of the system, or even groups correlated people in social networks. Albeit important, the community detection process is not a simple computational task, in special when the network is dynamic. thus, several researchers have addressed this problem providing distinct methods, especially to deal with static networks. Recently, a new algorithm was introduced to solve this problem. the approach consists of modeling the network as a set of particles inspired by a N-body problem. Besides delivering similar results to state-of-the-art community detection algorithm, the proposed model is dynamic in nature;thus, it can be straightforwardly applied to time-varying complex networks. However, the Particle Model still has a major drawback. Its computational cost is quadratic per cycle, which restricts its application to mid-scale networks. To overcome this limitation, here, we present a novel parallel algorithm using many-core high-performance resources. through the implementation of a new data structure, named distance matrix, was allowed a massive parallelization of the particle's interactions. Simulation results show that our parallel approach, running both traditional CPUs and hardware accelerators based on multicore CPUs and GPUs, can speed up the method permitting its application to large-scale networks.

关键词： community detection massively parallel algorithm high-performance computing on hardware accelerators

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FPGA-Accelerated for Constrained high Dispersal Network 15

FPGA-Accelerated for Constrained High Dispersal Network

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15th ieee international symposium on Parallel and Distributed Processing with Applications (ISPA) / 16th ieee international Conference on Ubiquitous computing and Communications (IUCC)

作者： Chen, Yanliang Zhu, Minghua Xiao, Bo Meng, Dan East China Normal Univ MOE Res Ctr Software Hardware Codesign Engn & App Shanghai Peoples R China

ISBN: (纸本)9781538637906

In recent years, the Deep Neural Network (DNN) has been successfully used in image classification. Most of existing DNN often need to learn a very large set of parameters, which require a huge amount of computational resources and time to train these model parameters using the gradient descent and back-propagation procedure. To solve this issue, the PCANet has been developed for high efficient design and training of the DNN. Compared with traditional DNN, PCANet has simpler structure and better performance, which makes it attractive for hardware design. To overcome the limitations of PCANet and significantly improve its performance, we have proposed a novel model named Constrained high Dispersal Network (CHDNet) which is a variant of PCANet. In this paper, we implement the CHDNet on the Xilinx ZYNQ FPGA to ensure the instantaneity of the system with lower power than personal computer needed by taking advantage of the algorithmic parallelism and ZYNQ architecture. Our experimental results over two major datasets, the MNIST dataset for handwritten digits recognition, and the Extended Yale B dataset for face recognition, demonstrate that our model of implementation on FPGA is more than 15x faster than software implementation on PC (Intel i7-4720HQ, 2.6GHz).

关键词： Image classification Deep neural network FPGA high-level Synthesis

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Multilevel Observability in Cloud Orchestration

Multilevel Observability in Cloud Orchestration

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ieee international symposium on Dependable, Autonomic and Secure computing (DASC)

作者： Rodolfo Picoreti Alexandre Pereira do Carmo Felippe Mendonça de Queiroz Anilton Salles Garcia Raquel Frizera Vassallo Dimitra Simeonidou Electrical Engineering Department Federal University of Espirito Santo Vitória Brasil Electrical Engineering Department Federal Institute of Espirito Santo Guarapari Brasil High Performance Networks Group University of Bristol Bristol United Kingdom

ISBN: (纸本)9781538675199

Cloud infrastructures can provide resource sharing between many applications and usually can meet the requirements of most of them. However, in order to enable an efficient usage of these resources, automatic orchestration is required. Commonly, automatic orchestration tools are based on the observability of the infrastructure itself, but that is not enough in some cases. Certain classes of applications have specific requirements that are difficult to meet, such as low latency, high bandwidth and high computational power. To properly meet these requirements, orchestration must be based on multilevel observability, which means collecting data from both the application and the infrastructure levels. thus in this work we developed a platform aiming to show how multilevel observability can be implemented and how it can be used to improve automatic orchestration in cloud environments. As a case study, an application of computer vision and robotics, with very demanding requirements, was used to perform two experiments and illustrate the issues addressed in this paper. the results confirm that cloud orchestration can largely benefit from multilevel observability by allowing specific application requirements to be met, as well as improving the allocation of infrastructure resources.

关键词： Observability Measurement Monitoring Tools Cloud computing Electronic mail computer architecture

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Distributed and dynamic shared-buffer router for high-performance interconnect 17

Distributed and dynamic shared-buffer router for high-perfor...

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11th ieee/ACM international symposium on Networks-on-Chip, NOCS 2017

作者： Effiong, Charles Sassatelli, Gilles Gamatie, Abdoulaye Université de Montpellier France

ISBN: (纸本)9781450349840

Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. this design decision leads to buffer underutilization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area. © 2017 Association for computing Machinery.

关键词： Network-on-chip

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Design and Evaluation of Vivado HLS-Based Compressive Sensing for ECG Signal Analysis

Design and Evaluation of Vivado HLS-Based Compressive Sensin...

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ieee international symposium on Dependable, Autonomic and Secure computing (DASC)

作者： Oussama Kerdjidj Naeem Ramzan Abbes Amira Khalida Ghanem Fatima Chouireb Lab Telecommunications Signals and Systems University of Amar Telidji-Laghouat School of Engineering and Computing University of the West of Scotland Scotland Paisley Department of Computer Science and Engineering Qatar University Qatar Wireless Communication Telecom Centre for Development of Advanced Technologies Algeria

ISBN: (纸本)9781538675199

this paper proposes an efficient implementation of the compressed sensing technique. Specifically, we present an architecture for implementing the Matching pursuit algorithm using the Vivado high-Level Synthesis Tool. the proposed architecture consists of compressing and recovering the electrocardiogram signal on a hardware. For the healthcare application, there is an obvious need to get the algorithm implementation up and running in real-time. the proposed implementation is applied on two different blocks sizes of the input data. Our results suggest that this difference in the size of input data produces consistent performance at the speed of execution. Specifically, according to our simulation, the blocks size of 256 samples achieve the speed by 8X as compare of a block of 2000 samples. therefore, a calculation time of 2000 samples was 598ms and the computing time of 256 samples was 8.61ms and the necessary time to compute 2000 samples using a block of input 256 data was 67.2ms, which brings back to use a small vector to expect the best performance in terms of speed and area consumption. the hardware implementation results were compared with software implementation and the error between these two implementations was negligible of an order of 10 (-15) .

关键词： Matching pursuit algorithms Electrocardiography Greedy algorithms Dictionaries Tools Hardware Compressed sensing

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