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SMART: A scalable mapping and routing technique for power-gating in NoC routers 17

SMART: A scalable mapping and routing technique for power-ga...

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11th ieee/ACM international symposium on Networks-on-Chip, NOCS 2017

作者： Farrokhbakht, Hossein Kamali, Hadi Mardani Hessabi, Shaahin Department of Computer Engineering Sharif University of Technology Tehran Iran

ISBN: (纸本)9781450349840

Reducing the size of the technology increases leakage power in Network-on-Chip (NoC) routers drastically. Power-gating, particularly in NoC routers, is one of the most efficient approaches for alleviating the leakage power. Although applying power-gating techniques alleviates NoC power consumption due to high proportion of idleness in NoC routers, since the timing behavior of packets is irregular, even in low injection rates, performance overhead in power-gated routers is significant. In this paper, we present SMART, a Scalable Mapping And Routing Technique, with virtually no area overhead on the network. It improves the irregularity of the timing behavior of packets in order to mitigate leakage power and lighten the imposed performance overhead. SMART employs a special deterministic routing algorithm, which reduces number of packets encounter power-gated routers. It establishes a dedicated path between each source-destination pair to maximize using powered-on routers, which roughly halves the number of wake-ups. Additionally, in order to maximize the efficiency of the proposed routing algorithm, SMART provides an exclusive mapping for each communication task graph. In proposed mapping, all cores should be arranged with a special layout suited for the proposed routing, which helps us to minimize the number of hops. Furthermore, we modify the predictor of conventional power-gating technique to reduce energy overhead of inconsistent wake-ups. Experimental results on SPLASH-2 benchmarks indicate that the proposed technique can save 21.9% of static power, and reduce the latency overhead by 42.9% compared with the conventional power-gating technique. © 2017 Association for computing Machinery.

关键词： Network-on-chip

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2017 11th ieee/ACM international symposium on Networks-on-Chip, NOCS 2017

2017 11th IEEE/ACM International Symposium on Networks-on-Ch...

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11th ieee/ACM international symposium on Networks-on-Chip, NOCS 2017

ISBN: (纸本)9781450349840

the proceedings contain 20 papers. the topics discussed include: minimally buffered deflection routing with in-order delivery in a torus;distributed and dynamic shared-buffer router for high-performance interconnect;a novel approach to reduce packet latency increase caused by power gating in network-on-chip;improving the reliability and energy-efficiency of high-bandwidth photonic NoC architectures with multilevel signaling;energy and area efficient near field inductive coupling: a case study on 3D NoC;achieving lightweight multicast in asynchronous NoCs using a continuous-time multi-way read buffer;BiNoCHS: bimodal network-on-chip for CPU-GPU heterogeneous systems;synchoricity and NOCs could make billion gate custom hardware centric SOCs affordable;system-level design of networks-on-chip for systems-on-chip;addressing extensibility and fault tolerance in CAN-based automotive systems;JAMS: jitter-aware message scheduling for FlexRay automotive networks;hybrid automotive in-vehicle networks;fairness-oriented and location-aware NUCA for many-core SoC;on the accuracy of stochastic delay bound for network on chip;SMART: a scalable mapping and routing technique for power-gating in NoC routers;on runtime communication- and thermal-aware application mapping in 3D NoC;3D NoC-enabled heterogeneous manycore architectures for accelerating CNN training: performance and thermal trade-offs;rethinking NoCs for spatial neural network accelerators;and adaptive manycore architectures for big data computing.

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Hierarchical Distributed Coordination for Economic Dispatch

Hierarchical Distributed Coordination for Economic Dispatch

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ieee international symposium on Industrial Electronics

作者： Zhi-Wei Liu Bin Hu Xiong Hu Ming Chi Chaojie Li Zhi-Hong Guan College of Automation Huazhong University of Science and Technology Wuhan P. R. China School of Electrical and Computer Engineering RMIT University Melbourne Australia

the classical economic dispatch problem faces difficult challenges in a future smart grid with a great many distributed generators and fast power fluctuations due to high percentage of renewable energy. the traditional centralized scheme can not cope with a large number of generators, and the convergence rate of the purely distributed control decreases with the increase of the network size. A hierarchical distributed scheme based on a partition framework is proposed, in which the centralized local optimizations in regions and the distributed optimization among regions are coupled to solve the economic dispatch problem. thus the number of agents in distributed part is greatly reduced by the partition. the simulation illustrate the effectiveness and good performance of the proposed protocol.

关键词： Distributed optimization Consensus Economic dispatch Hierarchical region

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Interference-Aware Virtual Machine Placement in Cloud computing system approach based on Fuzzy Formal Concepts Analysis

Interference-Aware Virtual Machine Placement in Cloud Comput...

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ieee international Conference on Enabling Technologies

作者： Wafa Ben Slama Zaki Brahmi Mohamed Mohsen Gammoudi Higher Institute of Computer and Communication Techniques ISITCOM Hammam Sousse Mahdia Tunisia Taibah university ksa RIADI-GD Laboratory Higher Institute of Arts and Multimedia Manouba ISAMM Manouba University Manouba Tunisia

Cloud computing is a model that allows users to rent the services they want, in real time, and pay as they go. thanks to virtualization, Cloud infrastructure exploitation will be easier and smoother because it offers many benefits to data center administrators and end users. the main goal of virtualization is to share the infrastructure between users with high isolation level, and to take advantages of their physical resources as much as possible. Fault of isolation, Cloud hypervisor doesn't have a great vision on the sharing and management of resources between virtual machines, hence a contention on shared resources will take place, it identifies by performance interference. In this paper, we study the effects of performance interference between Co-located VMs, we try to grasp the VMs that does not produce a lot of performance degradation based on the fuzzy formal concepts analysis(FFCA), with the aim of proposing a new virtual machine placement approach that first minimizes performance interference and communication costs, second maximizes and balances the use of cloud resources.

关键词： Cloud computing Interference Virtualization VMs Placement Fuzzy Formal Concepts Analysis Communication Cost Quality of service (Qos)

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On runtime communication- and thermal-aware application mapping in 3D NoC 17

On runtime communication- and thermal-aware application mapp...

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11th ieee/ACM international symposium on Networks-on-Chip, NOCS 2017

作者： Li, Bing Wang, Xiaohang Singh, Amit Kumar Mak, Terrence South China University of Technology China Department of Electronics and Computer Science University of Southampton United Kingdom Shenzhen Institute of Advanced Technology and Guangzhou Institute of Advanced Technology CAS China

ISBN: (纸本)9781450349840

Many-core systems connected by 3D Network-on-Chips (NoC) are emerging as a promising computation engine for systems like cloud computing servers, big data systems, etc. Mapping applications at runtime to 3D NoCs is the key to maintain high throughput of the overall chip under a thermal/power constraint. However, the goals of optimizing both the communication latency and chip peak temperature are contradicting due to several reasons. Firstly, exploiting the vertical TSV links can accelerate communications, while low peak temperature prefers that the tasks to be mapped closer to the heat sink, instead of using the vertical links. Secondly, mapping tasks in close proximity can reduce communication latency, but at the cost of poor heat dissipation. To address these issues, in this paper, we propose an efficient runtime mapping algorithm to reduce both communication latency and overall application running time under thermal constraint. In essence, this algorithm first selects a 3D cuboid core region of a specific shape for each incoming application by setting the region's number of occupied vertical layers and its distance to the heat sink, in order to optimize its communication performance and peak temperature. Next, the exact locations of the core regions in the chip are determined, followed by a task-to-core mapping. the experimental results have confirmed that, compared to two recently proposed runtime mapping algorithms, our proposed approach can reduce the total running time by up to 48% and communication cost by up to 44%, with a low runtime overhead. © 2017 Association for computing Machinery.

关键词： Network-on-chip

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Introducing Network Multi-tenancy for Cloud-based Enterprise Resource Planning: An IoT Application

Introducing Network Multi-tenancy for Cloud-based Enterprise...

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ieee international symposium on Industrial Electronics

作者： Mayank Tiwary Sunil Kumar Pankaj Kumar Agrawal Deepak Puthal Joel J. P. C. Rodrigues Kshira Sagar Sahoo Bibhudatta Sahoo SAP Labs Bangalore India Faculty of Engineering and IT University of Technology Sydney Australia National Institute of Telecommunications (Inatel) Brazil Instituto de Telecomunicações Portugal Department of Computer Science National Institute of Technology Rourkela India

the cloud service providers make a considerable investment in setting up the data centers backbone network with the aim to maximize the network resource. However, the actual utilization of the network resources is hard to predict. With the invent of Software Defined Networking (SDN) and OpenFlow protocol, the network control layer has got the capability to communicate with the applications or services which are offered by the service provider. Moreover, a Software Defined Data center suggests resource visualization at computing, storage, and network layer. the multi-tenancy is a well-accepted architecture in cloud computing where a single instance of a software application serves multiple customers. this work is a first of its kind, which aims at maximizing the network resources with respect to multi-tenancy at the network layer. In this work, with network multitenancy, different customers IoT traffic flows are prioritized, and then network resources are allocated to the traffic flows dynamically based on the priority. We considered a scenario of Enterprise Resource Planning (ERP) solutions deployed in the cloud which offers services in the form of Software as a Service to the customers. the IoT devices deployed at the manufacturing site makes transactions on the cloud ERP. this work focuses on prioritizing the ERP-IoT traffic to meets the demands of a multi-tenant data center network. the ERP-IoT flows are prioritized using a regression based machine learning technique for predicting the response time for execution of a query caused by a traffic flow in the ERP backend server. Later, the ERP-IoT flows are assigned to multiple queues created on each network device in data center. this assignment is performed based on the traffic flow priority and Demand & Supply scores, which aims at maximizing network resource utilization. During performance evaluation, we observed that the proposed work with network multi-tenancy shows more than 10% increase in service providers u

关键词： Data centers Cloud computing Time factors Databases Resource management

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LightClockV2 - A Motivation for Teaching Scalable Digital Hardware Design

LightClockV2 - A Motivation for Teaching Scalable Digital Ha...

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ieee international symposium on Industrial Electronics

作者： Michael Rathmair Friedrich Bauer Marcus Meisel TU Wien Institute of Computer Technology Vienna Austria

Learning embedded design can be achieved with simple standard applications and microcontrollers but to spark interest in the topic, to pursue digital hardware design, motivation of students is a key factor demanding new approaches. One of which is presented in this paper as the LightClockV2, a fancy LED-based visualization gadget, built from 60 RGB color LEDs mounted on a circular PCB board to generate radial light beams. For focusing beams, we used laser pointer lenses which are mounted and adjusted in 3D printed holders. A main challenge of the project was the generation of 180 individually controllable pulse width modulation (PWM) signals. Characteristics as a 100 kHz PWM frequency, expandability for other visualization applications and a full single chip solution tighten the project requirements. In an implementation perspective a FPGA based solution efficiently provides an appropriate computational unit (finite state machine) generating light patterns, and 180 PWM peripheral modules. However, the FPGA implementation is a powerful and high-performance realization of this application and faces significant advantages in contrast to a classical microcontroller-based solution.

关键词： Pulse width modulation Light emitting diodes Hardware Clocks Microcontrollers Field programmable gate arrays Lenses

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architecture Exploration of Intelligent Robot System using ROS-compliant FPGA Component 27

Architecture Exploration of Intelligent Robot System using R...

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27th international symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Ohkawa, Takeshi Yamashina, Kazushi Matsumoto, Takuya Ootsu, Kanemitsu Yokota, Takashi Utsunomiya Univ Grad Sch Engn 7-1-2 Yoto Utsunomiya Tochigi 3218585 Japan

ISBN: (纸本)9781450345354

this paper presents a novel method for architecture exploration of an intelligent robot system while satisfying high processing performance at low power by utilizing FPGA and remote computing resources. In order to ease development complexity in the conventional architecture exploration, ROS-compliant FPGA component technology is employed. As a case study, Visual SLAM (Self Localization and Mapping) processing is studied, which is important for realizing intelligent autonomous robots. Some part of Visual SLAM processing is to be off-loaded onto a remote server outside a robot and to be processed parallel in the server. At the same time, the essential part of front-end of SLAM processing stays in the robot itself to reduce communication traffic between the robot and the remote computing resources. We have studied SLAM processing to find optimum function partitioning. In order to distribute and parallelize this processing, we explored processing architecture for trade-offs of power and performance.

关键词： FPGA robot architecture exploration ROS component-oriented development

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MPC and Energy Storage Based Frequency Regulation Strategy for Hybrid Electric Ships

MPC and Energy Storage Based Frequency Regulation Strategy f...

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ieee international symposium on Industrial Electronics

作者： S. D. G. Jayasinghe D. R. Nayanasiri A. Tashakori S. Alahakoon N. Fernando D. M. Vilathgamuwa Australian Maritime College University of Tasmania Tasmania Australia Department of Electronic and Telecommunication Engineering University of Moratuwa Sri Lanka TGTECH Melbourne Australia School of Engineering & Technology Central Queensland University Australia RMIT University Australia School of Electrical Engineering and Computer Science Queensland University of Technology Brisbane Australia

Propulsion system of a hybrid electric ship is powered by the main engine and a motor coupled to the propeller shaft via a gearbox. the motor provides a power boost when the propulsion load is high and extracts excess power working as a generator at low loading conditions. the power boost comes from the auxiliary engine which is used to supply service loads as well. When excess power is taken out from the shaft it is delivered to the ship power system requiring the auxiliary engine to reduce its power. Consequently, auxiliary engine experiences frequent changes resulting in frequency sags or swells. In extreme conditions these could result in blackouts. In addition, changes in service loads could also lead to frequency deviations causing serious power quality issues. this paper proposes a novel model predictive control (MPC) based strategy to address this issue and thereby improve the power quality. the proposed strategy uses a battery energy storage system to absorb load changes and regulate the frequency of the ship power system. the same approach is tested with the PI controllers as well for performance comparisons. Simulation results are presented to verify the efficacy of the proposed frequency regulation strategy.

关键词： Hybrid electric ship Model predictive control Frequency regulation Ship power systems Battery energy storage

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Proceedings - symposium on computer architecture and high performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

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27th ieee international symposium on computer architecture and high performance computing, SBAC-PAD 2015

ISBN: (纸本)9781467380119

the proceedings contain 26 papers. the topics discussed include: towards seismic wave modeling on heterogeneous many-core architectures using task-based runtime system;GPU-accelerated high-speed eye pupil tracking system;performance and energy efficient hardware-based scheduler for symmetric/asymmetric CMPs;analysis and optimization of engines for dynamically typed languages;progressive co-design of an architecture and compiler using a proxy application;unifying router power gating with data placement for energy-efficient NoC;fusion of calling sites;watt watcher: fine-grained power estimation for emerging workloads;performance characterization of modern databases on out-of-order CPUs;and non-stationary simulation of computer systems and dynamic performance evaluation: a concern-based approach and case study on cloud computing.

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