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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Speeding Up Stencil Computations with Kernel Convolution 28

Speeding Up Stencil Computations with Kernel Convolution

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Januario, Guilherme C. Rosenburg, Bryan S. Park, Yoonho Perrone, Michael Moreira, Jose Carvalho, Tereza C. M. B. IBM Corp TJ Watson Res Ctr Yorktown Hts NY 10598 USA Univ Sao Paulo Polytech Sch Lab Sustainabil Sao Paulo SP Brazil

ISBN: (纸本)9781509061082

A technique to speed up stencil computation is introduced. Computation and data reuse schemes are developed for its application to 1- and 3-dimensional stencils. the approach traverses the data domain fewer times than a state-of-the-art, straightforward iterative stencil implementation would. performance results are shown for a variety of platforms, exemplifying how it can be straightforwardly applied with existing techniques and frameworks. the technique, named Aggregate Stencil-Loop Iteration (ASLI), works by applying a stencil obtained by the original stencil operator convolved with itself one or more times. this more complex operator creates new opportunities for in-register data reuse and increases the FLOPs-to-load ratio. the total number of FLOPs decreases for 1D but increases for 2D and 3D star-shaped stencils. In both scenarios, speed-up relative to the state-of-the-art is achieved. ASLI is relatively easy to implement and works synergistically with existing methods to optimize stencil computations.

关键词： high-performance computing Numeric kernels optimization stencil computation

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An Image Processing VLIW architecture for Real-Time Depth Detection 28

An Image Processing VLIW Architecture for Real-Time Depth De...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Iorga, Dan Nane, Razvan Lu, Yi Van Dalen, Edwin Bertels, Koen Delft Univ Technol Comp Engn Res Grp Mekelweg 4 NL-2628 CD Delft Netherlands Intel Benelux BV High Tech Campus 83 NL-5656 AG Eindhoven Netherlands

ISBN: (纸本)9781509061082

Numerous applications for mobile devices require 3D vision capabilities, which in turn require depth detection since this enables the evaluation of an object's distance, position and shape. Despite the increasing popularity of depth detection algorithms, available solutions need expensive hardware and/or additional ASICs, which are not suitable for low-cost commodity hardware devices. In this paper, we propose a low-cost and low-power embedded solution to provide high speed depth detection. We extend an existing off-the-shelf VLIW image processor and perform algorithmic and architectural optimizations in order to achieve the requested real-time performance speed. Experimental results show that by adding different functional units and adjusting the algorithm to take full advantage of them, a 640x480 image pair with 64 disparities(1) can be processed at 36.75 fps on a single processor instance, which is an improvement of 23% compared to the best state-of-the-art image processor.

关键词： Stereo vision VLIW

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Proceedings - symposium on computer architecture and high performance computing

Proceedings - Symposium on Computer Architecture and High Pe...

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ieee 27th international symposium on computer architecture and high performance computing Workshops, SBAC-PADW 2015

ISBN: (纸本)9781467386210

the proceedings contain 20 papers. the topics discussed include: using hardware transactional memory to enable speculative trace optimization;energy consumption and scalability evaluation for software transactional memory on a real computing environment;replicating the performance evaluation of an n-body application on a manycore accelerator;characterizing anomalies of a multicore ARMv7 cluster with parallel N-body simulations;MDACCER: modified distributed assessment of the closeness CEntrality ranking in complex networks for massively parallel environments;intra-clustering: accelerating on-chip communication for data parallel architectures;Kanga: a skeleton-based generic interface for parallel programming;painless parallelism on heterogeneous hardware leveraging the functional paradigm;CHAOS-MCAPI: an optimized mechanism to support multicore parallel programming;and exploiting parallelism in linear algebra kernels through dataflow execution.

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A Cache-Coherent Heterogeneous architecture for Low Latency Real Time Applications

A Cache-Coherent Heterogeneous Architecture for Low Latency ...

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international symposium on Object-Oriented Real-Time Distributed computing

作者： Michel Gémieux Yvon Savaria Jean-Pierre David Guchuan Zhu Department of Electrical and Computer Engineering Polytechnique Montréal Canada

ISBN: (纸本)9781538615751

this paper proposes a generic hardware architecture for runtime acceleration of heterogeneous high performance computing (HPC) clusters. this runtime accelerator performs real time resource allocation and management of HPC systems with low latency on multiple time scales. One of the target applications is to perform the signal processing in wireless communication systems such as LTE and 5G over the cloud. A core part of this work is to develop and characterize algorithms that can distribute workloads to server blades in a balanced manner with the aim of maximizing processor utilization in computing clusters. Resources are also managed to guarantee bandwidth for data transfer between computing nodes and reserved cache memories to enable deterministic task execution. this paper shows how a workload distributed among several server blades can be scheduled at a finer time scale than what a normal software implementation would allow, in order to minimize the makespan required to complete execution of sets of tasks. A case study is conducted on the implementation of a resource allocator for the proposed platform. A 760-time acceleration factor of the resource allocation process has been achieved compared to a pure software implementation, while enabling data transfers at the nanosecond scale. It stands as a proof of concept that confirms the viability of CPU-FPGA platforms for wireless standards virtualization.

关键词： Field programmable gate arrays computer architecture Hardware Runtime Acceleration Resource management Software

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Designing high performance Heterogeneous Broadcast for Streaming Applications on GPU Clusters 28

Designing High Performance Heterogeneous Broadcast for Strea...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Chu, C. -H. Hamidouche, K. Subramoni, H. Venkatesh, A. Elton, B. Panda, D. K. Ohio State Univ Dept Comp Sci & Engn Columbus OH 43210 USA Engility Corp Dayton OH USA

ISBN: (纸本)9781509061082

high-performance streaming applications are beginning to leverage the compute power offered by graphics processing units (GPUs) and high network throughput offered by high performance interconnects such as InfiniBand (IB) to boost their performance and scalability. these applications rely heavily on broadcast operations to move data, which is stored in the host memory, from a single source-typically live-to multiple GPU-based computing sites. While homogeneous broadcast designs take advantage of IB hardware multicast feature to boost their performance, their heterogeneous counter-part requires an explicit data movement between Host and GPU, which significantly hurts the overall performance. there is a dearth of efficient heterogeneous broadcast designs for streaming applications especially on emerging multi-GPU configurations. In this work, we propose novel techniques to fully and conjointly take advantage of NVIDIA GPUDirect RDMA ( GDR), CUDA inter-process communication (IPC) and IB hardware multicast features to design high-performance heterogeneous broadcast operations for modern multi-GPU systems. We propose intra-node, topology-aware schemes to maximize the performance benefits while minimizing the utilization of valuable PCIe resources. Further, we optimize the communication pipeline by overlapping the GDR + IB hardware multicast operations with CUDA IPC operations. Compared to existing solutions, our designs show up to 3X improvement in the latency of a heterogeneous broadcast operation. Our designs also show up to 67% improvement in execution time of a streaming benchmark on a GPU-dense Cray CS-Storm system with 88 GPUs.

关键词： Graphics processing unit

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A Study of Power-performance Modeling using a Domain-Specific Language 28

A Study of Power-Performance Modeling using a Domain-Specifi...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Umar, Mariam Meredith, Jeremy S. Vetter, Jeffrey S. Cameron, Kirk W. Virginia Tech Dept Comp Sci Blacksburg VA 24061 USA Oak Ridge Natl Lab Oak Ridge TN 37831 USA

ISBN: (纸本)9781509061082

Energy use is now a first-class design constraint in high-performance systems and applications. Improving our understanding of application energy consumption in diverse, heterogeneous systems will be essential to efficient operation. For example, power limits in large scale parallel and distributed systems will require optimizing performance under energy constraints. However, with increased levels of parallelism, complex memory hierarchies, hardware heterogeneity, and diverse programming models and interfaces, improving performance and energy efficiency simultaneously is exceedingly difficult. Our thesis is that estimating energy use, either a priori or as soon as possible at runtime, will be essential to future systems. Such estimates must adapt with changes in applications across hardware configurations. Existing approaches offer insight and detail, but typically are too cumbersome to enable adaptation at runtime or lack portability or accuracy. To overcome these limitations, we propose two energy estimation techniques which use the Aspen domain specific language for performance modeling: ACEE (Algorithmic and Categorical Energy Estimation), a combination of analytical and empirical modeling techniques embedded in a runtime framework that leverages Aspen, and AEEM (Aspen's Embedded Energy Modeling), a system level coarse-grained energy estimation technique that uses performance modeling from Aspen to generate energy estimations at runtime. this paper presents methodology of the models and examines their accuracy as well as their advantages and challenges in several use cases.

关键词： Domain specific language Energy estimation high-performance computing performance modeling

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Using Balanced Data Placement to Address I/O Contention in Production Environments 28

Using Balanced Data Placement to Address I/O Contention in P...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Neuwirth, Sarah Wang, Feiyi Oral, Sarp Vazhkudai, Sudharshan Rogers, James H. Bruening, Ulrich Heidelberg Univ Inst Comp Engn D-69115 Heidelberg Germany Oak Ridge Natl Lab Natl Ctr Computat Sci Oak Ridge TN USA

ISBN: (纸本)9781509061082

Designed for capacity and capability, HPC I/O systems are inherently complex and shared among multiple, concurrent jobs competing for resources. Lack of centralized coordination and control often render the end-to-end I/O paths vulnerable to load imbalance and contention. With the emergence of data-intensive HPC applications, storage systems are further contended for performance and scalability. this paper proposes to unify two key approaches to tackle the imbalanced use of I/O resources and to achieve an end-to-end I/O performance improvement in the most transparent way. First, it utilizes a topology-aware, Balanced Placement I/O method (BPIO) for mitigating resource contention. Second, it takes advantage of the platform-neutral ADIOS middle-ware, which provides a flexible I/O mechanism for scientific applications. By integrating BPIO with ADIOS, referred to as Aequilibro, we obtain an end-to-end and per job I/O performance improvement for ADIOS-enabled HPC applications without requiring any code changes. Aequilibro can be applied to almost any HPC platform and is mostly suitable for systems that lack a centralized file system resource manager. We demonstrate the effectiveness of our integration on the Titan system at the Oak Ridge National Laboratory. Our experiments with a synthetic benchmark and real-world HPC workload show that, even in a noisy production environment, Aequilibro can improve large-scale application performance significantly.

关键词： Parallel File System high performance computing Load Balancing performance Evaluation

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Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

Evaluating Fast Algorithms for Convolutional Neural Networks...

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Annual ieee symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Liqiang Lu Yun Liang Qingcheng Xiao Shengen Yan Center for Energy-efficient Computing and Applications Peking University Beijing China Sense Time Group Limited Department of Information Engineering The Chinese University of Hong Kong

In recent years, Convolutional Neural Networks (CNNs) have become widely adopted for computer vision tasks. FPGAs have been adequately explored as a promising hardware accelerator for CNNs due to its high performance, energy efficiency, and reconfigurability. However, prior FPGA solutions based on the conventional convolutional algorithm is often bounded by the computational capability of FPGAs (e.g., the number of DSPs). In this paper, we demonstrate that fast Winograd algorithm can dramatically reduce the arithmetic complexity, and improve the performance of CNNs on FPGAs. We first propose a novel architecture for implementing Winograd algorithm on FPGAs. Our design employs line buffer structure to effectively reuse the feature map data among different tiles. We also effectively pipeline the Winograd PE engine and initiate multiple PEs through parallelization. Meanwhile, there exists a complex design space to explore. We propose an analytical model to predict the resource usage and reason about the performance. then, we use the model to guide a fast design space exploration. Experiments using the state-of-the-art CNNs demonstrate the best performance and energy efficiency on FPGAs. We achieve an average 1006.4 GOP/s for the convolutional layers and 854.6 GOP/s for the overall AlexNet and an average 3044.7 GOP/s for the convolutional layers and 2940.7 GOP/s for the overall VGG16 on Xilinx ZCU102 platform.

关键词： Field programmable gate arrays Algorithm design and analysis Convolution Space exploration computer architecture Prediction algorithms Engines

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Approximate Lock: Trading off Accuracy for performance by Skipping Critical Sections 27

Approximate Lock: Trading off Accuracy for Performance by Sk...

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27th ieee international symposium on Software Reliability Engineering (ISSRE)

作者： Akram, Riad ul Alam, Mohammad Mejbah Muzahid, Abdullah Univ Texas San Antonio San Antonio TX 78249 USA

ISBN: (纸本)9781467390026

Approximate computing is gaining a lot of traction due to its potential for improving performance and consequently, energy efficiency. this project explores the potential for approximating locks. We start out with the observation that many applications can tolerate occasional skipping of computations done inside a critical section protected by a lock. this means that for certain critical sections, when the enclosed computation is occasionally skipped, the application suffers from quality degradation in the final outcome but it never crashes/deadlocks. To exploit this opportunity, we propose Approximate Lock (ALock). the thread executing ALock checks if a certain condition (e.g., high contention, long waiting time) is met and if so, the thread returns without acquiring the lock. We modify some selected critical sections using ALock so that those sections are skipped when ALock returns without acquiring the lock. We experimented with 14 programs from PARSEC, SPLASH2, and STAMP benchmarks. We found a total of 37 locks that can be transformed into ALock. ALock provides performance improvement for 10 applications, ranging from 1.8% to 164.4%, with at least 80% accuracy.

关键词： Multithreaded program Lock Approximate computing Accuracy performance

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A Study of Failures in Community Clusters: the Case of Conte 27

A Study of Failures in Community Clusters: The Case of Conte

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27th ieee international symposium on Software Reliability Engineering (ISSRE)

作者： Mitra, Subrata Javagal, Suhas Maji, Amiya Gamblin, Todd Moody, Adam Harrell, Stephen Bagchi, Saurabh Purdue Univ W Lafayette IN 47907 USA Lawrence Livermore Natl Lab Livermore CA USA

ISBN: (纸本)9781509036011

Large community clusters are becoming increasingly common in universities and other organizations due to the benefits they provide to the researchers in terms of operational costs and resource availability. However, efficient administration, failure diagnosis, and performance debugging on community clusters are challenging tasks due to the sheer diversity of workloads and users. these clusters are typically shared by users coming from various scientific domains and experience levels. Many users have little experience in computing and, hence, often face performance issues-leading to resource wastage. In this paper, we study these dynamics in one of the largest university-wide community clusters (Conte at Purdue University). We perform in-depth analysis of library and application usage patterns, job failures and performance issues. Further, we introduce a set of novel analysis techniques that can be used to identify hidden trends and diagnose job failures in compute clusters in general. We provide concrete recommendations for the cluster administrators and present case studies highlighting how such information can be used to proactively solve many user issues, ultimately leading to better quality of service.

关键词： Application workload computing cluster high-performance computing Public repository

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