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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Proceedings - 2016 ieee 15th international symposium on Network computing and Applications, NCA 2016

Proceedings - 2016 IEEE 15th International Symposium on Netw...

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15th ieee international symposium on Network computing and Applications, NCA 2016

ISBN: (纸本)9781509032167

the proceedings contain 65 papers. the topics discussed include: crowdsourcing-based architecture for post-disaster geolocation: a comparative performance evaluation;GeoTrie: a scalable architecture for location-temporal range queries over massive geotagged data sets;characterizing GPS outages: geodesic dead reckoning solution for VANETs and ITS;contextual geotracking service of incident markers in disaster search-and-rescue operations;a user level approach to schedule BoT applications on private clouds;heterogeneous resource allocation in cloud management;leveraging an homomorphic encryption library to implement a coordination service;and multi-phase proactive cloud scheduling framework based on high level workflow and resource characterization.

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A Benchmark on Multi Improvement Neighborhood Search Strategies in CPU/GPU Systems 28

A Benchmark on Multi Improvement Neighborhood Search Strateg...

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28th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rios, Eyder Coelho, Igor M. Ochi, Luiz Satoru Boeres, Cristina Farias, Ricardo UESPI BR-64202220 Parnaiba PI Brazil Univ Estado Rio De Janeiro Dept Comp BR-20550900 Rio De Janeiro RJ Brazil Univ Fed Fluminense Inst Comp BR-24210346 Niteroi RJ Brazil Univ Fed Rio de Janeiro COPPE Sistemas BR-21941914 Rio de Janeiro RJ Brazil

ISBN: (纸本)9781509048441

In combinatorial optimization problems, the neighborhood search (NS) is a fundamental component for local search based heuristics. It consists of selecting a solution from a high cardinality set of neighbor solutions, by means of operations called moves. To perform this search, NS algorithms usually adopt two main approaches: selecting the first or best improving move. the Multi Improvement (MI) strategy is a recently proposed method that consists in exploring simultaneously multiple move operations during the NS phase aiming to reach good quality solutions with shorter computational steps. this paper presents a benchmark for MI strategies in hybrid CPU/GPU systems. this technique efficiently explores the CPU processing power together with the massive parallelism achieved by modern GPUs, emerging as an efficient alternative for classic CPU neighborhood search strategies. the advantage of this approach depends heavily on finding the best tradeoff between CPU and GPU processing, as well as minimizing the memory transfers involved in the process. In the experiments, several MI configurations were tested in a hybrid CPU/GPU environment presenting better results than classical neighborhood search strategies for the Minimum Latency Problem, a hard combinatorial optimization problem.

关键词： GPU computing Local Search Multi Improvement Minimum Latency Problem

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Stochastic Modeling of Hybrid Cache Systems 24

Stochastic Modeling of Hybrid Cache Systems

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24th ieee international symposium on Modeling, Analysis and Simulation of computer and Telecommunication Systems (MASCOTS)

作者： Ju, Gaoying Li, Yongkun Xu, Yinlong Chen, Jiqiang Lui, John C. S. Univ Sci & Technol China Sch Comp Sci & Technol Hefei Peoples R China Natl Univ Def Technol Collaborat Innovat Ctr High Performance Comp Changsha Hunan Peoples R China AnHui Prov Key Lab High Performance Comp Hefei Peoples R China Chinese Univ Hong Kong Dept Comp Sci & Engn Hong Kong Hong Kong Peoples R China

ISBN: (纸本)9781509034321

In recent years, there is an increasing demand of big memory systems so to perform large scale data analytics. Since DRAM memories are expensive, some researchers are suggesting to use other memory systems such as non-volatile memory (NVM) technology to build large-memory computing systems. However, whether the NVM technology can be a viable alternative (either economically and technically) to DRAM remains an open question. To answer this question, it is important to consider how to design a memory system from a "system perspective", that is, incorporating different performance characteristics and price ratios from hybrid memory devices. this paper presents an analytical model of a "hybrid page cache system" so to understand the diverse design space and performance impact of a hybrid cache system. We consider (1) various architectural choices, (2) design strategies, and (3) configuration of different memory devices. Using this model, we provide guidelines on how to design hybrid page cache to reach a good trade-off between high system throughput (in I/O per sec or IOPS) and fast cache reactivity which is defined by the time to fill the cache. We also show how one can configure the DRAM capacity and NVM capacity under a fixed budget. We pick PCM as an example for NVM and conduct numerical analysis. Our analysis indicates that incorporating PCM in a page cache system significantly improves the system performance, and it also shows larger benefit to allocate more PCM in page cache in some cases. Besides, for the common setting of performance-price ratio of PCM, "flat architecture" offers as a better choice, but "layered architecture" outperforms if PCM write performance can be significantly improved in the future.

关键词： Stochastic Model Mean-field Analysis Hybrid Cache Systems

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Petascale Local Time Stepping for the ADER-DG Finite Element Method 30

Petascale Local Time Stepping for the ADER-DG Finite Element...

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30th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Breuer, Alexander Heinecke, Alexander Bader, Michael Univ Calif San Diego 9500 Gilman Dr La Jolla CA 92093 USA Intel Corp 2200 Mission Coll Blvd Santa Clara CA 95054 USA Tech Univ Munich Boltzmannstr 3 D-85748 Garching Germany

ISBN: (纸本)9781509021406

In this work we present a clustered local time stepping (LTS) scheme for the arbitrary high-order derivatives discontinuous Galerkin finite element scheme. By clustering elements of similar time step, our scheme meets regularity requirements of modern hardware through the design of the numerical discretization. We present a detailed description of our clustered local time stepping scheme for the seismic simulation package SeisSol. Our scheme is able to capture homogeneous and heterogeneous time step variations in the computational domain and maintains a large fraction of the theoretical speedup offered by LTS. From an engineering standpoint, our scheme addresses all important performance characteristics of state-of-the-art supercomputers. the combined algorithmic and computational performance results for SeisSol show that we are able to leverage the large potential of local time stepping by reducing time-to-solution by several factors (2.3-4.1), sustaining more than 53% of SuperMUC-II's HPL performance, what corresponds to more than 1.5 PFLOPS performance on 86,016 cores.

关键词： FEM ADER-DG local time stepping parallel alogithms high-performance computing hardware-aware algorithms

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high-throughput and Energy-efficient Graph Processing on FPGA 24

High-throughput and Energy-efficient Graph Processing on FPG...

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24th ieee international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Zhou, Shijie Chelmis, Charalampos Prasanna, Viktor K. Univ Southern Calif Ming Hsieh Dept Elect Engn Los Angeles CA 90007 USA

ISBN: (纸本)9781509023561

In this paper, we propose a novel design for large-scale graph processing on FPGA. Our design uses large external memory for storing massive graph data and FPGA for acceleration, and leverages edge-centric computing principles. We propose a data layout which optimizes the external memory performance and leads to an efficient memory activation schedule to reduce on-chip memory power consumption. Further, we develop a parallel architecture on FPGA which can saturate the external memory bandwidth and concurrently process multiple input data to increase throughput. We use our design to accelerate several classic graph algorithms, including single-source shortest path, weakly connected component, and minimum spanning tree. Experimental results show that for all the considered graph algorithms, our design achieves high throughput of over 600 million traversed edges per second (MTEPS) and high energy-efficiency of over 30 MTEPS/W. Compared with a baseline design, our optimizations result in over 3.6x throughput and 5.8x energy-efficiency improvements, respectively. Our design achieves 32% throughput improvement when compared with state-of-the-art FPGA designs, and up to 7.8x speedup when compared with state-of-the-art multi-core implementation.

关键词： Field programmable gate arrays (FPGA)

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EEGu2: An Embedded Device for Brain/Body Signal Acquisition and Processing 27

EEGu2: An Embedded Device for Brain/Body Signal Acquisition ...

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27th international symposium on Rapid System Prototyping (RSP) - Shortening the Path from Specification to Prototype

作者： Feng, Shen Tang, Mian Quivira, Fernando Dyson, Tim Cuckov, Filip Schirner, Gunar Northeastern Univ Boston MA 02115 USA Univ Massachusetts Boston MA 02125 USA

ISBN: (纸本)9781450345354

Brain/Body computer Interface (BBCI) technology facilitates research in human cognition and assistive technologies. BBCI acquires and analyzes physiological signals from human body/brain such as electroencephalography (EEG) to observe human physiological states and potentially enable external control. BBCI devices require accurate data acquisition systems with sufficient dynamic range for various brain/body signals. Also, embedded processing is desirable for real-time interaction and flexible deployment. However, most off-the-shelf BBCI devices are very costly, e.g. g. USBamp at $ 15K and do not offer embedded processing. Hence, an open embedded device for BBCI acquisition and processing is needed to foster the BBCI research. this paper proposes EEGu2 as a portable embedded BBCI device. Based on a BeagleBone Black (BBB), EEGu2 integrates a custom-designed cape including 2 PCBs: an acquisition board for 16-channel 24-bit acquisition up to 1KHz sampling frequency and a power board for wall charging and powering mobile operations. EEGu2 measurement shows a high acquisition accuracy with 25dB signal-to-noise ratio and 0.785 mu V peak-to-peak input referred noise. At maximum performance, the cape consumes 101.2 mW while BBB consumes 1850 mW. With two lithium batteries, EEGu2 operates independently 12 hours. We demonstrate the flexibility and portability of EEGu2 in the context of Human-in-the-Loop Cyber-Physical Systems (HiLCPS) that augments human interaction with physical world through BBCI. the EEGu2 firmware is integrated into the HiLCPS Framework to enable the location transparent access via the MATLAB interface. EEGu2 empowers rapid embedded BBCI application deployment and we show the flexibility of EEGu2 with a BCI Speller application that acquires real-time EEG signals and infers the user spelling based on Steady State Visually Evoked Potential.

关键词： Data Acquisition System Body/Brain-computer Interfaces EEG Embedded Real-time Hardware Abstraction Automated Embedded Deployment Domain-Specific Synthesis

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Self-Adaptive Service Driven architecture for Intelligent Transport System 19

Self-Adaptive Service Driven Architecture for Intelligent Tr...

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第十五届分布式计算及其应用国际学术研讨会

作者： Nauman Ahmad Khan Vesna Brujic-Okretic Souheil Khaddaj

ISBN: (纸本)9781509035946

Modern transport systems rely on an increasing number of sensors to control their operation including orientation,speed,arrival and departure times,fuel consumption,passenger count *** have become important parts of the echo system with their availability and performance playing a key role in daily ***,they produce data in high volume and frequency that need to be processed fast enough so that it can be shared across the network in *** system architectures have been unable to meet transport systems quality requirements scuh as scalability,adaptability,sustainability,extendibility and high ***,in this work,we propose a novel architecture to acquire,store,manipulate and integrate information from heterogeneous data sources to produce a reliable *** will help transport managers and bus companies to optimize,in real-time,scheduling,stops usage and passenger's time.

关键词： Real-time systems computer architecture Reliability Intelligent sensors Systems architecture Roads

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LCC-Graph: A high-performance Graph-Processing Framework with Low Communication Costs 24

LCC-Graph: A High-Performance Graph-Processing Framework wit...

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24th ieee/ACM international symposium on Quality of Service (IWQoS)

作者： Cheng, Yongli Wang, Fang Jiang, Hong Hua, Yu Feng, Dan Wang, Xiuneng Wuhan Natl Lab Optoelect Wuhan Peoples R China Huazhong Univ Sci & Technol Sch Comp Wuhan Peoples R China Univ Texas Arlington Dept Comp Sci & Engn Arlington TX 76019 USA

ISBN: (纸本)9781509026340

With the rapid growth of data, communication overhead has become an important concern in applications of data centers and cloud computing. However, existing distributed graph-processing frameworks routinely suffer from high communication costs, leading to very long waiting times experienced by users for the graph-computing results. In order to address this problem, we propose a new computation model with low communication costs, called LCC-BSP. We use this model to design and implement a high-performance distributed graph-processing framework called LCC-Graph. this framework eliminates the high communication costs in existing distributed graph-processing frameworks. Moreover, LCC-Graph also minimizes the computation workload of each vertex, significantly reducing the computation time for each superstep. Evaluation of LCC-Graph on a 32-node cluster, driven by real-world graph datasets, shows that it significantly outperforms existing distributed graph-processing frameworks in terms of runtime, particularly when the system is supported by a high-bandwidth network. For example, LCC-Graph achieves an order of magnitude performance improvement over GPS and GraphLab.

关键词： Costs

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Microservices architecture based Cloudware Deployment Platform for Service computing

Microservices Architecture based Cloudware Deployment Platfo...

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10th ieee international symposium on Service-Oriented System Engineering (ieee SOSE)

作者： Guo, Dong Wang, Wei Zeng, Guosun Wei, Zerong Tongji Univ Dept Comp Sci & Technol Shanghai 200092 Peoples R China Natl Engn & Technol Ctr High Performance Tongji Branch Shanghai 200092 Peoples R China Tongji Univ Minist Educ Key Lab Embedded Syst & Serv Comp Shanghai 200092 Peoples R China

ISBN: (纸本)9781509022533

With the rising of Cloud computing, evolution have occurred not only in datacenter, but also in software development, deployment, maintain and usage. How to build cloud platform for traditional software, and how to deliver cloud service to users are central research fields which will have a huge impact. In recent years, the development of microservice and container technology make software paradigm evolve towards Cloudware in cloud environment. Cloudware, which is based on service and supported by cloud platform, is an important method to cloudalize traditional software. It is also a significant way for software development, deployment, maintenance and usage in future cloud environment. Furthermore, it creates a completely new thought for software in cloud platform. In this paper, we proposed a new Cloudware PaaS platform based on microservice architecture and light weighted container technology. We can directly deploy traditional software which provides services to users by browser in this platform without any modification. By utilizing the microservice architecture, this platform has the characteristics of scalability, auto-deployment, disaster recovery and elastic configuration.

关键词： Cloud computing Cloudware Container Micro service PaaS

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high performance Pattern Matching using the Automata Processor 30

High Performance Pattern Matching using the Automata Process...

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30th ieee international Parallel and Distributed Processing symposium (IPDPS)

作者： Roy, Indranil Srivastava, Ankit Nourian, Marziyeh Becchi, Michela Aluru, Srinivas Georgia Inst Technol Sch Computat Sci & Engn Atlanta GA 30332 USA Univ Missouri Dept Elect & Comp Engn Columbia MO 65211 USA

ISBN: (纸本)9781509021406

In this paper, we study the acceleration of applications that require searching for all occurrences of thousands of string-patterns in an input data-stream, using the Automata Processor (AP). For this purpose, we use two applications from two fields, namely, network security and bioinformatics. the first application, called Fast-SNAP (for Fast-SNort using AP), scans network data for 4312 signatures of intrusion derived from the popular open-source Snort database. Using the resources of a single AP board, Fast-SNAP can scan for all these signatures at 10.3 Gbps. the second application, called PROTOMATA (for PROTein autOMATA), looks for all occurrences of 1308 protein motifs from the PROSITE database in protein sequences. PROTOMATA is up to half a million times faster than its single-CPU-based counterpart. the techniques developed to program these applications may be useful in the design and development of similar applications using this new hardware accelerator.

关键词： Finite Automata Regular Expressions Automata Processor FPGAs Intrusion detection Protein motifs

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