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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Graph Templates for Dataflow Programming 27

Graph Templates for Dataflow Programming

引用

ieee 27th international symposium on computer architecture and high performance computing

作者： Sena, Alexandre C. Vaz, Eduardo S. Franca, Felipe M. G. Marzulo, Leandro A. J. Alves, Tiago A. O. Univ Estado Rio de Janeiro Inst Matemat & Estat Dept Informat & Ciencia Comp Rio De Janeiro Brazil Univ Fed Rio de Janeiro COPPE Programa Engn Sistemas & Comp Rio De Janeiro Brazil FlatLabs Rio De Janeiro Brazil

ISBN: (纸本)9781467386210

Current works on parallel programming models are trending towards the dataflow paradigm, which naturally exploits parallelism in programs. the Sucuri Python Library provides basic features for creation and execution of dataflow graphs in parallel environments. However, there is still a gap between dataflow programming and traditional parallel programming. In this paper we aim at narrowing that gap by introducing a set of templates for Sucuri that represent some of the most important parallel programming patterns. through these templates programmers can implement applications that use patterns such as fork/join, pipeline and wavefront just by instantiating and connecting sub-graph objects. Evaluation showed that the use of templates makes programming easier, while allowing a significant reduction in lines of code, compared to manually creating the dataflow graph.

关键词： Dataflow high performance computing Parallel Programming Templates

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high-level service connectors for component-based high performance computing

High-level service connectors for component-based high perfo...

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19th international symposium on computer architecture and high performance computing

作者： de Carvalho-Junior, Francisco Heron Correa, Ricardo Cordeiro Araujo, Gisele Azevedo Silva, Jefferson Carvalho Lins, Rafael Duelre Univ Fed Ceara Dept Comp Fortaleza Ceara Brazil Univ Fed Pernambuco Dept Elect Sistemas Recife PE Brazil

ISBN: (纸本)9780769530147

Component-based programming has been applied to address the requirements of applications in high performance computing (HPC). the usual service connectors of commercial component models do not fit some requirements of HPC, mainly regarding the support of parallelism, however this paper looks at extensions to the usual notion of service connector to meet such requirements, using the # component model as a substratum, evidencing its expressiveness.

关键词： computer programming

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Energy Consumption and Scalability Evaluation for Software Transactional Memory on a Real computing Environment 27

Energy Consumption and Scalability Evaluation for Software T...

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ieee 27th international symposium on computer architecture and high performance computing

作者： Rico, Timoteo M. Pilla, Mauricio L. Du Bois, Andre R. Duarte, Rodrigo M. Univ Fed Pelotas PPGC CDTEC Pelotas RS Brazil

ISBN: (纸本)9781467386210

Transactional Memory is a concurrent programming abstraction that overcomes several of the limitations found in traditional synchronization mechanisms. As it is a more recent abstraction, little is known about energy consumption of Software Transactional Memories (STM). In this context, this work presents an analysis and characterization of energy consumption and performance of four Transactional Memory libraries: TL2, TinySTM, SwissTM, and AdaptSTM, using the STAMP benchmarks. Although most works in the state-of-the-art chose to evaluate Transactional Memories through simulation, in this work the benchmarks are run in actual computers, avoiding the known issues with modeling power consumption in simulators. Our results show that SwissTM is the most efficient library of the four in terms of energy consumption and performance for the default configurations, followed by AdaptSTM, TinySTM, and TL2, for most of the execution scenarios and 8 threads at most. STM's scalability is directly tied to the strategies for detection and resolution of conflicts. In this perspective, AdaptSTM is the best STM for applications with short transactions, SwissTM presents the best results for medium transactions, and long transactions with medium/high contention are best handled by TL2. On the other hand, TinySTM shows the worst scalability for most scenarios, but with good results for applications with very small abort rates.

关键词： Software transactional memory transactional memory green computing

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Instruction path coprocessors 00

Instruction path coprocessors

引用

27th international symposium on computer architecture

作者： Chou, Y Shen, JP Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)1581132328

this paper presents the concept of an Instruction Path Coprocessor (I-COP), which is a programmable on-chip coprocessor, with its own mini-instruction set, that operates on the core processor's instructions to transform them into an internal format that can be more efficiently executed. It is located off the critical path of the core processor to ensure that it does not negatively impact the core processor's cycle time or pipeline depth. An I-COP is highly versatile and can be used to implement different types of instruction transformations to enhance the IPC of the core processor. We study four potential applications of the I-COP to demonstrate the feasibility of this concept and investigate the design issues of such a coprocessor: A prototype instruction set for the I-COP is presented along with an implementation framework that facilitates achieving high I-COP performance. Initial results indicate that the I-COP is able to efficiently implement the trace cache fill unit as well as the register move, stride data prefetching and linked data structure prefetching trace optimizations.

关键词： computer architecture

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Minimizing branch misprediction penalties for superpipelined processors 27

Minimizing branch misprediction penalties for superpipelined...

引用

27th Annual international symposium on Microarchitecture, MICRO 1994

作者： Su, Ching-Long Despain, Alvin M. Advanced Computer Architecture Laboratory University of Southern California United States

ISBN: (纸本)0897917073

Branch misprediction penalties depend on branch misprediction rates and branch penalties. Dynamic branch schemes take advantage of hardware to record and predict branch behavior at run-time for reducing branch misprediction rates. Static branch schemes take advantage of scheduling safe instructions into branch delay slots at compile-time for reducing branch penalties. this paper evaluates and compares the performance of various stateof-the-art static and dynamic branch schemes for superpipelined processors. © 1994 ACM.

关键词： Delay Runtime Permission Program processors Pipelines Hardware Processor scheduling Distributed computing Machinery CMOS technology

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T2S-Tensor: Productively Generating high-performance Spatial Hardware for Dense Tensor Computations 27

T2S-Tensor: Productively Generating High-Performance Spatial...

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27th ieee Annual international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Srivastava, Nitish Rong, Hongbo Barua, Prithayan Feng, Guanyu Cao, Huanqi Zhang, Zhiru Albonesi, David Sarkar, Vivek Chen, Wenguang Petersen, Paul Lowney, Geoff Herr, Adam Hughes, Christopher Mattson, Timothy Dubey, Pradeep Cornell Univ Ithaca NY 14853 USA Intel Santa Clara CA USA Georgia Inst Technol Atlanta GA 30332 USA Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9781728111315

We present a language and compilation framework for productively generating high-performance systolic arrays for dense tensor kernels on spatial architectures, including FPGAs and CGRAs. It decouples a functional specification from a spatial mapping, allowing programmers to quickly explore various spatial optimizations for the same function. the actual implementation of these optimizations is left to a compiler. thus, productivity and performance are achieved at the same time. We used this framework to implement several important dense tensor kernels. We implemented dense matrix multiply for an Arria-10 FPGA and a research CGRA, achieving 88% and 92% of the performance of manually written, and highly optimized expert ("ninja") implementations in just 3% of their engineering time. three other tensor kernels, including MTTKRP, TTM and TTMc, were also implemented with high performance and low design effort, and for the first time on spatial architectures.

关键词： Optimization computer architecture Kernel Field programmable gate arrays Programming Hardware

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Towards a workflow-aware distributed versioning file system for metacomputing systems 05

Towards a workflow-aware distributed versioning file system ...

引用

14th ieee international symposium on high performance Distributed computing

作者： Wang, Y Univ Alberta Dept Comp Sci Edmonton AB T6G 2M7 Canada

ISBN: (纸本)0780390377

In this paper, a novel workflow-aware distributed versioning file system, WAD-VFS is presented to overcome the shortcoming of traditional DFS and facilitate the high performance computing. Our preliminary simulation results are impressive and can hence serve as a supporting evidence of deploying WAD-VFS to our ongoing metacomputing project, Trellis system.

关键词： File systems Metacomputing Distributed computing Processor scheduling Backplanes Target tracking Tree data structures Concrete computer applications computer architecture

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Infrastructure, requirements and applications for e-Science 14

Infrastructure, requirements and applications for e-Science

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14th symposium on computer architecture and high performance computing

作者： Perrott, R Queens Univ Belfast Sch Comp Sci Belfast Antrim North Ireland

Recent developments in the international arena has meant the technology is now mature enough to bring together those required for the implementation of a grid computing facility. this paper examines the requirements a... 详细信息

ISBN: (纸本)0769517722

关键词： grid computing distributed and parallel computing eScience

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A metascheduler for the Grid 11

A metascheduler for the Grid

引用

11th ieee international symposium on high performance Distributed computing (HPDC-11)

作者： Vadhiyar, SS Dongarra, JJ Univ Tennessee Comp Sci Dept Knoxville TN 37996 USA

ISBN: (纸本)0769516866

With the advent of Grid computing, scheduling strategies for distributed heterogeneous systems have either become irrelevant or have to be extended significantly to support Grid dynamics. In this paper, we describe a metascheduling architecture for a Grid system that takes into account both the application and system level considerations. Results are presented to demonstrate the usefulness of the metascheduler.

关键词： computer architecture computer science Contracts Distributed computing Dynamic scheduling Grid computing Libraries Lifting equipment Mars Processor scheduling

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Customizable Heterogeneous Acceleration for Tomorrow's high-performance computing 17

Customizable Heterogeneous Acceleration for Tomorrow's High-...

引用

2015 ieee 17th international Conference on high performance computing and Communications (HPCC)

作者： Cilardo, Alessandro Flich, Jose Gagliardi, Mirko Gavila, Rafael T. Univ Naples Federico II DIETI Naples Italy Univ Politecn Valencia GAP Valencia Spain

ISBN: (纸本)9781479989379

high-performance computing as we know it today is experiencing unprecedented changes, encompassing all levels from technology to use cases. this paper explores the adoption of customizable, deeply heterogeneous manycore systems for future QoS-sensitive and power-efficient high-performance computing. At the heart of the proposed architecture is a NoC-based manycore system embracing medium-end CPUs, GPU-like processors, and reconfigurable hardware regions. the paper discusses the high-level design principles inspiring this innovative architecture as well as the key role that heterogeneous acceleration, ranging from multicore processors and GPUs down to FPGAs, might play for tomorrow's high-performance computing.

关键词： field programmable gate arrays graphics processing units multiprocessing systems network-on-chip parallel processing power aware computing quality of service FPGA GPU-like processors NoC-based many-core system QoS-sensitive computing customizable heterogeneous acceleration heterogeneous acceleration heterogeneous manycore systems high-level design principles high-performance computing innovative architecture medium-end CPU multicore processors power-efficient high-performance computing reconfigurable hardware regions Acceleration computer architecture Field programmable gate arrays Hardware Program processors Quality of service Registers Field programmable gate arrays high performance computing Quality of service power aware computing Program processors Multiprocessing systems network-on-chip computer architecture Registers acceleration PARALLEL PROCESSING (computerS) Multi-core processors computer hardware Graphics Processing Unit

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