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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Proceedings - 2022 ieee 27th Pacific Rim international symposium on Dependable computing, PRDC 2022

Proceedings - 2022 IEEE 27th Pacific Rim International Sympo...

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27th ieee Pacific Rim international symposium on Dependable computing, PRDC 2022

ISBN: (纸本)9781665485555

the proceedings contain 30 papers. the topics discussed include: safe rust code recommendation based on Siamese graph neural network;modeling and evaluating the effects of jamming attacks on connected automated road vehicles;tracing processing of service requests in cloud environments;how data diversification benefits the reliability of three-version image classification systems;automating safety argument change impact analysis for machine learning components;characterizing deep learning neural network failures between algorithmic inaccuracy and transient hardware faults;enhanced software development process for CubeSats to cope with space radiation faults;a heterogeneous redundant architecture for industrial control system security;random bad state estimator to address false data injection in critical infrastructures;towards a dependable energy market: proof of authority in a blockchain-based peer-to-peer microgrid;and performance and security evaluation of a moving target defense based on a software-defined networking environment.

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Edge computing versus Cloud computing: Impact on Retinal Image Pre-processing 34

Edge Computing versus Cloud Computing: Impact on Retinal Ima...

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34th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Kunas, Cristiano A. Pinto, Dayla R. Granville, Lisandro Z. Serpa, Matheus S. Padoin, Edson L. Navaux, Philippe O. A. Fed Univ Rio Grande do Sul UFRGS Inst Informat Porto Alegre RS Brazil Reg Univ Northwestern Rio Grande do Sul UNIJUI Ijui Brazil

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

With the emergence of new intelligent applications, there has been a revolution in information management, mainly including processing routines, storage, and computing capacity. Cloud computing is one of the most well-known and popular paradigms. However, there are still some barriers to cloud adoption. Edge computing serves as a decentralized extension and provides solutions that facilitate data processing at the generation source. this paper discusses the development of a retinal image pre-processing application for efficient use in screening systems and the impact that pre-processing has on network interconnection. Results show that the parallel version has reduced application execution time by up to approximate to 73%, decreasing by approximate to 11.5x the bandwidth used, achieving throughput above 5 images/second with Edge pre-processing, 2.57x higher than Cloud.

关键词： high-performance computing edge cloud pre-processing diabetic retinopathy

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QuCloud: A New Qubit Mapping Mechanism for Multi-programming Quantum computing in Cloud Environment 27

QuCloud: A New Qubit Mapping Mechanism for Multi-programming...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Liu, Lei Dou, Xinglei Chinese Acad Sci Sys Inventor Lab ICT SKLCA Beijing Peoples R China

ISBN: (纸本)9781665422352

For a specific quantum chip, multi-programming improves overall throughput and resource utilization. Previous studies on mapping multiple programs often lead to resource under-utilization, high error rate, and low fidelity. this paper proposes QuCloud, a new approach for mapping quantum programs in the cloud environment. We have three new designs in QuCloud. (1) We leverage the community detection technique to partition physical qubits among concurrent quantum programs, avoiding the waste of robust resources. (2) We design X-SWAP scheme that enables inter-program SWAPs and prioritizes SWAPs associated with critical gates to reduce the SWAP overheads. (3) We propose a compilation task scheduler that schedules concurrent quantum programs to be compiled and executed based on estimated fidelity for the best practice. We evaluate our work on publicly available quantum computer IBMQ16 and a simulated quantum chip IBMQ50. Our work outperforms the state-of-the-art work for multi-programming on fidelity and compilation overheads by 9.7% and 11.6%, respectively.

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Nimblock: Scheduling for Fine-grained FPGA Sharing through Virtualization 23

Nimblock: Scheduling for Fine-grained FPGA Sharing through V...

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50th Annual international symposium on computer architecture (ISCA)

作者： Mandava, Meghna Reckamp, Paul Chen, Deming Univ Illinois Urbana IL 61801 USA

ISBN: (纸本)9798400700958

As FPGAs become ubiquitous compute platforms, existing research has focused on enabling virtualization features to facilitate fine-grained FPGA sharing. We employ an overlay architecture which enables arbitrary, independent user logic to share portions of a single FPGA by dividing the FPGA into independently reconfigurable slots. We then explore scheduling possibilities to effectively time- and space-multiplex the virtualized FPGA by introducing Nimblock. the Nimblock scheduling algorithm balances application priorities and performance degradation to improve response time and reduce deadline violations. Unlike other algorithms, Nimblock explores pre-emption as a scheduling parameter to dynamically change resource allocations, and automatically allocates resources to enable suitable parallelism for an application without additional user input. In our exploration, we evaluate five scheduling algorithms: a baseline, three existing algorithms, and our novel Nimblock algorithm. We demonstrate system feasibility by realizing the complete system on a Xilinx ZCU106 FPGA and evaluating on a set of real-world benchmarks. In our results, we achieve up to 5.7x lower average response times when compared to a no-sharing and no-virtualization scheduling algorithm and up to 2.1x average response time improvement over competitive scheduling algorithms that support sharing within our virtualization environment. We additionally demonstrate up to 49% fewer deadline violations and up to 2.6x lower tail response times when compared to other high-performance algorithms.

关键词： Virtualization Reconfigurable computing Real-time Scheduling Overlay architectures

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Near-Stream computing: General and Transparent Near-Cache Acceleration 28

Near-Stream Computing: General and Transparent Near-Cache Ac...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Wang, Zhengrong Weng, Jian Liu, Sihao Nowatzki, Tony Univ Calif Los Angeles Los Angeles CA 90095 USA

ISBN: (纸本)9781665420273

Data movement and communication have become the primary bottlenecks in large multicore systems. the near-data computing paradigm provides a solution: move computation to where the data resides on-chip. Two challenges keep near-data computing from the mainstream: lack of programmer transparency and applicability. Programmer transparency requires providing sequential memory semantics with distributed computation, which requires burdensome coordination. Broad applicability requires support for combinations of address patterns (e.g. affine, indirect, multi-operand) and computation types (loads, stores, reductions, atomics). We find that streams - coarse grain memory access patterns - are a powerful ISA abstraction for near data offloading. Tracking data access at stream-granularity heavily reduces the burden of coordination for providing sequential semantics. Decomposing the problem using streams means that arbitrary combinations of address and computation patterns can be combined for broad generality. With this insight, we develop a paradigm called near-stream computing, comprising a compiler, CPU ISA extension, and a microarchitecture that facilitate programmer transparent computation offloading to shared caches. We evaluate our system on OpenMP kernels that stress broad addressing and compute behavior, and find that 46% of dynamic instructions can be offloaded to remote banks, reducing the network traffic by 76%. Overall it achieves 2.13x speedup over a state-of-the-art near-data computing technique, with a 1.90x energy efficiency gain.

关键词： Stream-Based ISAs Programmer-Transparent Acceleration Near-Data computing

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Systematic Approaches for Precise and Approximate Quantum State Runtime Assertion 27

Systematic Approaches for Precise and Approximate Quantum St...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Liu, Ji Zhou, Huiyang North Carolina State Univ Raleigh NC 27695 USA

ISBN: (纸本)9781665422352

With the rapid growth of quantum computing technology, programmers need new tools for debugging quantum programs. Recent works show that assertions are a promising way for debugging quantum programs. However, there are two main drawbacks with the existing schemes. First, the existing schemes, including both statistical and dynamic assertions are only capable of asserting limited types of states, namely classical, superposition, and specific entanglement states. Second, the use cases of these assertions are limited, since the programmer has to know the exact/precise state to assert. In this work, we propose two systematic approaches for dynamic quantum state assertion and they can assert a much broader range of quantum states including both pure states and mixed states. We also introduce the idea of approximate quantum state assertion for the cases where the programmers only have limited knowledge of the quantum states. Approximate assertion is capable of checking membership in a set of states {vertical bar phi), vertical bar phi), ... }. While precise quantum state assertion can check a specific quantum state, approximate assertion enables a way to check whether the qubits of interest are in a super-set of some expected states, which is analogous to the well-known Bloom filter for membership checking in classical computing. Our experiments demonstrate that our systematic approaches can assert many more quantum states and can be used in various assertion locations for qubit state checking.

关键词： quantum computing runtime assertion

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MXFaaS: Resource Sharing in Serverless Environments for Parallelism and Efficiency 23

MXFaaS: Resource Sharing in Serverless Environments for Para...

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50th Annual international symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Xu, Tianyin Franke, Hubertus Torrellas, Josep Univ Illinois Champaign IL 61820 USA IBM Res Yorktown Hts NY USA

ISBN: (纸本)9798400700958

Although serverless computing is a popular paradigm, current serverless environments have high overheads. Recently, it has been shown that serverless workloads frequently exhibit bursts of invocations of the same function. Such pattern is not handled well in current platforms. Supporting it efficiently can speed-up serverless execution substantially. In this paper, we target this dominant pattern with a new serverless platform design named MXFaaS. MXFaaS improves function performance by efficiently multiplexing (i.e., sharing) processor cycles, I/O bandwidth, and memory/processor state between concurrently executing invocations of the same function. MXFaaS introduces a new container abstraction called MXContainer. To enable efficient use of processor cycles, an MXContainer carefully helps schedule same-function invocations for minimal response time. To enable efficient use of I/O bandwidth, an MXContainer coalesces remote storage accesses and remote function calls from same-function invocations. Finally, to enable efficient use of memory/processor state, an MXContainer first initializes the state of its container and only later, on demand, spawns a process per function invocation, so that all invocations can share unmodified memory state and hence minimize memory footprint. We implement MXFaaS in two serverless platforms and run diverse serverless benchmarks. With MXFaaS, serverless environments are much more efficient. Compared to a state-of-the-art serverless environment, MXFaaS on average speeds-up execution by 5.2x, reduces P99 tail latency by 7.4x, and improves throughput by 4.8x. In addition, it reduces the average memory usage by 3.4x.

关键词： Serverless computing cloud computing resource management

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MapZero: Mapping for Coarse-grained Reconfigurable architectures with Reinforcement Learning and Monte-Carlo Tree Search 23

MapZero: Mapping for Coarse-grained Reconfigurable Architect...

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50th Annual international symposium on computer architecture (ISCA)

作者： Kong, Xiangyu Huang, Yi Zhu, Jianfeng Man, Xingchen Liu, Yang Feng, Chunyang Gou, Pengfei Tang, Minggui Wei, Shaojun Liu, Leibo Tsinghua Univ BNRist Sch Integrated Circuits Beijing Peoples R China GBA Innovat Inst High Performance Server Guangzhou Guangdong Peoples R China HEXIN Technol Co Ltd Guangzhou Guangdong Peoples R China

ISBN: (纸本)9798400700958

Coarse-grained reconfigurable architecture (CGRA) has become a promising candidate for data-intensive computing due to its flexibility and high energy efficiency. CGRA compilers map data flow graphs (DFGs) extracted from applications onto CGRAs, playing a fundamental role in fully exploiting hardware resources for acceleration. Yet the existing compilers are time-demanding and cannot guarantee optimal results due to the traversal search of enormous search spaces brought about by the spatio-temporal flexibility of CGRA structures and the complexity of DFGs. Inspired by the amazing progress in reinforcement learning (RL) and Monte-Carlo tree search (MCTS) for real-world problems, we consider constructing a compiler that can learn from past experiences and comprehensively understand the target DFG and CGRA. In this paper, we propose an architecture-aware compiler for CGRAs based on RL and MCTS, called MapZero - a framework to automatically extract the characteristics of DFG and CGRA hardware and map operations onto varied CGRA fabrics. We apply Graph Attention Network to generate an adaptive embedding for DFGs and also model the functionality and interconnection status of the CGRA, aiming at training an RL agent to perform placement and routing intelligently. Experimental results show that MapZero can generate superior-quality mappings and reduce compilation time hundreds of times compared to state-of-the-art methods. MapZero can find high-quality mappings very quickly when the feasible solution space is rather small and all other compilers fail. We also demonstrate the scalability and broad applicability of our framework.

关键词： Coarse-Grained Reconfigurable architecture Compiler Graph Neural Network Reinforcement Learning

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μManycore: A Cloud-Native CPU for Tail at Scale 23

μManycore: A Cloud-Native CPU for Tail at Scale

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50th Annual international symposium on computer architecture (ISCA)

作者： Stojkovic, Jovan Liu, Chunao Shahbaz, Muhammad Torrellas, Josep Univ Illinois Champaign IL 61820 USA Purdue Univ W Lafayette IN 47907 USA

ISBN: (纸本)9798400700958

Microservices are emerging as a popular cloud-computing paradigm. Microservice environments execute typically-short service requests that interact with one another via remote procedure calls (often across machines), and are subject to stringent tail-latency constraints. In contrast, current processors are designed for traditional monolithic applications. they support global hardware cache coherence, provide large caches, incorporate microarchitecture for long-running, predictable applications (such as advanced prefetching), and are optimized to minimize average latency rather than tail latency. To address this imbalance, this paper proposes mu Manycore, an architecture optimized for cloud-native microservice environments. Based on a characterization of microservice applications, mu Manycore is designed to minimize unnecessary microarchitecture and mitigate overheads to reduce tail latency. Indeed, rather than supporting manycore-wide hardware cache coherence, mu Manycore has multiple small hardware cache-coherent domains, called Villages. Clusters of villages are interconnected with an on-package leaf-spine network, which has many redundant, low-hop-count paths between clusters. To minimize latency overheads, mu Manycore schedules and queues service requests in hardware, and includes hardware support to save and restore process state when doing a context-switch. Our simulation-based results show that mu Manycore delivers high performance. A cluster of 10 servers with a 1024-core mu Manycore in each server delivers 3.7x lower average latency, 15.5x higher throughput, and, importantly, 10.4x lower tail latency than a cluster with iso-power conventional server-class multicores. Similar good results are attained compared to a cluster with power-hungry iso-area conventional server-class multicores.

关键词： Microservices cloud computing manycore architecture

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RM-SSD: In-Storage computing for Large-Scale Recommendation Inference 28

RM-SSD: In-Storage Computing for Large-Scale Recommendation ...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Sun, Xuan Wan, Hu Li, Qiao Yang, Chia-Lin Kuo, Tei-Wei Xue, Chun Jason City Univ Hong Kong Dept Comp Sci Hong Kong Peoples R China Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan Natl Taiwan Univ NTU High Performance & Sci Comp Ctr Taipei Taiwan

ISBN: (纸本)9781665420273

To meet the strict service level agreement requirements of recommendation systems, the entire set of embeddings in recommendation systems needs to be loaded into the memory. However, as the model and dataset for production-scale recommendation systems scale up, the size of the embeddings is approaching the limit of memory capacity. Limited physical memory constrains the algorithms that can be trained and deployed, posing a severe challenge for deploying advanced recommendation systems. Recent studies offload the embedding lookups into SSDs, which targets the embedding-dominated recommendation models. this paper takes it one step further and proposes to offload the entire recommendation system into SSD with in-storage computing capability. the proposed SSD-side FPGA solution leverages a low -end FPGA to speed up both the embedding-dominated and MLP-dominated models with high resource efficiency. We evaluate the performance of the proposed solution with a prototype SSD. Results show that we can achieve 20-100x throughput improvement compared with the baseline SSD and 1.5-15x improvement compared with the state-of-art.

关键词： Computational modeling Memory management Prototypes throughput Field programmable gate arrays Service level agreements Load modeling

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