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FPNA: A Reconfigurable Accelerator for AI Inference at the Edge

FPNA: A Reconfigurable Accelerator for AI Inference at the E...

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ieee International SOC conference

作者： Peter Gadfort Oluseyi A. Ayorinde Sensors and Electron Devices Directorate DEVCOM Army Research Laboratory Adelphi MD USA

ISBN: (纸本)9781665429320

this paper will present the architecture of a Field Programmable Neural Array (FPNA) for Artificial Intelligence (AI) applications at the tactical computing edge. this platform combines domain specific accelerators for AI with a reconfigurable interconnect to permit any Deep Neural Network (DNN) to be mapped into the FPNA. Moreover, this architecture allows for new and different neural networks to be mapped onto the hardware post-fabrication. the domain specific accelerators perform inference tasks with higher computing efficiency than CPUs and GPUs, approaching that of ASICs designed specifically for AI applications. the chip, fabricated on GlobalFoundries 55nm, only consumes 3.1 mW at peak efficiency, and can perform LeNet inference at 56.5 GOPs/W. this paper provides measured performance of ML workloads, as well as characterizations of a single computational block performing convolutions and fully connected layer operations. the best-case efficiency comes when computing fully connected layers at 4-bit precision, where this chip achieves 545.4 GOPs/W.

关键词： Deep learning Semiconductor device measurement Neurons computer architecture Programming Inference algorithms Hardware

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A Two-Stage Path Planning Engine for Robot Navigation System

A Two-Stage Path Planning Engine for Robot Navigation System

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ieee International SOC conference

作者： Yu-En Hsu Yen-Chin Liao Hsie-Chia Chang Institute of Electronics National Yang Ming Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781665429320

this paper presents a two-stage path planning architecture, realized by using a general-purpose CPU as a global planner and a proposed path planning engine as a local planner, solving a path planning problem hierarchically. By the use of heterogeneity, the hardware-software cooperation architecture can take advantages of both hardware and software approach and achieve both generalization and hardware-acceleration. the proposed path planning engine is based on A* algorithm, several hardware-friendly optimization techniques are applied or proposed to reduce the time complexity of searching. the coefficient modification avoids the usage of square root hardware. then, the priority list reordering fully utilizes the memory bandwidth. Finally, we optimized the critical path and achieved 333MHz operating *** proposed system is established and verified in Xilinx PYNQ-Z2 platform using ARM A9 processor as global planner and FPGA as local planner. Moreover, the proposed path planning engine is implemented in TSMC 40nm CMOS process and integrated 296.1k logic gates in 0.28mm 2 chip area. It achieves 9.6µs/task latency and 0.16µJ/task energy consumption in 2D and 27.6µs/task latency and 0.48µJ/task energy consumption in 3D.

关键词： Energy consumption Navigation computer architecture Bandwidth Voltage Logic gates Path planning

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On the Learning Property of Logistic and Softmax Losses for Deep Neural networks 34

On the Learning Property of Logistic and Softmax Losses for ...

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34th AAAI conference on Artificial Intelligence / 32nd Innovative Applications of Artificial Intelligence conference / 10th AAAI Symposium on Educational Advances in Artificial Intelligence

作者： Li, Xiangrui Li, Xin Pan, Deng Zhu, Dongxiao Wayne State Univ Dept Comp Sci Detroit MI 48202 USA

ISBN: (纸本)9781577358350

Deep convolutional neural networks (CNNs) trained with logistic and softmax losses have made significant advancement in visual recognition tasks in computer vision. When training data exhibit class imbalances, the class-wise reweighted version of logistic and softmax losses are often used to boost performance of the unweighted version. In this paper, motivated to explain the reweighting mechanism, we explicate the learning property of those two loss functions by analyzing the necessary condition (e.g.. gradient equals to zero) after training CNNs to converge to a local minimum. the analysis immediately provides us explanations for understanding (1) quantitative effects of the class-wise reweighting mechanism: deterministic effectiveness for binary classification using logistic loss yet indeterministic for multi-class classification using softmax loss;(2) disadvantage of logistic loss for single-label multi-class classification via one-vs.-all approach, which is due to the averaging effect on predicted probabilities for the negative class (e.g., non-target classes) in the learning process. With the disadvantage and advantage of logistic loss disentangled, we thereafter propose a novel reweighted logistic loss for multi-class classification. Our simple yet effective formulation improves ordinary logistic loss by focusing on learning hard non-target classes (target vs. non-target class in one-vs.-all) and turned out to be competitive with softmax loss. We evaluate our method on several benchmark datasets to demonstrate its effectiveness.

关键词： Deep neural networks

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PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry

PreSyNC: Hardware realization of the Presynaptic Region of a...

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International conference on VLSI Design

作者： Rounak Chatterjee Souradeep Chowdhury Soham Mondal Arnab Raha Janet Paluh Amitava Mukherjee Jadavpur University Kolkata India Memory Solutions Samsung Electronics Co. Ltd. Bangalore India Advanced Architecture Research Intel Edge. AI Intel Corporation Santa Clara USA Colleges of Nanoscale Science and Engineering Nanobioscience SUNY Polytechnic Institute Albany New York USA Adamas University Kolkata India

Spiking Neural networks (SNN) have gained relevance in recent times, due to their ability to mimic the biological nature to communicate and process sparse asynchronous binary signals in a massively parallel fashion. SNN based neuromorphic hardware exhibits highly desired favourable properties such as low power consumption, fast inference, and event-driven information processing. A recognized challenge of standard SNN neuron models is their limited capabilities in biological applications, such as applying neural networks to study network responses arising from variations pertaining to damage, external influence or disruptions in channel transfer dynamics. this paper presents Pre-Synaptic Neuronal Circuit (PreSyNC), a high performance hardware realization of an input-specific presynaptic region of a generic neuron, without abstraction of primary intra-neuronal parameters. PreSyNC is configured to operate on three precision modes: ieee 754 single precision, double precision and the recently developed universal number posit number system. the developed hardware design is compared to current standards of SNN neuron models as well as biological models in terms of flexibility, resource efficiency and damage modelling capability. Error margins as low as 0.9 % were obtained and suggest the capability of our hardware in handling applications involving large scale neuron networks. these architectures are synthesized on 45 nm process technology where they all operate at a minimum frequency of approximately 1GHz. the three precision modes are compared based on power, accuracy, and sensitivity handling and are expected to benefit implantation oriented applications such as neural prosthesis and Human-computer Interaction (HCI). the posit-based implementation outperforms the rest of the operating modes in terms of RMS error, while having 26.3 % less area and 25.2 % less power consumption compared to double precision implementation. these new architectures can be expanded in the fut

关键词： Human computer interaction Adaptation models Power demand Neuromorphics Biological system modeling Neurons Hardware

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Certified robustness of graph convolution networks for graph classification under topological attacks 34

Certified robustness of graph convolution networks for graph...

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34th conference on Neural Information Processing Systems, NeurIPS 2020

作者： Jin, Hongwei Shi, Zhan Peruri, Ashish Zhang, Xinhua Department of Computer Science University of Illinois at Chicago ChicagoIL60607 United States

Graph convolution networks (GCNs) have become effective models for graph classification. Similar to many deep networks, GCNs are vulnerable to adversarial attacks on graph topology and node attributes. Recently, a number of effective attack and defense algorithms have been designed, but no certificate of robustness has been developed for GCN-based graph classification under topological perturbations with both local and global budgets. In this paper, we propose the first certificate for this problem. Our method is based on Lagrange dualization and convex envelope, which result in tight approximation bounds that are efficiently computable by dynamic programming. When used in conjunction with robust training, it allows an increased number of graphs to be certified as robust. © 2020 Neural information processing systems foundation. All rights reserved.

关键词： Convolution

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Label Error Correction and Generation through Label Relationships 34

Label Error Correction and Generation through Label Relation...

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34th AAAI conference on Artificial Intelligence / 32nd Innovative Applications of Artificial Intelligence conference / 10th AAAI Symposium on Educational Advances in Artificial Intelligence

作者： Cui, Zijun Zhang, Yong Ji, Qiang Rensselaer Polytech Inst Dept Elect Comp & Syst Engn Troy NY 12180 USA Tencent AI Lab Shenzhen Peoples R China

ISBN: (纸本)9781577358350

For multi-label supervised learning, the quality of the label annotation is important. However, for many real world multilabel classification applications, label annotations often lack quality, in particular when label annotation requires special expertise, such as annotating fine-gained labels. the relationships among labels, on other hand, are usually stable and robust to errors. For this reason, we propose to capture and leverage label relationships at different levels to improve fine-grained label annotation quality and to generate labels. Two levels of labels, including object-level labels and property-level labels, are considered. the object-level labels characterize object category based on its overall appearance, while the property-level labels describe specific local object properties. A Bayesian network (BN) is learned to capture the relationships among the multiple labels at the two levels. A MAP inference is then performed to identify the most stable and consistent label relationships and they are then used to improve data annotations for the same dataset and to generate labels for a new dataset. Experimental evaluations on six benchmark databases for two different tasks (facial action unit and object attribute classification) demonstrate the effectiveness of the proposed method in improving data annotation and in generating effective new labels.

关键词： Bayesian networks

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A joint model for definition extraction with syntactic connection and semantic consistency 34

A joint model for definition extraction with syntactic conne...

引用

34th AAAI conference on Artificial Intelligence, AAAI 2020

作者： Veyseh, Amir Pouran Ben Dernoncourt, Franck Dou, Dejing Nguyen, thien Huu Department of Computer and Information Science University of Oregon EugeneOR97403 United States Adobe Research San JoseCA United States VinAI Research Hanoi Viet Nam

ISBN: (纸本)9781577358350

Definition Extraction (DE) is one of the well-known topics in Information Extraction that aims to identify terms and their corresponding definitions in unstructured texts. this task can be formalized either as a sentence classification task (i.e., containing term-definition pairs or not) or a sequential labeling task (i.e., identifying the boundaries of the terms and definitions). the previous works for DE have only focused on one of the two approaches, failing to model the interdependencies between the two tasks. In this work, we propose a novel model for DE that simultaneously performs the two tasks in a single framework to benefit from their interdependencies. Our model features deep learning architectures to exploit the global structures of the input sentences as well as the semantic consistencies between the terms and the definitions, thereby improving the quality of the representation vectors for DE. Besides the joint inference between sentence classification and sequential labeling, the proposed model is fundamentally different from the prior work for DE in that the prior work has only employed the local structures of the input sentences (i.e., word-to-word relations), and not yet considered the semantic consistencies between terms and definitions. In order to implement these novel ideas, our model presents a multi-task learning framework that employs graph convolutional neural networks and predicts the dependency paths between the terms and the definitions. We also seek to enforce the consistency between the representations of the terms and definitions both globally (i.e., increasing semantic consistency between the representations of the entire sentences and the terms/definitions) and locally (i.e., promoting the similarity between the representations of the terms and the definitions). the extensive experiments on three benchmark datasets demonstrate the effectiveness of our approach. Copyright © 2020 Association for the Advancement of Artificial Intelligen

关键词： Convolutional neural networks

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Fast fourier convolution 34

Fast fourier convolution

引用

34th conference on Neural Information Processing Systems, NeurIPS 2020

作者： Chi, Lu Jiang, Borui Mu, Yadong Wangxuan Institute of Computer Technology Center for Data Science Peking University China

Vanilla convolutions in modern deep networks are known to operate locally and at fixed scale (e.g., the widely-adopted 3 × 3 kernels in image-oriented tasks). this causes low efficacy in connecting two distant locations in the network. In this work, we propose a novel convolutional operator dubbed as fast Fourier convolution (FFC), which has the main hallmarks of non-local receptive fields and cross-scale fusion within the convolutional unit. According to spectral convolution theorem in Fourier theory, point-wise update in the spectral domain globally affects all input features involved in Fourier transform, which sheds light on neural architectural design with non-local receptive field. Our proposed FFC is inspired to capsulate three different kinds of computations in a single operation unit: a local branch that conducts ordinary small-kernel convolution, a semi-global branch that processes spectrally stacked image patches, and a global branch that manipulates image-level spectrum. All branches complementarily address different scales. A multi-branch aggregation step is included in FFC for cross-scale fusion. FFC is a generic operator that can directly replace vanilla convolutions in a large body of existing networks, without any adjustments and with comparable complexity metrics (e.g., FLOPs). We experimentally evaluate FFC in three major vision benchmarks (ImageNet for image recognition, Kinetics for video action recognition, MSCOCO for human keypoint detection). It consistently elevates accuracies in all above tasks by significant margins. © 2020 Neural information processing systems foundation. All rights reserved.

关键词： Convolution

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Improving Spectrum Usage on Full-Duplex Communications with an Innovative Channel Reservation 1

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34th International conference on Advanced Information Networking and Applications, AINA 2020

作者： de Melo Guimarães, Lucas Bordim, Jacir Luiz Department of Computer Science University of Brasília Brasília70910-900 Brazil

ISBN: (数字)9783030440411

ISBN: (纸本)9783030440404

Full-duplex (FD) communications shall play an important role on the next generation (5G) mobile wireless networks as they are expected to enhance spectrum usage and throughput. It requires a proper design of medium access control (MAC) schemes to fully exploit the potential advantages of FD communications. Notwithstanding, main existing full-duplex MAC schemes relies on ieee 802.11 building blocks, which was designed to operate with half-duplex communications. this work proposes Full-duplex Multiple Receiver MAC (FDMR-MAC), which was tailored to enhance throughput and channel use. FDMR-MAC uses an innovative channel reservation scheme that raises the probability of establishing a full-duplex communication where the sender and the receiver nodes have data payload to transmit to each other. To compare FDMR-MAC with state-of-art full-duplex communications mechanisms, an analytical model addressing the particular aspects of a FD communication is proposed. Numerical results indicate that FDMR-MAC achieved throughput up to 67 higher than a state-of-art full-duplex scheme, thus pointing the potential impact of FDMR-MAC use in FD communications. © 2020, Springer Nature Switzerland AG.

关键词： Medium access control

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DeepMutation++: A mutation testing framework for deep learning systems 34

DeepMutation++: A mutation testing framework for deep learni...

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34th ieee/ACM International conference on Automated Software Engineering, ASE 2019

作者： Hu, Qiang Ma, Lei Xie, Xiaofei Yu, Bing Liu, Yang Zhao, Jianjun Kyushu University Japan Nanyang Technological University Singapore Singapore Shanghai Jiao Tong University China

ISBN: (纸本)9781728125084

Deep neural networks (DNNs) are increasingly expanding their real-world applications across domains, e.g., image processing, speech recognition and natural language processing. However, there is still limited tool support for DNN testing in terms of test data quality and model robustness. In this paper, we introduce a mutation testing-based tool for DNNs, DeepMutation++, which facilitates the DNN quality evaluation, supporting both feed-forward neural networks (FNNs) and stateful recurrent neural networks (RNNs). It not only enables to statically analyze the robustness of a DNN model against the input as a whole, but also allows to identify the vulnerable segments of a sequential input (e.g. audio input) by runtime analysis. It is worth noting that DeepMutation++ specially features the support of RNNs mutation testing. the tool demo video can be found on the project website https://***/view/deepmutationpp. © 2019 ieee.

关键词： Deep neural networks

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