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CNN-MERP: An FPGA-based memory-efficient reconfigurable processor for forward and backward propagation of convolutional neural networks

CNN-MERP: An FPGA-based memory-efficient reconfigurable proc...

引用

ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Xushen Han Dajiang Zhou Shihao Wang Shinji Kimura Production and Systems Waseda University Kitakyushu Fukuoka Japan

Large-scale deep convolutional neural networks (CNNs) are widely used in machine learning applications. While CNNs involve huge complexity, VLSI (ASIC and FPGA) chips that deliver high-density integration of computational resources are regarded as a promising platform for CNN's implementation. At massive parallelism of computational units, however, the external memory bandwidth, which is constrained by the pin count of the VLSI chip, becomes the system bottleneck. Moreover, VLSI solutions are usually regarded as a lack of the flexibility to be reconfigured for the various parameters of CNNs. this paper presents CNN-MERP to address these issues. CNN-MERP incorporates an efficient memory hierarchy that significantly reduces the bandwidth requirements from multiple optimizations including on/off-chip data allocation, data flow optimization and data reuse. the proposed 2-level reconfigurability is utilized to enable fast and efficient reconfiguration, which is based on the control logic and the multiboot feature of FPGA. As a result, an external memory bandwidth requirement of 1.94MB/GFlop is achieved, which is 55% lower than prior arts. Under limited DRAM bandwidth, a system throughput of 1244GFlop/s is achieved at the Vertex UltraScale platform, which is 5.48 times higher than the state-of-the-art FPGA implementations.

关键词： Kernel Bandwidth Memory management throughput Field programmable gate arrays Backpropagation Neural networks

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Guided lightweight Software test qualification for IP integration using Virtual Prototypes

Guided lightweight Software test qualification for IP integr...

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ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Daniel Große Hoang M. Le Muhammad Hassan Rolf Drechsler Universitat Bremen Bremen Bremen DE Cyber-Physical Systems DFKI GmbH Bremen Germany Institute of Computer Science University of Bremen Bremen Germany

Software-Driven Verification (SDV) has the promise to significantly reduce the overall time and effort for the task of IP integration and verification. With the help of SystemC Virtual Prototypes (VPs), SW tests to verify the (new) integrated IP blocks and the HW/SW integration can be developed in an early design stage and reused in the subsequent steps. However, the crucial question regarding the quality of these tests has not been considered so far. For this purpose, we propose in this paper a novel quality-driven methodology based on mutation analysis. By elevating the main concepts of mutation-based qualification to the context of SDV, our methodology is capable to detect serious quality issues in the SW tests. At its heart is a novel consistency analysis, that measures the coverage of the IP in HW/SW co-simulation in a lightweight fashion and relates this coverage to the SW test results to provide clear feedback on how to further improve the quality of tests. We provide two case studies on real-world VPs and SW tests to demonstrate the applicability and efficacy of our methodology.

关键词： IP networks Software Analytical models Prototypes Context Time-varying systems Time-domain analysis

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CCAS: Contention and congestion aware switch allocation for network-on-chips

CCAS: Contention and congestion aware switch allocation for ...

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ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Cunlu Li Dezun Dong Xiangke Liao Fei Lei Ji Wu College of Computer National University of Defense Technology Changsha China

Network-on-chip system plays an important role to improve the performance of chip multiprocessor systems. As the complexity of the network increases, congestion problem has become the major performance bottleneck and seriously influence the performance of NoCs. Prior works have focused on designing effective routing algorithm based on collecting contention and congestion information to load balance the traffic. However, most prior works do not consider balancing the traffic load during switch allocation. Due to the lack of congestion information in switch allocation stage, switch allocator performs allocation only based on packet requests and thus aggravates the congestion in the ports of switch. In this paper, we propose CCAS, a new switch allocation strategy to add the contention and congestion information into the switching process to load balance the traffic and achieve efficient switch allocation. We carefully design CCAS to balance the trade-off between traffic load balance and the matching efficiency in switch allocation. We evaluate our design under synthetic traffic and traces of PARSEC benchmarks. Our evaluations show that CCAS can achieve remarkable latency reduction compared to other switch allocation strategies.

关键词： Ports (computers) Resource management Switches Benchmark testing Mesh networks Routing computers

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Extending On-chip Interconnects for rack-level remote resource access

Extending On-chip Interconnects for rack-level remote resour...

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ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Yisong Chang Ke Zhang Sally A. McKee Lixin Zhang Mingyu Chen Liqiang Ren Zhiwei Xu University of Chinese Academy of Sciences Beijing China Chalmers University of Technology Gothenburg Sweden ICT CAS State Key Laboratory of Computer Architecture Beijing China

the need to perform data analytics on exploding data volumes coupled with the rapidly changing workloads in cloud computing places great pressure on data-center servers. To improve hardware resource utilization across servers within a rack, we propose Direct Extension of On-chip Interconnects (DEOI), a high-performance and efficient architecture for remote resource access among server nodes. DEOI extends an SoC server node's on-chip interconnect to access resources in adjacent nodes with no protocol changes, allowing remote memory and network resources to be used as if they were local. Our results on a four-node FPGA prototype show that the latency of user-level, cross-node, random reads to DEOI-connected remote memory is as low as 1.16μs, which beats current commercial technologies. We exploit DEOI remote access to improve performance of the Redis in-memory key-value framework by 47%. When using DEOI to access remote network resources, we observe an 8.4% average performance degradation and only a 2.52μs ping-pong latency disparity compared to using local assets. these results suggest that DEOI can be a promising mechanism for increasing both performance and efficiency in next-generation data-center servers.

关键词： Servers System-on-chip Hardware Protocols computer architecture Software Prototypes

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DSCNN: Hardware-oriented optimization for Stochastic Computing based Deep Convolutional Neural networks

DSCNN: Hardware-oriented optimization for Stochastic Computi...

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ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Zhe Li Ao Ren Ji Li Qinru Qiu Yanzhi Wang Bo Yuan Department of Electrical Engineering and Computer Science Syracuse University Syracuse NY USA Department of Electrical Engineering University of Southern California Los Angeles CA USA ‡Department of Electrical Engineering City University of New York New York NY USA

Deep Convolutional Neural networks (DCNN), a branch of Deep Neural networks which use the deep graph with multiple processing layers, enables the convolutional model to finely abstract the high-level features behind an image. Large-scale applications using DCNN mainly operate in high-performance server clusters, GPUs or FPGA clusters; it is restricted to extend the applications onto mobile/wearable devices and Internet-of-things (IoT) entities due to high power/energy consumption. Stochastic Computing is a promising method to overcome this shortcoming used in specific hardware-based systems. Many complex arithmetic operations can be implemented with very simple hardware logic in the SC framework, which alleviates the extensive computation complexity. the exploration of network-wise optimization and the revision of network structure with respect to stochastic computing based hardware design have not been discussed in previous work. In this paper, we investigate Deep Stochastic Convolutional Neural Network (DSCNN) for DCNN using stochastic computing. the essential calculation components using SC are designed and evaluated. We propose a joint optimization method to collaborate components guaranteeing a high calculation accuracy in each stage of the network. the structure of original DSCNN is revised to accommodate SC hardware design's simplicity. Experimental Results show that as opposed to software inspired feature extraction block in DSCNN, an optimized hardware oriented feature extraction block achieves as higher as 59.27% calculation precision. And the optimized DSCNN can achieve only 3.48% network test error rate compared to 27.83% for baseline DSCNN using software inspired feature extraction block.

关键词： Feature extraction Hardware Neurons Optimization Neural networks Stochastic processes Software

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A model for Application Slowdown Estimation in on-chip networks and its use for improving system fairness and performance

A model for Application Slowdown Estimation in on-chip netwo...

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ieee International conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Xiyue Xiang Saugata Ghose Onur Mutlu Nian-Feng Tzeng University of Louisiana at Lafayette Carnegie Mellon University ETH Zürich

ISBN: (纸本)9781509051434

In a network-on-chip (NoC) based system, the NoC is a shared resource among multiple processor cores. Network requests generated by different applications running on different cores can interfere with each other, leading to a slowdown in performance of each application. the degree of slowdown introduced by this interference varies for each application, as it depends on (1) the sensitivity of the application to NoC performance, and (2) network traffic induced by other applications running concurrently on the system. In modern systems, NoC interference is largely uncontrolled, and therefore some applications unfairly slow down much more than others. this can lead to overall system performance degradation, prevent fair progress of different applications, and cause starvation of unfairly-treated applications. Our goal is to accurately model the slowdown of each application executing on the system due to NoC interference at runtime, and to use this information to improve system performance and reduce unfairness. To this end, we propose the NoC Application Slowdown (NAS) Model, the first online model that accurately estimates how much network delays due to interference contribute to the overall stall time of each application. the key idea of NAS is to determine how the delays induced at each level of network data transmission overlap with each other, and to use the overlap information to calculate the net impact of the delays on application stall time. Our model determines the application slowdowns at runtime with a very low error rate, averaging 4.2% over 90 multiprogrammed workloads for an 8×8 mesh network. We use NAS to develop Fairness-Aware Source throttling (FAST), a mechanism that employs slowdown predictions to control the network injection rates of applications in a way that minimizes system unfairness. Our results over a variety of multiprogrammed workloads show that FAST improves average system fairness and performance by 9.5% and 5.2%, respectively.

关键词： Interference Delays Multicore processing Runtime System performance Ports (computers) Estimation

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Current Techniques, Trends and New Horizons in Avionics networks Configuration 34

Current Techniques, Trends and New Horizons in Avionics Netw...

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ieee/AIAA 34th Digital Avionics Systems conference (DASC)

作者： Steiner, Wilfried Gutierrez, Marina Matyas, Zoltan Pozo, Francisco Rodriguez-Navas, Guillermo TTTech Comp Tech AG Vienna Austria TTTech Hungary Kft Budapest Hungary Malardalen Univ Vasteras Sweden

ISBN: (纸本)9781479989409

Avionics networks are probably the best understood communication technologies when it comes to guaranteed quality of service since they need to deliver their service under all operational conditions, sometimes even in presence of failures. However, this is only possible because the right tools are available for the rather complex tasks of network configuration and traffic analysis.

关键词： aerospace simulation avionics local area networks quality of service scheduling search problems TTEthernet TTP aircraft avionics full-duplex switched Ethernet avionics network configuration communication technology data transmission network calculus scheduling problem search-based technique time-triggered synchronized communication bus time-triggered system traffic analysis Real-time systems

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Group-based Fast Handover for PMIPv6-Based NEtwork MObility in Vehicular networks

Group-based Fast Handover for PMIPv6-Based NEtwork MObility ...

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34th ieee conference on computer Communications (INFOCOM)

作者： Kim, Mun-Suk Lee, SuKyoung Yonsei Univ Dept Comp Sci Seoul South Korea

ISBN: (纸本)9781467371315

To improve the handover performance of network mobility basic support (NEMO-BS), several schemes have been developed. However, these schemes are designed for a single vehicle and hence may incur significant signaling overhead in the vehicular networks (VNs). therefore, we propose an bulk fast handover scheme to mitigate such signaling overhead. Simulation results show that the proposed scheme significantly outperforms the previous

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Dynamic State Estimation in Power Systems Using A Distributed MAP Method 34

Dynamic State Estimation in Power Systems Using A Distribute...

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第三十四届中国控制会议

作者： SUN Yibing FU Minyue WANG Bingchang ZHANG Huanshui School of Control Science and Engineering Shandong University School of Control Science and Engineering Zhejiang University School of Electrical Engineering and Computer Science University of Newcastle

ISBN: (纸本)9789881563897

this paper studies a dynamic state estimation problem for power systems, which can be seen as the quasi-static systems. the state vector of each subsystem(called node) in power networks is expressed by measurements. Based on a distributed maximum a posteriori(MAP) estimation technique, a fully distributed state estimation method is presented to update the local state at each time instant. Also, the assumption of local observability of every node is no longer needed. Tests on the ieee 118-bus system are used to show the performance of the proposed approach and compare its results with a centralized state estimation method providing the optimal state estimate for the entire power networks, a local state estimation method using the edge measurements as the local measurements to estimate its local state, and a distributed static state estimation algorithm.

关键词： Distributed state estimation,MAP estimation,Kalman filter,Power networks

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Heterogeneous Wireless Sensor networks for Flood Prediction Decision Support Systems

Heterogeneous Wireless Sensor Networks for Flood Prediction ...

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34th ieee conference on computer Communications (INFOCOM)

作者： Andersson, Karl Hossain, Mohammad Shahadat Lulea Univ Technol Pervas & Mobile Comp Lab SE-93187 Skelleftea Sweden Univ Chittagong Dept Comp Sci & Engn University 4331 Bangladesh

ISBN: (纸本)9781467371315

Recent advancements in the fields of sensor equipment and wireless sensor networks have opened the window of opportunity for many innovative applications. In this paper, we propose a new architecture for building decision support systems using heterogeneous wireless sensor networks. the architecture is built around standard hardware and existing wireless sensor networks technology. We show the effectiveness of the proposed architecture by applying it to a flood prediction scenario.

关键词： Internet of things Wireless Sensor networks Flood prediction Belief-rule-based Decision Support Systems

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