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2024 ieee international conference on Sensing, Diagnostics, Prognostics, and Control, SDPC 2024

作者： Meng, Linghui Xie, Jinyang Zhou, Zhenwei Chen, Yiqiang China Electronic Product Reliability and Environmental Testing Research Institute Science and Technology on Reliability Physics and Application of Electronic Component Laboratory Guangzhou China School of Electrical Engineering Beijing Jiaotong University Beijing China

ISBN: (纸本)9798350388855

With the objective to achieve an accurate diagnosis of commonly encountered fault problems in power electronic circuits and to prevent the occurrence of catastrophic failures, a soft fault diagnosis model for dc-dc converter based on the gram angle difference filed (GADF) and the channel split residual network (CSRN) is proposed. Firstly, the original fault data is coded by GADF to generate the fault data set. Secondly, channel split preprocessing (CSP) and Darwinian selection mechanism (DSM) are introduced to enhance the residual network and further construct the CSRN. CSP emphasizes the important channel features in the fault feature images by achieving a brute-force enhancement of the channel information and highlighting subtle features. DSM retains the key features and removes the secondary features during network training. The GADF-CSRN diagnosis model proposed in this paper is verified by the fault data collected from a dc-dc converter. The result showed that a diagnosis accuracy of 97.92% is achieved, surpassing the accuracy of conventional method by at least 1.85%, while exhibiting better noise resistance. © 2024 ieee.

关键词： DC distribution systems

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Adaptive Methods for Machine Learning-Based testing of Integrated circuits and Boards

Adaptive Methods for Machine Learning-Based Testing of Integ...

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ieee international Test conference (ITC)

作者： Liu, Mengyun Chakrabarty, Krishnendu Duke Univ Dept Elect & Comp Engn Durham NC 27706 USA

ISBN: (纸本)9781665416955

The relentless growth in information technology and artificial intelligence (AI) is placing demands on integrated circuits and boards for high performance, added functionality, and low power consumption. However, these new trends lead to high test cost and challenges associated with test planning. Machine learning (ML) provides an opportunity to overcome the challenges associated with the testing of complex systems. Taking the advantages of ML techniques, useful information can be extracted from test data logs, and this information helps facilitate the testing process for both chips and boards. In addition, the ever-growing need to achieve test-cost reduction with no test-quality degradation is driving the adoption of ML-based adaptive methods for testing. Adaptive test methods observe changes in the distribution of test data and dynamically adjust the testing process, thus reducing test cost. In this paper, we describe efficient solutions for adapting machine-learning techniques to testing and diagnosis. To reduce manufacturing cost, we select different test items for chips with different predicted quality levels. To avoid the periodic interruption of computing tasks in accelerators for AI, we describe an efficient online testing method that interrupts the regular computation only when a high defect rate is estimated. To identify board-level functional faults with high accuracy, we utilize online incremental learning and transfer learning to address the practical issues that arise when we deal with real-life test data in a high-volume production environment.

关键词： Integrated circuits Costs Power demand Transfer learning Production Market research Planning

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Reduction of Fault Dictionary Size by Optimizing the Order of Test Patterns Application 35

Reduction of Fault Dictionary Size by Optimizing the Order o...

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35th international Technical conference on circuits/systems, Computers and Communications (ITC-CSCC)

作者： Higami, Yoshinobu Inamoto, Tsutomu Wang, Senling Takahashi, Hiroshi Saluja, Kewal K. Ehime Univ Grad Sch Sci & Engn Bunkyocho 3 Matsuyama Ehime 7908577 Japan Univ Wisconsin Dept Elect & Comp Engn 1415 Engn Dr Madison WI 53706 USA

ISBN: (纸本)9784885523281

Fault dictionary based approach is known to be a popular diagnosis method. In this approach, output responses are compared between a circuit under diagnosis and an associated fault dictionary to deduce candidate faults. A fault dictionary that contains output values at all the primary outputs for all the test patters and for all the target faults is called full response dictionary, and its size tends to be very large. Therefore, for practical reasons the fault dictionary size needs to be reduced. In this paper we propose a test pattern ordering method for reducing the fault dictionary size. For example, let's consider a case where a certain fault f exists in a circuit under diagnosis. If first n test patterns are sufficient to deduce fault f as the only candidate fault, then the dictionary does not need to store the output responses for fault f with the test patterns other than the first n test patterns. The proposed method applies a heuristic approach to determine the order of test patterns to reduce the size of fault dictionary to be stored. Experimental results show the effectiveness of the proposed method.

关键词： LSI testing Fault diagnosis Fault dictionary

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A Learning-Based Cell-Aware diagnosis Flow for Industrial Customer Returns

A Learning-Based Cell-Aware Diagnosis Flow for Industrial Cu...

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ieee international Test conference

作者： S. Mhamdi P. Girard A. Virazel A. Bosio A. Ladhar LIRMM Univ. of Montpellier / CNRS Montpellier France INL École Centrale de Lyon France STMicroelectronics Crolles France

ISBN: (数字)9781728191133

ISBN: (纸本)9781728191140

diagnosis is crucial in order to establish the root cause of observed failures in systems-on-Chip (SoC). In this paper, we present a new framework based on supervised learning for cell-aware defect diagnosis of customer returns. By using a Naive Bayes classifier to accurately identify defect candidates, the proposed flow indistinctly deals with static and dynamic defects that may occur in actual circuits. Results achieved on benchmark circuits, as well as comparison with a commercial cell-aware diagnosis tool, show the effectiveness of the proposed framework in terms of accuracy and resolution. Moreover, the proposed flow has been experimented and validated on industrial circuits (two test chips and one customer return from STMicroelectronics), thus corroborating the results achieved on benchmark circuits.

关键词： Circuit faults Training data Tools Manufacturing Benchmark testing Standards Integrated circuit modeling

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Deep Convolutional Neural Network (DCNN) for Skin Cancer Classification

Deep Convolutional Neural Network (DCNN) for Skin Cancer Cla...

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ieee international conference on Electronics, circuits and systems (ICECS)

作者： Nour Aburaed Alavikunhu Panthakkan Mina Al-Saad Saad Ali Amin Wathiq Mansoor College of Engineering and IT University of Dubai Dubai UAE

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Skin cancer is one of the most threatening types of cancer, with an increasing rates throughout the decade. Detecting and classifying skin cancer in its early stages provides better chances for treatment. In the recent years, Convolutional Neural Networks (CNNs) emerged as a powerful solution that aids the diagnosis of skin cancer. In this paper, Human Against Machine (HAM) 10000 dataset is used to demonstrate skin cancer classification strategy. VGG16, VGG19, and a Deep CNN proposed in this paper are implemented, trained, and evaluated. The dataset pre-processing steps and methodology are illustrated, and the network parameters and training process are explained. The performance of all three networks are compared in terms of the average overall accuracy and loss.

关键词： Training Lesions Skin testing Melanoma Computer architecture Deep learning

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High Throughput Chain diagnosis Methodology with Minimal Failure Data Collection

High Throughput Chain Diagnosis Methodology with Minimal Fai...

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ieee international Test conference on India (ITC India)

作者： Sameer Chillarige Anil Malik Atul Chhabra Bharath Nandakumar Kanika Kanwal Cadence Design Systems Noida India

The following topics are dealt with: integrated circuit testing; integrated circuit design; electronic engineering computing; automotive electronics; failure analysis; boundary scan testing; integrated circuit reliabi... 详细信息

ISBN: (纸本)9781728105741

关键词： failure analysis flip-flops integrated circuit reliability logic testing integrated circuit reliability Logic testing flip-flops FAILURE ANALYSIS failures Product Design diagnosis linearly ordered set

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An Novel testing Sequence Optimization Method under Dynamic Environments 10

An Novel Testing Sequence Optimization Method under Dynamic ...

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10th international conference on Communications, circuits and systems (ICCCAS)

作者： Lu, Bo Mei, Wenjuan Zhou, Jianming Zhou, Hu Du, Li Liu, Zhen Beijing Aerosp Automat Control Inst Beijing Peoples R China Univ Elect Sci & Technol China Chengdu Sichuan Peoples R China

ISBN: (纸本)9781538693896

Over decades, testing sequence optimization has been an important part for the design of testability (DFT). However, most existed method suffers from high searching complexity. Meanwhile,with the high speed of updating with electronic technology, the cost for test points and the probability of the fault state varies due to the development of the systems. Therefore, how to update the testing sequential model comes to be important to improve the efficiency on diagnosis. Since that, in this paper, we proposed a new testing sequence optimization method based on AO* and dynamic programming to improve the efficiency on generate solutions. Also, we develop the updating method for the problem under three dynamic conditions which may change the optima solution. The experiments shows that our method can achieve better performance than several state-of-art algorithms.

关键词： AO* algorithm Test Sequential Optimization Dynamic Programming

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Accelerated Life testing and Performance Evaluation of Smart Pressure Transmitters for use in Nuclear Power Plants 7

Accelerated Life Testing and Performance Evaluation of Smart...

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7th international conference on Reliability, Infocom Technologies and Optimization - Trends and Future Directions (ICRITO)

作者： Chauhan, Yashasvi Shrestha, N. B. Santhosh, T. V. Shrivastava, Vivek Ramteke, P. K. Vinod, Gopika Chattopadhyay, J. Natl Inst Technol Delhi India Bhabha Atom Res Ctr Reactor Safety Div Mumbai Maharashtra India

ISBN: (纸本)9781538646922

Nuclear power plants (NPP) require continuous monitoring of various process parameters such as temperature, pressure and flow etc. for safe and reliable operation of the plant. Smart pressure transmitters (SPT) are increasingly being used in the nuclear industry over conventional pressure transmitters. Smart pressure transmitter offers the potential to improve safety and reliability for NPP by use of their advance features such as self-diagnosis, remote configuration for field communication, etc. This has simultaneously increased the complexity of the smart transmitter and added additional challenges in reliability area. Therefore, it is important to assess the reliability of SPTs before their use in safety critical systems. This paper represents the findings from accelerated life testing and performance evaluation study carried out on smart pressure transmitters. An experimental investigation of 9 SPTs has been carried out by subjecting to accelerated thermal ageing under different temperature conditions [60 degrees C, 70 degrees C and 80 degrees C] for approximately 4 months. The study focused mainly on deriving the performance parameters from calibration, power supply and load variation effect, insulation resistance tests. The important parameters measured are the accuracy, repeatability, hysteresis etc. It was observed from the study that the performance of SPTs degrades due to ageing of its internal components such as sensors, electronic circuits, insulation degradation, etc. Based on the performance data obtained from the testing, the degradation models have also been developed for remaining useful life estimation of SPTs.

关键词： Reliability Performance Evaluation Smart Pressure Transmitters Acceleration Life testing Nuclear Power Plants

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diagnosis of Performance Limiting Segments in Integrated circuits Using Path Delay Measurements

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ieee TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND systems 2017年第2期36卷 325-335页

作者： Somashekar, Ahish Mysore Tragoudas, Spyros Southern Illinois Univ Dept Elect & Comp Engn Carbondale IL 62901 USA

An approach capable of identifying the locations of distributed small delay defects, arising due to manufacturing aberrations, is proposed. It is shown that the proposed formulation can be transformed into a Boolean satisfiability form to be solved by any satisfiability solver. The approach is capable of providing a small number of alternative sets of potential defective segments, and one of the solutions is the actual defect configuration. This is shown to be a very important property toward the effective identification of the defective segments. Experimental analysis on international symposium on circuits and systems and international Test conference benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.

关键词： Delay testing diagnosis satisfiability silicon debug small delay defects (SDDs)

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Next Generation Armament Test Solutions for the Flightline

Next Generation Armament Test Solutions for the Flightline

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international Automatic testing conference, AUTOTESTCON

作者： Loofie Gutterman Marvin Test Solutions Irvine CA USA

Smart weapon systems are now common place within the U.S. Armed Forces community and among U. S. allies. And to ensure mission success, maintainers need to confirm that all of these systems are mission ready or Full Mission Capable (FMC). Gone are the days of simply checking for the absence of stray voltage and the presence of firing signals by using an Armament circuits Pre-Load Test Set (ACPTS), commonly referred to as a “beer can”. Today's sophisticated weapon systems need to support not only legacy test needs but also advanced systems by providing multiple measurement and stimulus channels as well as incorporating communication busses such as MMSI, MIL-STD-1760, Ethernet, CAN Bus, and more. The challenges faced by developers and customers alike lie with the difficulty to incorporate these capabilities into a handheld package to help minimize the “footprint of test”. There are some advanced solutions available today that can address not only the current generation of legacy and smart weapons but also have the flexibility to address future armament test needs on the flightline. Building on the current generation of “smart” beercans, the next generation solution for flightline test offers maintainers the ability to perform advanced test and diagnosis on the flightline - simplifying maintenance logistics while increasing performance and reducing test and maintenance time. This next generation “smart” beercan - the “SmartCan™”, offers advanced features and capabilities including: : Full analog test support for legacy systems including Audio and Video signal generation : Full MIL-STD-1760 support : Full support for additional interfaces including EBR1553, MMSI, Ethernet, CAN Bus, and more By offering these advanced features and improved legacy test capabilities, maintainers now have the ability to not only test but also emulate the weapons - facilitating a complete test of the weapon system's interface, from the cockpit's multi-function display (MFD) to the launch rai

关键词： Weapons Aircraft testing Military aircraft Next generation networking Firing Military standards

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