The proceedings contain 172 papers. The topics discussed include: study of the test flow optimization method in radar fault isolation;network cable fault location based on the wide pulse time domain reflection;researc...
ISBN:
(纸本)9781424425877
The proceedings contain 172 papers. The topics discussed include: study of the test flow optimization method in radar fault isolation;network cable fault location based on the wide pulse time domain reflection;research and application about general-purpose electronic system test platform;research and implementation of glitch capture technology;research on clock synchronization of wireless distributed measurement system;design and implementation of FC-AE-1553 point transmission hardware platform;a survey of neuromorphic engineering-biological nervous system realized on silicon;the research and application of the electric capacitor detecting sea ice thickness and its detecting system;a platform based on CORBA for open networked measurement system;and design for low power testing of computation modules with contiguous subspace in VLSI.
Based on the recommendation of ictd'09 TPC members, this Special Issue of the Journal of Electronic Science & Technology of China (JESTC) contained 22 high quality papers selected from the Proceedings of 2009 ieee...
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Based on the recommendation of ictd'09 TPC members, this Special Issue of the Journal of Electronic Science & Technology of China (JESTC) contained 22 high quality papers selected from the Proceedings of 2009 ieee circuits and systems international conference on testing and diagnosis (ictd '09) which is fully sponsored by the ieeecircuits and systems Society (CASS), and is technically co-sponsored by the University of Electronic Science and Technology of China (UESTC), the Chinese Institute of Electronics (CIE), the China Instrument & Control Society (CIS), and organized by UESTC.
This paper presents a method to realize FC-AE-1553 point to point data transmission hardware platform, and bring forward a method to test the platform. We used well developed protocol cards and embedded computer to re...
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ISBN:
(纸本)9781424425860
This paper presents a method to realize FC-AE-1553 point to point data transmission hardware platform, and bring forward a method to test the platform. We used well developed protocol cards and embedded computer to realize the Fiber Channel transmitting system and MIL-STD-1553 bus, used local computer and embedded computer to realize the Protocol Bridge software, and used local computer to control the whole FC-AE-1553 transmission and do the system test. At last we tested our platform with our method to prove the validity of platform.
This paper presents an original system verification methodology for complex consumer electronic devices. Automated verification of the system which consists of hardware (integrated circuit) and corresponding software ...
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ISBN:
(纸本)9781424425860
This paper presents an original system verification methodology for complex consumer electronic devices. Automated verification of the system which consists of hardware (integrated circuit) and corresponding software as a one building block within a modern flat panel TV sets is in the focus. Created environment provides fast and reliable verification of the system, focusing on the software realized features.
This paper presents a Built-In Self-Test (BIST) approach to test embedded memory blocks in configurable System-on-Chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testin...
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ISBN:
(纸本)9781424425860
This paper presents a Built-In Self-Test (BIST) approach to test embedded memory blocks in configurable System-on-Chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtex1-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMS operating in all of different sizes both in single-port and dual-port modes. The paper also has developed a parameterized VerilogHDL code which is portable and can be used to test embedded memories with minimal changes in any configurable SoCs.
A JTAG IP core based on ieee1149.1 standard has been reported here, including its design and implementation. it has been described using synthesized Verilog HDL language. Simulation demonstration has also been made an...
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ISBN:
(纸本)9781424425860
A JTAG IP core based on ieee1149.1 standard has been reported here, including its design and implementation. it has been described using synthesized Verilog HDL language. Simulation demonstration has also been made and the result has been synthesized. It has been demonstrated that the IP core design is feasibility. Moreover, based on the characteristic of DFT using JTAG standard, some improvements on the JTAG structure are proposed to get an optimized result.
This paper presents an experimental study on the testing of process control for a real-time control system. Several indexes, such as the capability of system approximation output, the ramp rates, the smoothness and st...
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ISBN:
(纸本)9781424425860
This paper presents an experimental study on the testing of process control for a real-time control system. Several indexes, such as the capability of system approximation output, the ramp rates, the smoothness and stability of output ability, control of temperature overshoot, are selected as performance parameters, with which validating, analyzing and monitoring the thermal performance of thermal cyclers. A testing prototype is designed and fabricated as a supplementary instrument for the experimental study. A tracking temperature algorithm with feed forward and feedback control is also introduced to improve the efficiency of system performance testing by the testing prototype.
A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects sing...
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ISBN:
(纸本)9781424425860
A novel Built-in Self-Test (BIST) approach to test the configurable Input/Output buffers in Xilinx Virtex series SOCs using Hard Macro has been proposed in this paper. The proposed approach can completely detects single and multiple stuck-at gate-level faults as well as associated routing resources in I/O buffers. The proposed BIST architecture has been implemented and verified on Xilinx Virtex series FPGAs. Only total of 10 configurations are required to completely test the I/O buffers of Virtex devices.
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