This paper contributes to the research in the field of generative computational design of discrete assemblies and their implementations in constructing spatial structures in architecture. In the article, by proposing ...
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(纸本)9789887891833
This paper contributes to the research in the field of generative computational design of discrete assemblies and their implementations in constructing spatial structures in architecture. In the article, by proposing a standard tubular shape as the base unit, and then accomplishing type constraints, quantity integration, and cost control, we achieve an effective generation, optimization, and assembly strategy for discrete structures. Based on the principles of performance-oriented architecture and cost control, we utilize computational geometric generation and optimal design with simulated annealing and genetic algorithms to achieve a globally optimal solution by constraining the spatial voxel control mesh, which produces a discrete modular assembly system that not only has structural stability but also creates complex spatial forms. The method has the potential to optimize the digital generation and construction process, control implementation costs, and extend engineering applications.
This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic computer-aideddesign (ECAD) architecture in the form of software is implemented. It makes it possible t...
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This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic computer-aideddesign (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic controlsystem. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.
computer-aided interpreting(CAI) systems are software applied to one or more stages of interpreting tasks, which can directly promote the work of interpreters and improve the interpreting quality. Until now, studies o...
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computer-aided interpreting(CAI) systems are software applied to one or more stages of interpreting tasks, which can directly promote the work of interpreters and improve the interpreting quality. Until now, studies on CAI in simultaneous interpretation(SI) have been limited, primarily focusing on the design and development of manual extraction models. Moreover, what's particularly noteworthy is the lack of thorough investigation into the development of fully automated CAI models for extracting terms (SI difficulties) and other related aspects. Based on the experimental research of existing ones, this study puts forward some new methods based on automatic speech recognition(ASR) and develops a CAI system-InterpretSIMPLE with user-friendly interface, which implements automatic retrieval and display of terms (pre-imported), numbers, etc. as well as other functions specialized for conference interpreters. Through the setting of three-line label control and underline panel control, the system realizes the attention allocation and positioning of the source text content at different levels. One-click import of commonly-used Excel glossary gives simple operation with no additional format conversion. Terminologies and numbers are displayed below the corresponding position while displaying the source text, so that interpreters could locate and solve these recognized SI difficulties. Through the "exact matching" or "partial matching" setting, it could meet the personalized requirements of terms matching. The experiment shows that after the system receives text information from Tencent Cloud, the real-time display rate of the pre-imported glossary reaches 98.92%. The research results could provide references for the research and development of in-process automated CAI tools.
Correcting the controlsystem’s frequency response to meet requirements such as stability, steady-state and dynamic performance is a crucial part in the course Automatic control Principle. To help students better und...
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Modern GPUs have integrated multilevel cache hierarchy to provide high bandwidth and mitigate the memory wall problem. However, the benefit of on-chip cache is far from achieving optimal performance. In this article, ...
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Modern GPUs have integrated multilevel cache hierarchy to provide high bandwidth and mitigate the memory wall problem. However, the benefit of on-chip cache is far from achieving optimal performance. In this article, we investigate existing cache architecture and find that the cache utilization is imbalanced and there exists serious data duplication among L1 cache *** order to exploit the duplicate data, we propose an intergroup cache cooperation (ICC) method to establish the cooperation across L1 cache groups. According the cooperation scope, we design two schemes of the adjacent cache cooperation (ICC-AGC) and the multiple cache cooperation (ICC-MGC). In ICC-AGC, we design an adjacent cooperative directory table to realize the perception of duplicate data and integrate a lightweight network for communication. In ICC-MGC, a ring bi-directional network is designed to realize the connection among multiple groups. And we present a two-way sending mechanism and a dynamic sending mechanism to balance the overhead and efficiency involved in request probing and *** results show that the proposed two ICC methods can reduce the average traffic to L2 cache by 10% and 20%, respectively, and improve overall GPU performance by 19% and 49% on average, respectively, compared with the existing work.
The ubiquitous presence and utilization of system-on-Chips (SoCs) have made them critical to our daily lives. As SoCs become more complex, their susceptibility to security threats has also increased. The comprehensive...
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The ubiquitous presence and utilization of system-on-Chips (SoCs) have made them critical to our daily lives. As SoCs become more complex, their susceptibility to security threats has also increased. The comprehensive security assurance of an SoC system requires a deep knowledge of the design and security-critical assets that must be protected. As SoC applications vary, the assets vary in number, type, importance level, and form based on the various hardware blocks that construct the SoC and their complex interactions. Some assets are distinctive in their definition and characteristics, making them easily identifiable, such as encryption/decryption keys, logic locking keys, etc. However, other assets, such as system bus control registers that are internal to the design, require a more complex design analysis. Automatic identification of these security assets at the presilicon stage can help designers take the necessary precautions to protect them. Equipped with the security assets, designers can then incorporate techniques to protect these security assets against various threats. This article presents the variation among security assets based on hardware design and defines attributes to help classify them. Then, we introduce security asset identification framework (SAIF), an automated framework that can help identify security assets for a design at the register-transfer level (RTL). We introduce a set of metrics into SAIF to perform comprehensive vulnerability analysis and identify security assets that are prone to specific vulnerabilities. Finally, we report our findings on the effectiveness of SAIF for various open-source hardware designs and the National Institute of Standards and Technology (NIST) lightweight crypto designs. We show that SAIF can automatically identify critical security assets in a design with high accuracy and performance. Moreover, we analyze the security implications of the identified secondary assets to show their importance in presilicon se
Semi-autonomous (SA) systems face the Challenge of determining which source to prioritize for control, whether it is from the human operator or the autonomous controller, especially when they conflict with each other....
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Semi-autonomous (SA) systems face the Challenge of determining which source to prioritize for control, whether it is from the human operator or the autonomous controller, especially when they conflict with each other. While one may design an SA system to default to accepting control from one or the other, such design choices can have catastrophic consequences in safety-critical settings. For instance, the sensors an autonomous controller relies upon may provide incorrect information about the environment due to tampering or natural fault. On the other hand, the human operator may also provide erroneous input. To better understand the consequences and resolution of this safety-critical design choice, we investigate a specific application of an SA system that failed due to a static assignment of control authority: the well-publicized Boeing 737-MAX maneuvering characteristics augmentation system (MCAS) that caused the crashes of Lion Air Flight 610 and Ethiopian Airlines Flight 302. First, using a representative simulation, we analyze and demonstrate the ease by which the original MCAS design could fail. Our analysis reveals the most robust public analysis of aircraft recoverability under MCAS faults, offering bounds for those scenarios beyond the original crashes. We also analyze Boeing's updated MCAS and show how it falls short of its intended goals and continues to rely upon on a fault-prone static assignment of control priority. Using these insights, we present SA-MCAS, a new MCAS that both meets the intended goals of MCAS and avoids the failure cases that plague both MCAS designs. We demonstrate SA-MCAS's ability to make safer and timely control decisions of the aircraft, even when the human and autonomous operators provide conflicting control inputs.
By designing a proper electromagnetic constraint within a memristor, and introducing it into a dynamical system with the increase of dimension, a class of memristive chaotic systems with 2-D offset boosters is constru...
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By designing a proper electromagnetic constraint within a memristor, and introducing it into a dynamical system with the increase of dimension, a class of memristive chaotic systems with 2-D offset boosters is constructed. One offset constant directly applies offset boosting of a system variable while the other modifies the offset of two variables simultaneously. Furthermore, when the derived structure satisfies a specific feedback balance law, the property of total amplitude control can be obtained. The circuit implementation is consequently realized and the results are in line with the theoretical analysis.
With the continuous improvement of automation level in modern production lines, the application of robotic arms is becoming more and more widespread, greatly reducing the labor intensity of workers and also lowering l...
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Jointly sponsored by ACM and ieee, the International conference on computer-aideddesign (ICCAD) is a premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technolog...
Jointly sponsored by ACM and ieee, the International conference on computer-aideddesign (ICCAD) is a premier forum to explore new challenges, present leading-edge innovative solutions, and identify emerging technologies in the electronic design automation (EDA) research areas. ICCAD covers the full range of computer-aideddesign (CAD) topics-from the device and circuit levels up through the system level, as well as post-CMOS design.
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