检索结果-内蒙古大学图书馆

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Zhou, Yuejia Huang, Weiqin Zhu, Runteng Huang, Ru Tang, Kechao Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China

ISBN: (纸本)9798350388138;9798350388145

Multi-level cell (MLC) ferroelectric FETs (FeFETs) encounter the critical reliability challenges of poor device uniformity and limited endurance. In this work, a holistic strategy leveraging gate stack engineering and optimal write voltage pulses was proposed to co-optimize the uniformity and endurance of FeFETs. By inserting a thin Al2O3 layer in the middle of the ferroelectric Zr-doped HfO2 (HZO) layer, the device-to-device variation is suppressed due to grain size reduction, and gate leakage is effectively blocked to prevent early breakdown. Writing scheme is also optimized by applying voltage pulses with larger magnitude and shorter width, which is found to benefit both the uniformity and endurance. The combined device structure and write scheme optimization reduces the average memory states variation by 36% for a reliable 2 bit MLC, and enables a state-of-the-art endurance of more than 10(9) cycles.

关键词： multi-level cell (MLC) FeFET uniformity endurance pulse scheme

来源：评论

学校读者我要写书评

暂无评论

A 6.3 dBm 258-314 GHz Power Amplifier using a Broadband 8-way SQWL Power Combiner in 130-nm SiGe BiCMOS Technology 50

A 6.3 dBm 258-314 GHz Power Amplifier using a Broadband 8-wa...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Fu, Shouqing Li, Shuyang Li, Xingcun Chen, Wenhua Tsinghua Univ Dept Elect Engn Beijing Peoples R China Sanechips Technol Co Ltd Analog Design Dept Shenzhen Peoples R China State Key Lavoratory Mobile Network & Mobile Mult Shenzhen Peoples R China

ISBN: (纸本)9798350388138;9798350388145

In this paper, a 258-314 GHz power amplifier fabricated in a 130nm SiGe BiCMOS technology with f(t)/f(max)=350/450 GHz is presented. The PA employs 4 cascode amplification stages and the inductance gain-boosting method. A broadband 8-way subquarter-wavelength power combiner with compensated stepped-impedance transmission lines (TLs) is proposed to achieve wideband matching and power combining simultaneously. The circuit exhibits a peak gain of 15 dB with 56 GHz 3 -dB bandwidth. The maximum output power and OP-1dB are 63 dBm and 4.5 dBm at 270 GHz. It consumes 506 mW DC power and realizes a maximum PAE of 0.8%. The bandwidth and output power of this PA have both reached the leading level in 130-nm SiGe BiCMOS with f(max) less than 500 GHz.

关键词： power amplifier (PA) gain-boosting broadband power combiner subquarter-wavelength (SQWL) balun

来源：评论

学校读者我要写书评

暂无评论

A Novel Ferroelectric FET based Multibit Content Addressable Memory with Dynamic and Static Modes for Energy-Efficient Training and Inference 50

A Novel Ferroelectric FET based Multibit Content Addressable...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Xu, Weikai Luo, Jin Fu, Boyi Chen, Zerui Fu, Zhiyuan Wang, Kaifeng Huang, Qianqian Huang, Ru Peking Univ Sch Integrated Circuits Beijing 100871 Peoples R China Beijing Adv Innovat Ctr Integrated Circuits Beijing 100871 Peoples R China Chinese Inst Brain Res Beijing 102206 Peoples R China

ISBN: (纸本)9798350388138;9798350388145

In this work, a novel multibit content addressable memory (CAM) based on complementary ferroelectric FET (FeFET) with split-gate, enabling both dynamic and static modes, is proposed and experimentally demonstrated for the first time. For dynamic CAM (DCAM), by utilizing the complementary polarity engineering and the non-destructive readout of n/p-type FeFET, only single storage capacitor and single search signal are required for dynamic entry storage and dynamic query searching, enabling reduced hardware cost and power consumption. Moreover, by further utilizing the split-gate engineering of FeFET, the proposed dynamic CAM supports additional in-situ multibit expansion for high-accuracy training. For static CAM (SCAM), by utilizing the non-volatile multilevel ferroelectric polarization for static entry storage, the proposed CAM can also support static binary and multibit CAM modes with single static search signal. Based on the proposed dual-mode CAM design, where the DCAM mode with update-frequent capability for training and the SCAM mode with long retention for inference, the image recognition tasks are demonstrated with high accuracy and significant improvement in speed and energy-efficiency over GPU, along with the lowest write and search energy consumption compared with other state-of-the-art CAM designs, showing its great potential for area- and energy-efficient machine learning.

关键词： FeFET dynamic CAM static CAM in-memory-searching machine learning

来源：评论

学校读者我要写书评

暂无评论

A 7.3mW 200MHz-BW 4-element Passive-Beamforming Continuous-Time ΔΣ ADC with >30dB Spatial Interferer Suppression 50

A 7.3mW 200MHz-BW 4-element Passive-Beamforming Continuous-T...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Schalk, Remco van Mourik, Patrick Liu, Qilong Bajoria, Shagun Kong, Wei Radulov, Georgi Breems, Lucien Eindhoven Univ Technol Integrated Circuits Grp Eindhoven Netherlands NXP Semicond RFP BL Eindhoven Netherlands

ISBN: (纸本)9798350388138;9798350388145

This paper proposes a novel BF-Delta Sigma M concept, which integrates passive vector modulators within the AM loop filter to suppress spatial blockers and hence greatly reduce the dynamic range requirements of the ADC. To enhance phased-array receiver performance, a CT-Delta Sigma M with embedded R-2R based vector modulators as feed-in coefficients is proposed. Resistive vector modulators can provide accurate phase shifting and amplitude scaling, enabling beam-steering and null-steering. This 4-element 40nm CMOS BF-Delta Sigma M achieves >30dB suppression of interferers up to three spatial interferers, 200MHz-bandwidth and >70dB spatial blocker DR with only 7.3mW. The BF-Delta Sigma M obtains 7fJ/cs and 177dB BF-ADC equivalent Walden FoM and Schreier FoM.

关键词： Analog-digital conversion Beam steering Delta-sigma modulation Phase shifters Phased arrays Receivers

来源：评论

学校读者我要写书评

暂无评论

Reconfigurable Si Field-Effect Transistors With Symmetric On-states Enabling Adaptive Complementary and Combinational Logic

引用

ieee TRANSACTIONS ON electron devices 2024年第2期71卷 1302-1307页

作者： Wind, Lukas Fuchsberger, Andreas Demirkiran, Ozgur Vogl, Lilian Schweizer, Peter Maeder, Xavier Sistani, Masiar Weber, Walter M. TU Vienna Inst Solid State Elect A-1040 Vienna Austria Swiss Fed Labs Mat Sci & Technol Lab Mech Mat & Nanostruct CH-3602 Thun Switzerland

Reconfigurable field-effect transistors (RFETs), combining n-and p-type operation in a single device, have already shown promising simulation results for enhancing performance and functionality in conventional devices and further enabling novel adaptive computing concepts. With recent advances in the formation of high-quality monolithic and single-crystalline Al-Si Schottky contacts providing a reproducible way to fabricate RFETs with highly symmetric n-and p-type operation, we are now able to demonstrate their integration in fundamental complementary and combinational logic circuits. In this regard, we show an inverter, as well as NAND/NOR and XOR/XNOR gates, capable of dynamically run-time switching their operation mode, while simultaneously reducing transistor count compared to conventional circuits with static transistors. Importantly, we could demonstrate their reliable operation using only fully symmetric supply voltages while providing a full output swing. Their robust operation is verified by analyzing their noise margins, stability to input voltage variations, and transient behavior. Most notably, the presented device concept and the Al-Si material system are potentially compatible with the state-of-the-art complementary metal-oxide-semiconductor (CMOS) processing technology, paving the way for future hybrid reconfigurable-CMOS circuits with improved functional density and energy efficiency.

关键词： Combinational logic reconfigurable field-effect transistors (RFETs) reconfigurable transistor Schottky barrier field-effect transistor (SBFET) silicon-on-insulator (SOI)

来源：评论

学校读者我要写书评

暂无评论

A 20 x 20-Pixels Mixed-Signal Silicon Photomultiplier with On-Chip Adjustable Front-End for Background Light Rejection 50

A 20 x 20-Pixels Mixed-Signal Silicon Photomultiplier with O...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Morciano, Arianna Gandola, Massimo Perenzoni, Matteo Gasparini, Leonardo Radogna, Antonio Vincenzo D'Amico, Stefano Univ Salento Dept Engn Innovat Lecce Italy Fdn Bruno Kessler FBK Trento Italy Sony Semicond Solut Europe Trento Italy Univ Salento Dept Expt Med Lecce Italy

ISBN: (纸本)9798350388138;9798350388145

This paper presents a mixed-signal Silicon Photomultiplier (msSiPM) front-end for background light rejection. Each Silicon Photon Avalanche Diode (SPAD) output signal is digitized into a signal pulse with possibility of tuning fall time, in order to maximize the laser signal compared to background light. Then, all analog current signals are collected by a transimpedance amplifier (TIA) which provides an output voltage proportional to the number of triggered SPAD. As the architecture is mostly digital, msSiPM consumes a low static power consumption, equal to 428 mu W. The receiver is composed by a 20x20-pixel array, and it is fabricated in a 0.11 mu m CMOS technology reaching a pixel fill factor (FF) equal to 32.8%. Measurements have been carried out under different background photon fluxes, one stronger and one weaker, corresponding to 2.15 and 4.15 GPhotons/s at the SiPM, demonstrating strong background rejection in both conditions.

关键词： SPAD SiPM CMOS integrated circuits Pulse Shaper SNR SBR Background Rejection Laser Pulse

来源：评论

学校读者我要写书评

暂无评论

Analysis of TID Effects on the Threshold Voltage and Breakdown Voltage of 100-V Split-Gate Trench VDMOS

引用

ieee TRANSACTIONS ON electron devices 2024年第6期71卷 3483-3489页

作者： Wang, Yuan Liu, Tao Dai, Zhijiang Tao, Jingyu Qian, Lingli Wu, Hao Hu, Shengdong Chongqing Univ Sch Microelect & Commun Engn Chongqing 400030 Peoples R China Sichuan Inst Solid State Circuits Chongqing 401332 Peoples R China

This article investigates the impact of total ionizing dose (TID) on 100-V split-gate trench vertical double-diffused MOSFETs (SGT VDMOS). The experimental results for both ON-state and OFF-state irradiation are explored, focusing on the shift in threshold voltage ( V-th) and breakdown voltage (BV). The physical mechanisms responsible for BV shifts after ON-state irradiation and OFF-state irradiation are analyzed and verified using Sentaurus TCAD with two distinct positive oxide trapped charge (N-ot) models. The analysis reveals that BV shifts are attributable to the redistribution of the electric field due to positive oxide trapped charges induced by TID, which suppress depletion in the drift region. To mitigate this issue, a radiation-hardened SGT VDMOS with double p-pillars is proposed. The introduction of double p-pillars significantly improves TID tolerance on BV by facilitating an enhanced depletion effect. The effectiveness of this proposed solution has been analyzed in this study.

关键词： Radiation effects Electric fields Threshold voltage Split gate flash memory cells Logic gates Degradation Scanning electron microscopy Breakdown voltage (BV) OFF-state irradiation ON-state irradiation split gate total ionizing dose (TID)

来源：评论

学校读者我要写书评

暂无评论

BEoL Varactors Based on HfO2/ZrO2 Superlattice for mmWave Applications 50

BEoL Varactors Based on HfO2/ZrO2 Superlattice for mmWave Ap...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Abdulazhanov, Sukhrob Le, Quang Huy Lehninger, David Suenbuel, Ayse Kaempfe, Thomas Gerlach, Gerald Fraunhofer IPMS Ctr Nanoelect Technol D-01109 Dresden Germany Tech Univ Dresden Inst Solid State Elect D-01069 Dresden Germany

ISBN: (纸本)9798350388138;9798350388145

In this study, we demonstrate for the first time the mmWave performance of a thin-film metal-ferroelectric-metal (MFM) varactor utilizing [HfO2/ZrO2](4) superlattice (SL), integrated into the Back-End-of-Line (BEoL) of 180 nm HV SOI technology. At low frequencies, the varactor exhibits tunability of 28.9% and 24% before and after wake-up cycling, respectively, using voltage sweeps ranging from -2.4 V to 1 V. During mmWave characterization spanning from 1 GHz to 60 GHz, the device demonstrates consistent tunability of 19.6%-18.8% and 17% - 15.7% before and after wake-up, respectively. Moreover, comparison with a standard Hf0.5Zr0.5O2 (HZO) varactor, integrated within a similar technology, reveals the superior performance of superlattice-based varactor, highlighting its immense potential for mmWave applications.

关键词： ferroelectric MFM varactor superlattice Back-End-of-Line tunability loss tangent Q-factor

来源：评论

学校读者我要写书评

暂无评论

Paralleled SiC MOSFETs Circuit Breaker With a SiC MPS Diode for Avalanche Voltage Clamping

IEEE OPEN JOURNAL OF POWER ELECTRONICS

引用

ieee OPEN JOURNAL OF POWER electronICS 2024年 5卷 392-401页

作者： Takamori, Taro Wada, Keiji Saito, Wataru Nishizawa, Shin-ichi Tokyo Metropolitan Univ Dept Elect Engn & Comp Sci Tokyo 1910065 Japan Kyushu Univ Res Inst Appl Mech Fukuoka 8168580 Japan

This paper proposes a solid-state circuit breaker comprising silicon carbide (SiC) MOSFETs and a SiC diode, based on the principle of avalanche voltage clamping. The key challenge in realizing a solid-state circuit breaker lies in reducing conduction loss. A parallel connection of power semiconductor devices is the suitable configuration that can meet these requirements. However, in such a configuration, the current balance during cutoff operation may be affected by the variation in the breakdown voltage characteristics of the power semiconductor devices. To address this issue, the proposed circuit breaker employs clamping with a SiC merged pin Schottky (MPS) diode, with high avalanche tolerance and robust characteristics under repetitive avalanche events. The effectiveness of the proposed solid-state circuit breaker is validated through experiments conducted in an unclamped inductive switching (UIS) test circuit using a 400-V, 50-A DC distribution system. Eventually, the demonstrations indicate that the SiC diode clamping method contributes to more compact implementations for solid-state circuit breakers.

关键词： Silicon carbide Breakdown voltage Clamps MOSFET solid state circuits Semiconductor diodes Steady-state Avalanche breakdown clamping component parallel connection silicon carbide solid-state circuit breaker unclamped inductive switching

来源：评论

学校读者我要写书评

暂无评论

A 273μW 0.34mm² Efficient CRYSTALS-KYBER Processor for PQC Towards Edge Computing 50

A 273μW 0.34mm<SUP>2</SUP> Efficient CRYSTALS-KYBER Process...

引用

50th ieee European solid-state electronics Research conference (ESSERC)

作者： Li, Aobo Lu, Jiahao Liu, Dongsheng Yang, Shuo Huang, Tianze Zhang, Jiaming Xiong, Siqi Yang, Chenjun Li, Xiang Huazhong Univ Sci & Technol Sch Integrated Circuits Wuhan 430074 Peoples R China

ISBN: (纸本)9798350388138;9798350388145

Due to the existence of store-now-decrypt-later attack strategies, the world urgently needs alternative post-quantum cryptographic (PQC) solutions. The lattice-based PQC algorithm CRYSTALS-KYBER (Kyber) is widely recognized as a standardization for its good performance and security. We propose a compact and efficient Kyber processor architecture for resource-constrained edge computing. Lightweight SHA-3 with half-fold keccak and samplers provide high-quality discrete distribution coefficient generation with energy-saving features. Modular arithmetic elements are configured as variable structures for different types of fast polynomial computations. The proposed architecture is fabricated under 40 nm process, and ASIC results show that the processor occupies 0.34 mm(2) and 253 k equivalent gates with minimum 7 KB memory and the lowest power 273 mu W. Compared to similar works, we reduce the power by 50%, improve the 6.1x energy optimization, 8x area and achieve state-of-the-art in energy efficiency.

关键词： Post-quantum cryptography CRYSTALS-KYBER low power energy-efficient

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：