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A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET 72

A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET

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72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Shen, Junhua Chen, Wei-Hung Burlinqame, Efram Weinreich, Stephen Elliott, Michael McCracken, Stuart Kenney, Jack Brunsilius, Janet Korkmaz, Anil Fontecilla, Enrique Alvarez Rakuljic, Nevena Mehta, Ushma Sullivan, Ben Scuteri, Jeremy Luu, Bac Binh Nichols, Mitchell Martin, Dara Sullivan, Richard Debolt, Daniel Kapusta, Ron Analog Devices WilmingtonMA United States Analog Devices SomersetNJ United States Analog Devices San DiegoCA United States Analog Devices AustinTX United States Analog Devices DurhamNC United States Analog Devices Limerick Ireland

ISBN: (纸本)9798331541019

Time-interleaved (TI) SAR ADC architecture is preferred in the low-to-moderate resolution space to achieve >GS/s speed for its excellent power and area efficiency [1-3], as well as to reduce design complexity, which may lead to fewer tape-outs and faster product development. High-speed and medium-resolution ADCs are used in applications like wireless communications and portable instrumentation. Emerging applications such as RF direct sampling in fully digital phased arrays require similarly high sample rates, but they also demand RF SNDR beyond 45dB. In [4-6], high-speed SAR ADCs with such SNDR were reported. Often, 3 or more supply domains are utilized and tailored for optimized analog performance, as in [4, 5], making integration into a larger transceiver system difficult. In this paper, we present a 12GS/s 16× TI SAR ADC that achieves 48.1dB SNDR at 5.3GHz input, consumes 160mW from integration-friendly 1.8V and 0.8V standard process supplies and occupies 0.25mm2 in 16nm FinFET. © 2025 ieee.

关键词： FinFET

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Performance Evaluation of GaN and SiC solid state devices for Circuit Breaker Application 2nd

Performance Evaluation of GaN and SiC Solid State Devices fo...

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2nd International conference on Smart Electrical Grid and Renewable Energy, SEGRE 2024

作者： Xu, Yang Zhang, Miaoran Zhang, Wenxin Xu, Peichao Department of Electrical and Electronic Engineering Xi’an Jiaotong-Liverpool University Suzhou China

ISBN: (纸本)9789819619641

Compared to AC transmission systems, DC transmission systems have become an attractive research topic and practical solution due to their higher efficiency, translating into significant energy savings and reduced operational costs over long distances. This advantage, however, brings challenges, particularly in protection systems where high-speed and precise protection is critical, emphasizing the importance of circuit breakers. Circuit breakers ensure the safety and reliability of power systems by quickly isolating faults and preventing damage. In the context of DC transmission, solid-state circuit breakers, known for their fast response times and reliability, are promising. This paper compares the performance of two solid-state devices—silicon (Si) and gallium nitride (GaN)—under the same bus voltage in different circuits. Each material’s unique characteristics impact its DC application performance. Silicon (Si) devices are widely used due to mature technology and low cost. However, silicon carbide (SiC) devices offer lower conduction losses and higher efficiency at higher voltages, while GaN devices are known for high electron mobility and efficiency, though they are more expensive and less mature technologically. By discussing criteria for DC solid-state circuit breakers (such as switching speed, thermal management, and reliability), this paper deduces the pros and cons of each device and analyzes their potential in DC systems. Simulation results show that while Si devices are cost-effective, SiC and GaN devices provide superior efficiency and speed, albeit at higher costs. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2025.

关键词： Gallium nitride

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A 91.25% Peak Power-Conversion-Efficiency Capacitive Power-Management IC Supporting up to 5.68mJ Burst Energy Delivery Using a Single External Capacitor for mm-Scale IoT Applications 72

A 91.25% Peak Power-Conversion-Efficiency Capacitive Power-M...

引用

72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Fang, Qishen Li, Feiyu Martins, Rui P. Law, Man-Kay University of Macau China Instituto Superior Tecnico University of Lisboa Lisbon Portugal

ISBN: (纸本)9798331541019

As Internet of Things (IoT) devices continue to shrink in size, the limited available system energy is becoming a major bottleneck. Even though the system power of miniaturized IoT devices can be reduced down to the sub-μW level, the peak system power consumption (e.g., during wireless data transmission) can increase up to the mW level. Despite the enhanced energy density and safety, the existing mm-scale solid-state batteries still fall short in their load driving capability due to the high internal resistance (e.g., RIN~200Ω with a peak pulse energy of 4.8μJ in [1]), directly limiting the burst system power requirement. To increase the output driving capability, the conventional approach is to employ a large storage capacitor CSTO [2]. However, due to the lack of reconfiguration flexibility of CSTO, only ~2% of the stored energy can be utilized to ensure a negligible supply voltage drop. Even though [3] can increase the extracted energy to 215μJ, the requirement of an exceedingly large super capacitor CSTO of up to 7.5mF renders such an approach highly inefficient. In [4], the counter-flow approach was proposed to extract up to 70% of the stored energy from 16 on-chip capacitors, which was further enhanced in [5] using two unbalanced on-chip capacitor banks to achieve a peak energy extraction efficiency (EEE) of up to 78.4%. Yet, due to the low density of on-chip storage capacitors, the burst energy delivery capability is still limited (e.g., only 0.87nJ in [5]). To maximize the deliverable energy during burst mode operation without additional passives, we propose to first charge up a single external CSTO to a high voltage (HV), and then continuously draw the stored energy using an on-chip step-up/-down switched-capacitor (SC) converter. As observed in Fig. 31.4.1, considering the derating of capacitors, the stored energy of a commercial 22μF Multi-layer Ceramic Capacitor (MLCC) with a 0603 package exhibits a relatively linear relationship between the stored energ

关键词： solid-state Batteries

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A 13.5μW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS 72

A 13.5μW 35-Keyword End-to-End Keyword Spotting System Feat...

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72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Lee, Hyuk-Jin Pyo, Kyunghoon Jang, Taekwang Seok, Mingoo Cho, Seonghwan KAIST Daejeon Korea Republic of ETH Zürich Zürich Switzerland Columbia University New YorkNY United States

ISBN: (纸本)9798331541019

Modern IT devices offer personalized features that can be customized to individual users. However, keyword spotting (KWS), a feature that is gaining widespread adoption in many personal devices, remains largely non-user-configurable as it is designed for the general public. While user-specific training can enable a personalized KWS system tailored to individual users' accents, the large power consumption and high complexity required in training have hindered its adoption. Thus, existing KWS systems often suffer from missed commands, especially for users with accents, leading to increased energy consumption and an undesirable user experience. Furthermore, existing KWS systems usually recognize only a few words for waking up the device, although future devices are expected to understand a much broader vocabulary to execute various commands. In the recent past, several KWS systems have been proposed [1]-[9] with an emphasis on low-power consumption. Unfortunately, most works only recognize up to ten keywords, and although [1] supports 35 keywords, it suffers from low accuracy (78%) (>150μW) due to the increased complexity. More importantly, none of these systems have user-specific trainability, which leads to poor accuracy for users with accents. In this work, we propose a low-power 35-keyword end-to-end KWS system featuring personalized on-chip training that ensures high accuracy for speakers with different accents. On-chip training also allows the use of a compact convolutional neural network (CNN) and small memory size, thereby saving power and area. The proposed chip also features a compact sine-based convolution [11] with an approximate logarithm function that serves as a low-complexity feature extractor (FE). Fabricated in 28nm CMOS, the proposed KWS system achieves an average accuracy of 92.2% on a 35-keyword accented dataset that is trained and tested on speakers from nine different countries, while consuming 10.93μW during inference and 13.46μW during training

关键词： CMOS integrated circuits

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A 20W CMOS/LDMOS All-Digital Transmitter with Dynamic Retiming and Glitch-Free Phase Mapper, Achieving 68%/62% Peak Drain/System Efficiency 72

A 20W CMOS/LDMOS All-Digital Transmitter with Dynamic Retimi...

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72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Mul, Dieuwert Peter Nicolaas Bootsman, Rob J. Beikmirza, Mohammadreza El Boustani, Ossama Shen, Yiyu Maassen, Daniel Van Velzen, Bart Rousstia, Mohadig Koster, Ronald Gajadharsing, John R. Fritzsch, Thomas Alavi, Morteza De Vreede, Leo C.N. Delft University of Technology Delft Netherlands Ampleon Nijmegen Netherlands Fraunhofer IZM Berlin Germany

ISBN: (纸本)9798331541019

Base stations account for 73% of wireless-operators' energy consumption, mainly dominated by their analog-PA-based TXs [1]. All-digital transmitters (DTXs), leveraging custom low-VT RF-power technologies [2], offer substantial energy savings by using switching operation and completely eliminating quiescent currents. In addition, DTXs enable extreme bandwidths since their circuit topology is frequency-agile up to the (power combining) output-matching network. To date, no high-power, high-efficiency DTX solutions have been reported that offer RF-power levels required for mMIMO base stations (Pavg >3W), with the essential fine-gate segmentation and glitch-free operation to support wideband modulated signals. In this work, an 8-phase multi-phase (MP) DTX upconversion with dynamic retiming and a glitch-free phase-mapper operation is proposed (Fig. 5.8.1). The required output power, resolution, and sampling speed are achieved via a high-density flip-chip DTX approach with a high-speed DTX controller placed on a custom low-VT LDMOS MMIC featuring power switch banks with in-finger gate segmentation (Fig. 5.8.1). © 2025 ieee.

关键词： Flip chip devices

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Session 35 Overview: Implantable and Wearable Biomedical devices

Session 35 Overview: Implantable and Wearable Biomedical Dev...

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ieee International conference on solid-state circuits (ISSCC)

Session 35 Overview: Implantable and Wearable Biomedical devices.

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

Session 35 Overview: Implantable and Wearable Biomedical devices.

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An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz 72

An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscilla...

引用

72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Chen, Jiawen Xu, Kai Siriburanon, Teerachot Staszewski, Robert Bogdan University College Dublin Dublin Ireland King's College London London United Kingdom

ISBN: (纸本)9798331541019

As data-rate requirements in 5G-Advanced and future 6G communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring higher-order modulation schemes and ever-higher throughput. Under the CMOS-limited supply voltage and power-dissipation constraints, the PN in conventional parallel-resonance (PR) LC-tank oscillators is primarily limited by the tank quality factor (Q). To continue the quest for everlower PN, N oscillators can be coupled together for an effective PN reduction of 10log(N) (Fig. 19.4.1, top-right) [1]. However, the practical implementation of multicore oscillators is hampered by 1) mismatches between the cores, which degrades the achievable PN and figure of merit (FoM), and 2) the area-intensive floorplan required when coupling many cores. Series-resonance (SR) LC oscillators have the potential to achieve ultra-low PN with a single-core configuration [2-4]. Nonetheless, several challenges arise when implementing this configuration in CMOS: 1) Realizing a cross-coupled oscillator core that provides current-controlled negative resistance is difficult in CMOS;although, it can be achieved in bipolar technologies with additional diodes (Fig. 19.4.1, bottom-left) to maintain the output voltage amplitude [3];2) four-stage inverter-based SR oscillators (Fig. 19.4.1, bottommiddle) require 4× the power consumption and introduce additional noise from active devices to maintain the oscillation, as each series-LC tank provides a 90° phase shift [4]. Both reported works burn over 300mW. © 2025 ieee.

关键词： CMOS integrated circuits

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A 2-TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with ieee 802.15.4/4z Standards 72

A 2-TRX IR-UWB Transceiver with Shared Antennas Supporting C...

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72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Seok, Hyun-Gi Lee, Jaekeun Kim, Sinyoung Jung, Wonjun Han, Honggul Kim, Junhyeong Kang, Sumin Kim, Chanho Kim, Wonkang Cho, Jongpil Bae, Seungyoung Lee, Yanghoon Kim, Sungbeom Son, Hyeonuk Jang, Junyoung Kim, Taeyeon Cho, Sanguk Cho, Misuk Ahn, Chiyoung Sung, Hyukjun Kim, Wan Oh, Seunghyun Lee, Jongwoo Ko, Hyungjong Kim, Joonsuk Samsung Electronics Hwaseong Korea Republic of

ISBN: (纸本)9798331541019

Unlike received signal-strength-indicator (RSSI)-based localization methodology of Wi-Fi and BLE, which have a distance error of several meters or more [1], impulse-radio ultrawideband (IR-UWB) using narrow pulse width enables accurate distance information within a few centimeters [2]. Additionally, IR-UWB has demonstrated stand-alone radar capabilities [3], enabling expanded radar applications such as child presence detection, augmented reality, and motion sensing. With the expansion of UWB applications, multiple UWB ICs are widely used in various areas such as IoT devices, mobile devices, and automobiles. Consequently, there is growing concern in the market about the potential for these devices to interfere with each other's communication. Furthermore, the channel environment is getting worse as the 6GHz band is becoming increasingly crowded due to both Wi-Fi and cellular New Radio (NR) bands. With the UWB solution of previous works [3,4] only supporting two channels (ch5 and ch9), there are limitations in handling multiple users effectively. To address these issues, UWB technology needs to support multiple channels to make better use of the channel environment. In addition, to minimize the number of antennas, previous works [3-5] have adopted a cost-effective structure that shares TX/RX antennas using RF switches. In [5], external RF switches based on the silicon-on-insulator (SOI) process are used to share TX and RX antennas;however, the use of external RF switches and the system-in-package (SiP) incur additional costs, which can be challenging for mass production. In [3,4], the RF switches are fully integrated using the CMOS process, but the high insertion loss of the internal RF switch increases RX noise figure (NF), leading to degraded sensitivity. © 2025 ieee.

关键词： Silicon on insulator technology

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Session 15 Overview: Neural Interfaces and Edge Intelligence for Medical devices

Session 15 Overview: Neural Interfaces and Edge Intelligence...

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ieee International conference on solid-state circuits (ISSCC)

Session 15 Overview: Neural Interfaces and Edge Intelligence for Medical devices.

ISBN: (数字)9798331541019

ISBN: (纸本)9798331541026

Session 15 Overview: Neural Interfaces and Edge Intelligence for Medical devices.

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A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable 1.2μm-Pitch 50Mpixel Rolling Shutter and 2.4μm-Pitch 12.5Mpixel Global Shutter Modes for Mobile Applications 72

A 3-Stacked Hybrid-Shutter CMOS Image Sensor with Switchable...

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72nd ieee International solid-state circuits conference, ISSCC 2025

作者： Shim, Heesung Kim, Seung-Sik Seo, Min-Woong Park, Sangsu Kwon, Hyukbin Kim, Yongjun Lee, Sanggwon Park, Sungbong Bae, Daehee Koo, Si Gyoung Ito, Masamichi Jeon, Jae-Hoon Yoon, Sol Byun, Sung-Jae Kim, Sangyoon Kim, Kwansik Cho, Gihwan Lee, Joonho Kim, Tekyou Jun, Sungjae Lee, Jae-Kyu Moon, Chang-Rok Song, Jaihyuk Samsung Electronics Hwaseong Korea Republic of

ISBN: (纸本)9798331541019

In recent years, the development of CMOS image sensors (CISs), especially for mobile applications, has focused on pixel scaling to achieve ultra-high pixel resolutions of over 50 megapixels (Mp) [1]. In addition, various efforts have been actively devoted to strengthen the functionality of image sensors through advanced stacking process technologies, e.g., rolling shutter (RS) CIS with event vision sensors (EVS) for enhancing imaging quality [2]. A global shutter (GS) CIS is an excellent alternative to overcome the limitations of conventional RS CISs. GS CISs for mobile applications can create value as follows: 1) GS CISs can get distortion-free images when capturing fast-moving objects;2) GS CISs don't suffer from flicker-related artifacts because all pixels are exposed at the same time, while RS CISs require a tradeoff between a long exposure time such as 1/60 or 1/120 seconds to prevent the flicker phenomena and a short one to avoid image blurring;and 3) Flash banding caused by sudden camera flashes can be avoided. We believe that the aforementioned advantages of GS CISs have the potential to offer a valuable user experience in mobile devices. Despite these features, voltage-domain GS CISs exhibit a higher random noise (RN) level, generated by sampling capacitors, compared to RS CISs, which limits their applicability. Therefore, a hybrid shutter (HS) CIS capable of operating in both modes, RS and GS, is developed to maximize the benefits of each. © 2025 ieee.

关键词： CMOS integrated circuits

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