检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

529 篇 会议
10 篇 期刊文献

馆藏范围

539 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

396 篇 工学
- 261 篇 电气工程
- 151 篇 电子科学与技术（可...
- 119 篇 计算机科学与技术...
- 59 篇 材料科学与工程（可...
- 52 篇 信息与通信工程
- 52 篇 软件工程
- 35 篇 机械工程
- 27 篇 仪器科学与技术
- 27 篇 化学工程与技术
- 26 篇 动力工程及工程热...
- 21 篇 控制科学与工程
- 17 篇 冶金工程
- 16 篇 石油与天然气工程
- 13 篇 光学工程
- 10 篇 航空宇航科学与技...
- 7 篇 建筑学
- 6 篇 土木工程
- 5 篇 力学（可授工学、理...
- 4 篇 轻工技术与工程
- 4 篇 核科学与技术
104 篇 理学
- 72 篇 物理学
- 25 篇 化学
- 19 篇 数学
- 4 篇 生物学
24 篇 管理学
- 23 篇 管理科学与工程(可...
- 7 篇 工商管理
8 篇 医学
- 5 篇 临床医学
- 5 篇 特种医学
5 篇 经济学
- 5 篇 应用经济学
3 篇 军事学

主题

61 篇 multichip module...
25 篇 silicon
25 篇 multi-chip modul...
24 篇 packaging
23 篇 microprocessor c...
22 篇 switches
20 篇 substrates
19 篇 electronics pack...
18 篇 silicon carbide
16 篇 assembly
13 篇 costs
13 篇 integrated circu...
12 篇 radio frequency
11 篇 multichip module
11 篇 logic gates
11 篇 inductance
10 篇 bonding
10 篇 finite element a...
10 篇 ceramics
9 篇 reliability

机构

4 篇 univ alabama dep...
4 篇 hypres inc elmsf...
3 篇 stanford univ st...
2 篇 shanghai aerospa...
2 篇 marvell burnaby
2 篇 marvell
2 篇 jst tsukuba ibar...
2 篇 sun microsystems...
2 篇 caltech jet prop...
2 篇 georgia inst tec...
2 篇 tyndall natl ins...
2 篇 guilin univ elec...
2 篇 univ alabama dep...
2 篇 micromodule syst...
2 篇 center for integ...
2 篇 fraunhofer izm
2 篇 micromodule syst...
2 篇 shenzhen smartch...
2 篇 academy of infor...
2 篇 keio university ...

作者

4 篇 yorozu shinichi
4 篇 miyazaki toshiyu...
4 篇 lemmon andrew n.
3 篇 paolo mattavelli
3 篇 luo le
3 篇 dai wayne wei-mi...
3 篇 lu hua
3 篇 boroyevich dusha...
3 篇 wang li
3 篇 brian hughes
3 篇 ning puqi
3 篇 castellazzi albe...
3 篇 pence w.e.
3 篇 bailey chris
3 篇 dushan boroyevic...
3 篇 lemmon andrew
3 篇 hughes brian
3 篇 mattavelli paolo
2 篇 zhang tao
2 篇 kameda yoshio

语言

529 篇 英文
7 篇 中文
3 篇 其他

检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是1-10 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A multi-SCALE FEATURE FUSION NETWORK FOR chip SURFACE DEFECT DETECTION 31

A MULTI-SCALE FEATURE FUSION NETWORK FOR CHIP SURFACE DEFECT...

引用

2024 International conference on Image Processing

作者： Ren, Haoang Tian, Mengke Zhang, Guanwen Zhou, Wei Northwestern Polytech Univ Sch Elect & Informat Xian Peoples R China Beijing Microelect Technol Inst Beijing 100076 Peoples R China

ISBN: (纸本)9798350349405;9798350349399

chip surface defect detection plays a crucial role in semiconductor manufacturing and the electronics industry. However, chip surface defects have relatively tiny defect areas and complex defect features make the chip surface defect detection task low in accuracy. In this paper, we propose a multi-scale feature fusion network based on encoder-decoder architecture to solve this challenge. Particularly, we propose a Residual Feature Fusion Attention module (RFFAM) and an Intersection over Union Loss for Defect with Auxiliary Bounding Box (DA-IoU), and we incorporate a Transformer Prediction Head (TPH) for the network. Additionally, in order to solve the problem of the shortage of chip surface defect datasets, this paper proposes a chip surface defect dataset containing four defect categories. The experimental results show that the method not only improves the detection accuracy but also maintains a small number of parameters, satisfying the engineering requirements of chip surface defect detection.

关键词： chip surface defect detection attention module multi-scale feature fusion auxiliary bounding box

来源：评论

学校读者我要写书评

暂无评论

Condition Monitoring the Inhomogeneous Thermal Fatigue of multi-chip IGBT module Based on the Natural Frequency of Thermal Network 10

Condition Monitoring the Inhomogeneous Thermal Fatigue of Mu...

引用

10th ieee International Power Electronics and Motion Control conference, IPEMC 2024 ECCE Asia

作者： Zhang, Jun Shen, Huixian Sun, Pengju Ma, Xing Hohai University School of Electrical and Power Engineering China Chongqing University School of Electrical Engineering China Chongqing Electric Power Research Institute State Grid China

ISBN: (纸本)9798350351330

The inhomogeneous thermal fatigue is easily produced during the operation of multi-chip IGBT module. Condition monitoring the health status of multi-chip IGBT module can provide guidance for the regular maintenance of power converter and reduce the cost of unscheduled downtime. This paper proposed to use the natural frequency of thermal network as the characteristic quantity, and realized the condition monitoring of multi-chip IGBT module. We show that the natural frequencies increase with the degradation of multiple parallel devices. Simulations and experiments were performed to verify the proposed method. In addition, this method is able to quantify the degree of inhomogeneous thermal fatigue, which then can be used to analyze the current distribution between the parallel devices. © 2024 ieee.

关键词： Condition monitoring

来源：评论

学校读者我要写书评

暂无评论

multi-chip Stacked Memory module Development using chip to Wafer (C2W) Hybrid Bonding for Heterogeneous Integration Applications 74

Multi-Chip Stacked Memory Module Development using Chip to W...

引用

ieee 74th Electronic Components and Technology conference (ECTC)

作者： Sekhar, Vasarla Nagendra Kumar, Mishra Dileep Tippabhotla, Sasi Kumar Rao, B. S. S. Chandra Daniel, Ismael Cereno Chong, Ser Choong Rao, Vempati Srinivasa ASTAR Inst Microelect IME 2 Fusionopolis WayInnovis 08-02 Singapore 138634 Singapore

ISBN: (纸本)9798350375985;9798350375992

The present study focuses on multi-chip stacked memory module development, and it encompasses a comprehensive overview of critical aspects, key learnings, encountered challenges, and the corresponding mitigation strategies. It initiates the formulation of test vehicle designs and progresses through mechanical simulations, wafer fabrication, and meticulous materials selection. It delves into the complexities of chip-to-wafer (C2W) hybrid bonding and assembly processes for hybrid bonding module development. The test vehicle design is tailored to accommodate a substrate along with two logic and memory stacked test chips. Extensive finite element analysis (FEA) simulations are conducted to comprehend and enhance the integrity of bonded dielectric layers and Cu pads, considering diverse designs, materials, and process parameters of the C2W-HB processes. For test chip stacking, chip design, dielectric materials selection, wafer fabrication methodology, chip warpage, and hybrid bonding approach play a critical role. The process integration, dielectric stack, and dielectric deposition recipes have been fine-tuned to limit the thin memory chip warpage to less than 60 mu m, ensuring successful chip stacking and hybrid bonding. Several fabrication processes and modules have been optimized to fabricate memory wafers with double-side hybrid bonding pads and TSV structures using low-temperature dielectric materials on the backside. Following C2W hybrid bonding and molding, under-bump metallization (UBM) fabrication is established on the substrate wafer backside for electrical testing and board-level assembly purposes. Electrical testing outcomes and yields at the UBM match those obtained from wafer front-side testing.

关键词： chip-to-wafer hybrid bonding multi-chip stacking finite element analysis thin wafer handling process challenges mitigation plans

来源：评论

学校读者我要写书评

暂无评论

Array Packaging with integrated Mirrors for High Power multi-chip UVC-LED modules 10

Array Packaging with integrated Mirrors for High Power Multi...

引用

10th ieee Electronics System-Integration Technology conference (ESTC)

作者： Hansen, Ulli Hu, Xiaodong Maus, Simon Gyenge, Oliver MSG Lithoglas GmbH Dresden Germany

ISBN: (纸本)9798350390377;9798350390360

UVC-LEDs are gaining increasing importance in disinfection applications for water, surface and air disinfection. The efficiency and quality of such devices is developing quickly and due to small size, instant light emission and low power consumption these LEDs enable a large variety of new applications like e.g., point-of-use disinfection of drinking water in off-grid areas. The Lithoglas packaging solution utilizes miniaturized mirror elements placed close to the LED, which helps to significantly increase light output and improve the thermal performance of the packaged LEDs. UVC-LED modules with high power can be achieved by placing several LED chips into one package. This paper describes a novel solution using integrated mirror arrays to enable very efficient high-power multi-chip packages with each LED optically insulated by a miniaturized mirror structure for optimal optical performance.

关键词： UVC-LED reflector package multi-chip package light extraction heat dissipation high-power module

来源：评论

学校读者我要写书评

暂无评论

Thermal-Aware SoC Macro Placement and multi-chip module Design Optimization with Bayesian Optimization 73

Thermal-Aware SoC Macro Placement and Multi-chip Module Desi...

引用

ieee 73rd Electronic Components and Technology conference (ECTC)

作者： Molter, Michael Kumar, Rahul Koller, Sonja Bhatti, Osama Waqar Ambasana, Nikita Rosenbaum, Elyse Swaminathan, Madhavan Univ Illinois Urbana IL 61801 USA Penn State Univ University Pk PA 16802 USA Intel Deutschland GmbH Neubiberg Germany Georgia Inst Technol Atlanta GA 30332 USA Intel India DCAI DPE Chennai Tamil Nadu India

ISBN: (纸本)9798350334982

The effect of temperature on the reliability and performance of electrical components and integrated circuits warrants the inclusion of thermal considerations in the early stages of electronic system design. However, the many design parameters involved in the design of the package and the die or macro placement, along with the use of expensive thermal simulations, poses difficulty for conventional optimization algorithms. To overcome that hurdle, this work proposes an efficient Bayesian optimization algorithm which is demonstrated for two early-stage design problems. First, the proposed algorithm is used for the thermal-aware placement of macros with a variable aspect ratio. Second, the proposed Bayesian optimization algorithm is utilized in a two-stage process to optimize the die placement and the package design parameters of a multi-chip module.

关键词： Bayesian optimization Macro Placement Floor-planning Die placement multi-chip module

来源：评论

学校读者我要写书评

暂无评论

AdCoalescer: An Adaptive Coalescer to Reduce the Inter-module Traffic in MCM-GPUs

AdCoalescer: An Adaptive Coalescer to Reduce the Inter-Modul...

引用

1st International conference on Smart Energy Systems and Artificial Intelligence (SESAI)

作者： Zhang, Xu Zhang, Guangda Wang, Lu Zhao, Xia Acad Mil Sci Def Innovat Inst Beijing Peoples R China

ISBN: (纸本)9798350364613;9798350364606

The push for greater computing capabilities has led to the development of multi-chip-module GPUs (MCM-GPUs), advancing parallel processing potential. Unfortunately, MCM-GPUs encounter a notable challenge, i.e., the performance bottleneck due to the inter-module network. Within MCM-GPUs, a large proportion of memory accesses by Streaming multiprocessors (SMs) must traverse this inter-module network to access remote memory, encountering bandwidth constraints and increased latency-. This is in contrast to the efficient network-on-chip designs in single-module GPU architectures. In MCM-GPUs, we identify significant data access redundancy among SMs within a GPU module which can be coalesced to reduce the network pressure. However, directly coalescing by recording every memory address is inefficient, as a significant number of memory requests are directed to private data addresses, thus underutilizing the hardware resources. To address this challenge, we introduce the Adaptive Coalescer (AdCoalescer). AdCoalescer is a novel framework designed to adaptively coalesce memory requests from different SMs sent to the same cache lines, especially those likely to be concurrently accessed by multiple SMs. Our evaluations validate AdCoalescer design in alleviating the challenges posed by the inter-module network. On average, AdCoalescer achieves a performance improvement of 22.5% (with up to 71.9% improvement) compared to traditional designs with minimal hardware cost.

关键词： multi-chip-module (MCM) GPU data sharing coalescing

来源：评论

学校读者我要写书评

暂无评论

2.5D MCM (multi-chip module) Technology Development for Advanced Package 73

2.5D MCM (Multi-chip Module) Technology Development for Adva...

引用

ieee 73rd Electronic Components and Technology conference (ECTC)

作者： Yip, Laurene Tsai, James Lin, Rosa Hsu, Ian MediaTek Inc San Jose CA 95134 USA MediaTek Inc Hsinchu Taiwan

ISBN: (纸本)9798350334982

2.5D silicon interposer packages have been widely adopted for high-end applications such as datacenter, networking, and artificial intelligence. To meet the increasing demand for higher performance and greater bandwidth, the die and package sizes have been increasing due to the need for higher levels of device integration. As the package size increases, chip-to-package interaction (CPI) will become more challenging to manage. The main challenges with large 2.5 devices are warpage, C4 bump integrity, underfill cracking, and mold compound delamination caused by interposer corner stress. In our study, package warpage and reliability of a chip-on-wafer-on-substrate (CoWoS) multi-chip module (MCM) package with two 1.5X reticle interposers and a package size of 85mmX85 mm were investigated. The coefficient of thermal expansion (CTE) mismatch between different package materials can cause warpage and induce mechanical stresses that can lead to bump cracks, underfill delamination/cracking, and other failures in the package. We will discuss package design methods to reduce interposer die stress to enhance package reliability. By using finite element stress analysis to optimize the device layout, C4 bump standoff height, and interposer structure, large size 2.5D MCM packages were developed and evaluated with reliability testing.

关键词： 2.5D multi-chip module interposer package warpage CoWoS reliability

来源：评论

学校读者我要写书评

暂无评论

A Simple and Non-Destructive Method to Measure Per-Terminal Baseplate Coupling of Power modules 38

A Simple and Non-Destructive Method to Measure Per-Terminal ...

引用

ieee Applied Power Electronics conference and Exposition (APEC)

作者： Deboi, Brian Curbow, Austin Lemmon, Andrew Wolfspeed Inc Power Modules Fayetteville NC 27703 USA Univ Alabama Elect & Comp Engn Tuscaloosa AL USA

ISBN: (纸本)9781665475396

The high edge rates of wide bandgap semiconductors can produce common-mode currents that flow through the baseplates of multi-chip power modules. These currents increase the electromagnetic signature of these devices and force designers to reduce edge rates or add additional filters in order to meet compliance standards. Parasitic baseplate capacitances that exist within power module packaging are known to be a primary path for the flow of these common-mode currents. Unfortunately, the measurement techniques currently available to characterize these capacitances are either challenging to perform or require the internal interconnects to be removed. This paper proposes a simple and non-destructive measurement technique to characterize the baseplate capacitances of multi-chip power modules on a per-terminal basis. The technique can be performed with an impedance analyzer and does not require any special fixturing or alterations to the module. The measurement technique is applied to three fully populated commercial module and is validated by comparisons to the standard destructive measurement technique.

关键词： wide bandgap electromagnetic interference measurement methods power module baseplate capacitance impedance analysis

来源：评论

学校读者我要写书评

暂无评论

Temperature-Aware Sizing of multi-chip module Accelerators for multi-DNN Workloads

Temperature-Aware Sizing of Multi-Chip Module Accelerators f...

引用

Design, Automation and Test in Europe conference and Exhibition (DATE)

作者： Shukla, Prachi Aguren, Derrick Burd, Tom Coskun, Ayse K. Kalamatianos, John Boston Univ Boston MA 02215 USA Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798350396249

This paper demonstrates the need for temperature awareness in sizing accelerators to target multi-DNN workloads. To that end, we build TESA, a TEmperature-aware methodology that Sizes and places Accelerators to balance both the cost and power of a multi-chip module (MCM), including DRAM power for multi-deep neural network workloads. TESA tunes the accelerator chiplet size and inter-chiplet spacing to generate a temperature-aware MCM layout, subject to user-defined latency, area, power, and thermal constraints. Using TESA for both 2D and 3D systolic array-based chiplets, we demonstrate up to 44% MCM cost savings and 63% DRAM power savings, respectively, over a temperature-unaware baseline at iso-frequency and iso-interposer area. We also demonstrate a need for TESA to obtain feasible MCM configurations for multi-DNN workloads such as augmented/virtual reality (AR/VR).

关键词： 3D stacking thermal awareness multi-DNN workloads systolic arrays multi-chip module

来源：评论

学校读者我要写书评

暂无评论

3-D Modeling and FEA for MCM by APDL

3-D Modeling and FEA for MCM by APDL

引用

ieee MTT-S International conference on Numerical Electromagnetic and multiphysics Modeling and Optimization (NEMO)

作者： Lin, Qian Zhao, Peng-Fei Wu, Hai-Feng Qinghai Minzu Univ Coll Phys & Elect Informat Engn Xining 810007 Peoples R China Chengdu Ganide Technol Chengdu 610073 Peoples R China

ISBN: (纸本)9798350347401

In order to accurately analyze interconnect reliability for a complex multi-chip module (MCM), a highly integrated RF MCM for TDD base stations which is consisted with two Si switch chips and two GaAs low noise amplifiers is taken as an example here. ANSYS Parametric Design Language (APDL) is used to achieve the automatic 3-D modeling, and the temperature reliability can be predicted by finite element analysis (FEA). This is the first time to conduct interconnect reliability analysis for a MCM chip. This can provide the basis and guidance for interconnect reliability analysis and design of MCM chip. Meanwhile, the 3-D modeling is high-efficient in modeling time and memory.

关键词： 3-D model APDL multi-chip multi-functional module (MCM) Finite element analysis (FEA)

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共54页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：