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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是91-100 订阅

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Analysis of multi chips Turn on Consistency in High Voltage and High Current IGBT module 2

Analysis of Multi Chips Turn on Consistency in High Voltage ...

引用

ieee 2nd International conference on Circuits and Systems (ICCS)

作者： Yao, Erxian Wang, Rui Liu, Xuguang Pan, Zhengwei Tong, Yan Nari Geiri Semicond Co Ltd Nanjing Peoples R China

ISBN: (纸本)9781728191225

In this paper, the influence of module internal structure, gap between and substrate, chip layout on multi chips turn on consistency are analyzed, taking the 3300V-1500A IGBT module as example. the copper foil area of the drive PCB should be expanded as much as possible, and the gate copper foil and the emitter copper foil should overlap as much as possible to offset the influence of the power side current change on the drive signal. On the chip layout, the difference between the gate path and the emitter path length should be minimized to improve the consistency of the driving signals of different chips. The gap between the drive PCB and the backing plate should be increased as much as possible to reduce the impact of the power side current change on the drive side.

关键词： switching consistency high power IGBT module parasitic parameters

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Experimental Validation of CT-Snubber for multichip SiC MOSFET Power module 63

Experimental Validation of CT-Snubber for Multichip SiC MOSF...

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63rd ieee International Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Fu, Bo Shahabi, Ali Freeborn, Todd J. Lemmon, Andrew N. Kisacikoglu, Mithat C. Univ Alabama Dept Elect & Comp Engn Tuscaloosa AL 35487 USA

ISBN: (纸本)9781728180588

Recently, a "CT-snubber" circuit was shown to enable high bandwidth current measurements and ringing suppression in silicon carbide MOSFETs multi-chip power modules. Preliminary designs increased damping but also increased the voltage overshoot during switching transients. In this work, the associations between CT-snubber impedance characteristics and dynamic performance (e.g. settling time and voltage overshoot) during double-pulse testing are explored using a simulation study. A fabricated CT-snubber prototype is then implemented and integrated into double-pulse testing of a silicon carbide multi-chip power module at a bus voltage of 1 kV and 400 A load, achieving damping ratios with up to 2:78x improvement over tests without the CT-snubber.

关键词： Double-Pulse Testing multi-chip SiC Power module Voltage Overshoot Settling Time Snubbing

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Approximate Pattern Matching for On-chip Interconnect Traffic Prediction 20

Approximate Pattern Matching for On-Chip Interconnect Traffi...

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ACM International conference on Parallel Architectures and Compilation Techniques (PACT)

作者： Adhinarayanan, Vignesh Feng, Wu-chun Virginia Tech Blacksburg VA 24061 USA

ISBN: (纸本)9781450380751

Emerging multi-chip module GPUs (MCM-GPUs) expend over 17% of the total power budget on chip interconnects and this fraction is expected to increase as chip size increases. Towards proactively managing the power consumption of these interconnects, we propose approximate pattern matching to predict future interconnect traffic from past observations. Compared to past prediction techniques such as Markov model (MM) and history table (HT), our proposed technique reduces average prediction error to 2.66% from 7.11% and 3.83% for MM and HT, respectively.

关键词： data movement phase prediction multi-chip module chiplet interconnects

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LAMBDA: An Open Framework for Deep Neural Network Accelerators Simulation

LAMBDA: An Open Framework for Deep Neural Network Accelerato...

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19th ieee International conference on Pervasive Computing and Communications (ieee PerCom)

作者： Russo, Enrico Palesi, Maurizio Monteleone, Salvatore Patti, Davide Ascia, Giuseppe Catania, Vincenzo Univ Catania Dept Elect Elect & Comp Engn DIEEI I-95125 Catania Italy Univ Enna Fac Engn & Architecture I-94100 Kore Enna Italy

ISBN: (纸本)9781665404242

Many tasks in the realm of recognition, mining, and synthesis are increasingly being implemented by using machine learning approaches. In particular, deep neural networks (DNNs) are currently able to solve a myriad of tasks with superhuman accuracy. The ever more increasing cost of communication as compared to computation is pushing toward the shifting of the intelligence as close as the edge of the network. However, the edge nodes often come in the form of resource-constrained devices that do not have the computational and memory capabilities required to perform DNN inferences. To solve this problem, the use of DNN accelerators embedded into a device makes it possible to run complex DNN inferences even on resource-constrained devices. A DNN accelerator exposes many configurable hardware settings that the designer has to properly set to select the optimal trade-off among different conflicting criteria, including performance, energy, and accuracy. This paper presents LAMBDA, a framework based on Timeloop/Accelergy infrastructure that allows exploring the design space of configurable DNN accelerators taking into account a variety of architectural and microarchitectural parameters. We describe the key components of LAMBDA focusing on the modeling of the communication and memory sub-system, which have the greatest impact on the energy and performance figures of a hardware accelerator.

关键词： Deep neural network domain-specific hardware accelerator multi-chip-module silicon interposer 2.5D stacking simulation

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Silicon Photonic 2.5D Integrated multi-chip module Receiver

Silicon Photonic 2.5D Integrated Multi-Chip Module Receiver

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conference on Lasers and Electro-Optics (CLEO)

作者： Abrams, Nathan C. Cheng, Qixiang Glick, Madeleine Jezzini, Moises Morrissey, Padraic O'Brien, Peter Bergman, Keren Columbia Univ Dept Elect Engn New York NY 10027 USA Tyndall Natl Inst Cork Ireland

We demonstrate the first 2.5D integrated, wavelength division multiplexing, silicon photonic receiver. The multi-chip module utilizes a silicon interposer to integrate the four-channel photonic cascaded microdisk rece... 详细信息

ISBN: (数字)9781943580767

ISBN: (纸本)9781943580767

关键词： Modulators Silicon Silicon photonics Tunable lasers Variable optical attenuators Wavelength division multiplexing

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multi-RF chip module Through FOWLP

Multi-RF Chip Module Through FOWLP

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Electronics Packaging Technology conference (EPTC)

作者： Serine Soh Siew Boon David Ho Soon Wee Chia Lai Yee Norhanani Jaafar Jacob Soh Hsiao Hsiang Yao Sharon Lim Pei Shan Xu Feng Ong Poh Kuan Chan Kien Teck Institute of Microelectronics (IME) Agency for Science Technology and Research (A*STAR) Singapore MEDs Technologies Pte Ltd

ISBN: (数字)9798331522001

ISBN: (纸本)9798331522018

This paper depicts the development of multiple Pseudomorphic high electron mobility transistor (pHEMT) semiconductors with AlGaAs/InGaAs/GaAs developed to realize high power and high-efficiency amplifiers for System-in-Package (SiP) modules. The developed Fan-out package measures 5.27mm X 7.15 mm X 0.15mm, based on the electrical simulation has anticipated gain of approximately 3-4dB, with power consumption < 1-1.5 W. The Re-distribution Layer (RDL) is introduced onto the Au pads at the frontside of the FOWLP to establish interconnections between the respective III-V chips, implementing Under Bump Metallization (UBM) and completes the package with solder bumps, for mounting onto the Printed Circuit Board (PCB). The package consists of four RF chips with dies of 50um and 100um die-thicknesses. On the back of the FOWLP, a copper ground plane is plated to build interconnections from the back of the embedded chips through the Though-Mold-Vias (TMVs) to the top of the package, that was introduced to aid heat dissipation when the SiP is turned on.

关键词： Radio frequency Semiconductor device measurement System-in-package Power measurement Power demand Printed circuits PHEMTs Integrated circuit interconnections Prototypes Transistors

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Challenges of large Fan out multi-chip module and fine Cu line space 70

Challenges of large Fan out multi-chip module and fine Cu li...

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70th ieee Electronic Components and Technology conference (ECTC)

作者： Huang, Yu Lung Chung, C. Key Lin, C. F. Lu, Guan Hua Tseng, Ching Hung Da Chang, Hong Hsu, Chih Hsun Xu, Bruce Siliconware Precis Ind Co Ltd Corp R&D Taichung Taiwan

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161808

The growth of artificial intelligence, internet of things and 5G technology demands for much higher data rate. Though Moore's law has come to end. But, the need of high functions devices are not stopping. Thus chiplet package is evolved. chiplet package basically contains of single chip module to connect multi-chips into one as to deliver high bandwidth transmission. The inputs/outputs counts are high and densely packed with large number of Cu line within confined package size. To fulfill these requirements, multiple chiplets packages have been designed. Fan-Out multi chip module (FOMCM) is one of chiplets that designed for lower cost and high data rate transmission package. In this study, we have developed a very large chiplet package using FOMCM technology. This package has the size of 77.5 * 77.5 mm2 and contained one chip module with 2 integrated dies. Each of the die size is 26 * 16 mm2. The 2 chips are attached on the three prefabricated redistribution layers (RDLs). In TV (Test Vehicle) sample, two TVs are tested as samples. The difference between these two TVs is only in the dimension design of Cu line in RDL. Firstly, in TV1, the size of Cu line is 2/2/2.3 (line space/width/thickness, mu m) in 2nd and 3rd layers of RDL. Then, in TV2, the size of Cu line is 1/1/2.5 in 2nd layer of RDL and 1/1/1 in 3rd layer of RDL. In results, firstly, in TV1, the maximum and the minimum of shifting values are 3.09 mu m and 1.86 mu m in chip module. Secondly, for TV1, the width of Cu line in RDL is from 1.71 mu m to 2.03 mu m in ISO (Isolation) zone of Cu line and is from 1.72 mu m to 2.06 mu m in dense zone of Cu line. For TV2, the width of Cu line in RDL is from 0.73 mu m to 1.02 mu m in ISO zone of Cu line and is from 0.72 mu m to 1.06 mu m in dense zone of Cu line. Thirdly, based on package level reliability, TV1 passes the tests of TCT B 1000 x, mu HAST 96 hr, and HTSL 1000 hr, while TV2 passes the tests of TCT B 1000 x, mu HAST 192 hr, and HTSL 1000 hr. Fourthly, for T

关键词： Fan-out multi-chip RDL Cu line Fine Cu line space Fine pitch Large PKG. FOMCM

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multi-Physical Simulations and Modelling of an Integrated GaN-on-Si module Concept for Millimetre-Wave Communications 70

Multi-Physical Simulations and Modelling of an Integrated Ga...

引用

70th ieee Electronic Components and Technology conference (ECTC)

作者： Rasilainen, Kimmo Buisman, Koen Andersson, Kristoffer Fager, Christian Chalmers Univ Technol Dept Microtechnol & Nanosci SE-41296 Gothenburg Sweden Ericsson AB SE-41756 Gothenburg Sweden

ISBN: (纸本)9781728161808

This paper presents a multi-physical system-level simulation workflow to characterise the performance of a heterogeneously integrated communications module for mm-wave applications. Basic principles behind modelling different parts and properties of the module are explained. The workflow combines the electromagnetic properties of a patch antenna array operating at 39 GHz with polynomial-based power amplifier (PA) models and thermal simulations of the structural heating. Effects of heating on the PA properties are also considered. The PA model is based on and compared with circuit simulations of a mm-wave transceiver chip, and the results are in good agreement. The proposed workflow can be used to describe and predict the performance of the module in different spatio-temporal use cases, and the approach also scales to larger arrays and more detailed simulation models.

关键词： Antenna array electrothermal model heterogeneous integration multi-physical workflow

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MONOLITHIC MEMS FILTER BANKS ON RFSOI FRONT-END module 33

MONOLITHIC MEMS FILTER BANKS ON RFSOI FRONT-END MODULE

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33rd ieee International conference on Micro Electro Mechanical Systems (MEMS)

作者： Campanella, Humberto Qian, You Romero, Christian O. Giner, Joan Kumar, Rakesh GLOBALFOUNDRIES Singapore Singapore Singapore Tyndall Natl Inst Cork Ireland

ISBN: (纸本)9781728135816

This work is the first demonstration of a monolithic multiband RF front-end module (RF-FEM), integrating MEMS Lamb-wave filters and switches on 200mm RF silicon-on-insulator (RFSOI) foundry technology. multiple MEMS filters with photolithography-defined frequencies coexist with RF components in the same wafer. This technology enables vertical integration of RF-FEM components for more compact System-on-chip (SoC) architectures. The resulting RF-FEMs will then integrate in the same process multi-frequency filter banks, low noise amplifiers (LNAs), and switches, with a footprint reduction up to 50% compared to system-in-package (SiP) modules. The SoC architecture also simplifies the design of interconnection lines and impedance matching networks.

关键词： MEMS filters RF front-end modules Lamb wave filters monolithic 3D integration 5G System-on-chip

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Personal Trusted Platform module for the multi-Core System of 5G Security and Privacy 13

Personal Trusted Platform Module for the Multi-Core System o...

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13th International ELEKTRO conference (ELEKTRO)

作者： Ruchkin, Vladimir Fulin, Vladimir Romanchuk, Vitaly Koryachko, Alexei Ruchkina, Ekaterina Ryazan State Univ Phys & Math Fac Ryazan Russia Ryazan State Radioengn Univ Cad Comp Facil Chair Ryazan Russia Ryazan State Radioengn Univ Hist Philosophy & Law Chair Ryazan Russia

ISBN: (纸本)9781728175423

The article is devoted to the choice of personal means of the 5G defense in dependence of hard- and software available to the user. The universal module MS 127.04 and its software compatible unit can be universally configured for use. An intelligent hardware and software platform is proposed for multi-core setting of policies for the automatic encryption of confidential data and selective blocking related to the implementation of computing security and confidentiality of data transfer, using such additional specially. A platform that resists the external influences is described. The platform is based on a universal module MS 127.05 (produced in Russia), that is a heterogeneous multiprocessor system on a chip), the system features 16 processor cores (NeuroMatrix Core 4) and five ARM Cortex-A5 units (ULSI 1879VM8Ya.

关键词： computer security confidentiality policy setting blocking application Virtualization Based Security Trusted Platform module Cyber-Physical Systems Internet of smart (mobile) CPSs Internet of Things 127.05 module NeuroMatrix Core 4 ARM Cortex-A5 ULSI 1879VM8Ya MPSoC

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