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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是121-130 订阅

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A 8-12GHz 4-Element SiGe BiCMOS multi-Function chip for Phased Array Systems 4

A 8-12GHz 4-Element SiGe BiCMOS Multi-Function Chip for Phas...

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4th International conference on Integrated Circuits and Microsystems (ICICM)

作者： Zhang Hao Wan Chuanchuan Nanjing Res Inst Elect Technol Nanjing Peoples R China

ISBN: (纸本)9781728151328

This paper presents a 4-element X-band multi-function chip(MFC) based on SiGe technology, which includes RF switches, low noise amplifier, power amplifier driver, attenuator, phase shifter, Power divider and digital beam forming. The traditional MFC is realized by GaAs process, which has the disadvantages of high cost and low integration. This design is based on SiGe process, which greatly reduces the cost of the chip and improves the integration. A series of techniques, such as on-chip temperature compensation, phase compensation and amplifier parallel peaking, arc adopted to achieve better temperature characteristics, smaller attenuation additional phase shift and broadband characteristics. The test results show that the MFC works at 8-12GHz, RMS phase error is less than 3.5 degrees, attenuation additional phase shift is less than 3degrees, the RX gain and TX gain is 10dB and 3dB, respectively. The gain variation is less than 0.019dB/oC. The size of the chip contains pad is about 6mm*9mm.

关键词： multi-function chip phase shifter attenuator BiCMOS phased array T/R module

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multi-chip module Based GaAs MMICs Packaging for L-Band High Gain Application

Multi-chip Module Based GaAs MMICs Packaging for L-Band High...

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ieee MTT-S International Microwave and RF conference (IMARC)

作者： Gugulothu, Ravi Bhalke, Sangam, V Naik, Anant A. Lalkishore, K. Dasari, Ramakrishna Gallium Arsenide Enabling Technol Ctr Dept ATQC Hyderabad Telangana India Osmania Univ Univ Coll Engn Autonomous Dept Elect & Commun Engn Hyderabad Telangana India

ISBN: (纸本)9781728140407

this paper details a multi-chip module (MCM) suitable for GaAs monolithic microwave integrated circuit common control high gain block MCM package design, 3D EM simulation of the package, package fabrication and end module level execution, which includes assembly and testing under various environmental test conditions as per the space standards. This MCM package designed using three internally separated cavities for individual cavity isolation, 4-RF Ports, 10mil thin film microstrip line and optimized wire bonding interconnects, and the same package is EM simulated using a CST microwave studio. This package modelled and fabricated using kovar material. This MCM package proposed to house a chain of four amplifiers with a common gain of 69dB, 2 SPDT switches with insertion loss of 3.6dB, a digital attenuator with initial attenuation of 2.5dB with TTL driver and 2 thermopads of 3dB individual attenuation. This package resonating frequency is 7.484GHz. The packaged MCM measurements are carried out over a frequency of 1.1GHz-1.4GHz and resulted with S-21 of 60dB, S11&S-22 of better than 15dB and P-1dB out of 15dBm.

关键词： Amplifiers SPDT DA TTL driver Ceramics GaAs MMIC Package multichip module

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System Co-Design of a High Current (40A) Synchronous Step-Down Converter in an Innovative multi-chip module (MCM) LQFN-type Packaging Technology 69

System Co-Design of a High Current (40A) Synchronous Step-Do...

引用

69th ieee Electronic Components and Technology conference (ECTC)

作者： Harrison, Todd Chen, Jie Murugan, Rajen Texas Instruments Inc Cary NC USA Texas Instruments Inc Dallas TX 75243 USA

ISBN: (纸本)9781728114989

The drive for multi-chip module (MCM) packaging technology essentially stems from the ever-increasing demand for miniaturization of power electronics. While promising, MCM packaging technologies present considerable design challenges (viz. electrical, thermal, reliability and manufacturing/assembly) if system co-design techniques are not adopted early in the design process. In this paper we present the electrical system co-design and measurement validation results of a high-efficiency, single channel, integrated FET, synchronous buck converter packaged in a 40-pin 7.00mm x 5.00mm MCM-in-LQFN-type innovative package. Due to the complex 3D level of integration of the monolithic control, drive circuitry, and the two discrete N-channel NexFET (TM) power MOSFETs, electromagnetic interactions, between die, package, and PCB, are exacerbated with potential impact to system-level performance. We detail here how optimization of the system, was achieved through a coupled circuit-to-electromagnetic co-design modeling and simulation methodology. Laboratory measurements on an integrated high current (40A) synchronous step-down converter are presented that validate the integrity of the co-design modeling and simulation methodology.

关键词： Integrated circuit modeling Analytical models MOSFET Switches Inductance

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Reconfigurable module of multi-mode AES Cryptographic Algorithms for AP SoCs 5

Reconfigurable Module of Multi-mode AES Cryptographic Algori...

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ieee Nordic Circuits and Systems conference (NORCAS) NORchip / International Symposium of System-on-chip (SoC)

作者： Silitonga, Arthur Jiang, Zhou Khan, Nadir Becker, Juergen Karlsruhe Inst Technol Inst Informat Proc Technol ITIV Karlsruhe Germany Datang Mobile Commun Equipment Co Ltd Shanghai Peoples R China FZI Res Ctr Informat Technol Karlsruhe Germany

ISBN: (纸本)9781728127699

In the implementation of the Advanced Encryption Standard (AES), as one instance of symmetrically cryptographic (crypto) algorithms, there are existing various block cipher modes used to offer higher confidentiality compared to the Electronic Codebook (ECB). In this article, we implement the AES with three different key lengths and different block cipher modes using High-Level Synthesis (HLS). The modes are Cipher Block Chaining (CBC), Cipher Feedback Mode (CFB), Output Feedback Mode (OFB), Counter (CTR), and Ciphertext Stealing (XTS) as extensions of the Electronic Codebook (ECB). All Programmable System-on-chip (AP SoC) consisting of a hard multi-core processor and an FPGA is the target platform, and we leverage the capabilities of static and dynamic partial reconfigurations of FPGA. It is shown that the combination of a pipeline, array partitioning, and unrolled loop can lead to an increase in the data rate up to seven times. The approach comes at a trade-off of increased resource demand, which we carefully balance to achieve optimal results. Based on further evaluation, there are significant differences in throughput of the optimized CTR implementation between static and partial reconfigurations, and between the usage of Processor Configuration Access Port (PCAP) and Internal Configuration Access Port (ICAP). In the realization, the bare-metal and Linux-based Operating System implementations show a possible occurrence to implement partial reconfiguration of multi-mode AES crypto algorithms in different configurations of AP SoCs during run-time.

关键词： FPGA Advanced Encryption Standard (AES) All-Programmable System-on-chip (AP SoC) High-Level Synthesis (HLS) Dynamic Partial Reconfiguration (DPR)

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TeraPHY: A High-density Electronic-Photonic chiplet for Optical I/O from a multi-chip module

TeraPHY: A High-density Electronic-Photonic Chiplet for Opti...

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Optical Fiber Communications conference and Exhibition (OFC)

作者： Meade, Roy Ardalan, Shahab Davenport, Michael Fini, John Sun, Chen Wade, Mark Wright-Gladstein, Alexandra Zhang, Chong Ayar Labs Inc 6460 Hollis StSte A Emeryville CA 94608 USA

In this work, we provide an overview of System-in-Package (SiP) integration of an electronic-photonic chiplet fabricated in a commercial CMOS foundry. Assembly considerations, including co-packaging in a standard mult... 详细信息

ISBN: (纸本)9781943580538

关键词： Optical fibers Optical fiber communication Optical device fabrication Electronic packaging thermal management Optical fiber devices Bandwidth

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Thermal chips Layout Method in MCM Based on an Improved Particle Swarm Algorithm 31

Thermal Chips Layout Method in MCM Based on an Improved Part...

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31st Chinese Control And Decision conference (CCDC)

作者： Ning, Ye Jie, Yang Ye, Tao Northeastern Univ Sch Informat Sci & Engn Shenyang 110819 Peoples R China

ISBN: (纸本)9781728101057

The emergence of multichip module(MCM) means that the development of component technology is greatly improved in number, speed and performance. Research on thermal layout optimization methods for MCM can promote its reliability, this paper established a numerical relationship model between junction temperature and coordinates of each chip. and uses ANSYS to simulate and analyze the temperature profile of the optimization results. This paper compares several typical optimization schemes based on (W) and presents the improved particle swarm algorithm. Experimental results show that improved particle swarm algorithm can improve inertia weight and maximum speed effectively, and also can achieve lower chip junction temperature in chip layout.

关键词： multi-chip module(MCM) Particle Swarm Optimization Algorithm Thermal Layout Optimization Inertia Weight

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Process Induced Wafer Warpage Optimizationfor multi-chip Integrationon Wafer Level Molded Wafer 69

Process Induced Wafer Warpage Optimizationfor Multi-chip Int...

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69th ieee Electronic Components and Technology conference (ECTC)

作者： Huang, Chen-Yu Ng, Daniel Lee, Hung-Ho Lin, Vito Lin, Chang-Fu Chung, C. Key Siliconware Precis Ind Co Ltd Corp R&D Taichung 4288 Taiwan

ISBN: (纸本)9781728114989

In this paper, the demonstration of test vehicle by two kinds of process flows noted as "C4-first" and "C4 last", which integrate chips on mold-based, Cu via wafer with glass carriers, are presented. Their warpage behavior during wafer-form integration will be experimentally and numerically evaluated, and also compared with wafer warpages of 2.5D assembly which applied Si interposer with TSV (through Si via). The C4-first flow is to attaching chips on wafers where the C4 bumps have been completed between mold layer and glass carrier. This flow is similar to 2.5D manufacturing process that the Si interposer was temporarily bonded on a carrier which can suppress the interposer warpage variation during reflow process. The temporary glue is required to protect the C4 bumps during chip on wafer procedures. In regarding to the cycle time and cost, the flow to complete C4 after chips attaching will be further studied. The processed induced u-bump (micro-bump) and u-pad (micro-pad) shift post jointing are observed to be larger than that in 2.5D flow. In the manufacturing process of molded wafer, the high CTE glass carriers are used to reduce CTE mismatch between molding compound and carrier. The significant wafer warpage changing from concave to convex shape was observed after chips attaching on the wafer. And the warpage will be further increased after underfilling and molding processes. To well predict and address the warpage trend, the finite element analyses are carried out to understand the process-induced warpage behaviors, and thus to select better material and process parameter. The key parameters affecting wafer warpages like material properties of molding compound, glass carrier and top-mold thickness are determined by finite element simulation. In light of the handing procedure of wafer form assembling equipment, the preferred wafer warpage shape is determined by experimental results. Finally, the test vehicle have been assembled with substrate as well. The chip

关键词： C4 first C4 last chip module interposer

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multi-Physical Simulations and Modelling of an Integrated GaN-on-Si module Concept for Millimetre-Wave Communications

Multi-Physical Simulations and Modelling of an Integrated Ga...

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Electronic Components and Technology conference (ECTC)

作者： Kimmo Rasilainen Koen Buisman Kristoffer Andersson Christian Fager Department of Microtechnology and Nanoscience Chalmers University of Technology Gothenburg Sweden Ericsson AB Gothenburg Sweden

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

This paper presents a multi-physical system-level simulation workflow to characterise the performance of a heterogeneously integrated communications module for mm-wave applications. Basic principles behind modelling different parts and properties of the module are explained. The workflow combines the electromagnetic properties of a patch antenna array operating at 39 GHz with polynomial-based power amplifier (PA) models and thermal simulations of the structural heating. Effects of heating on the PA properties are also considered. The PA model is based on and compared with circuit simulations of a mm-wave transceiver chip, and the results are in good agreement. The proposed workflow can be used to describe and predict the performance of the module in different spatio-temporal use cases, and the approach also scales to larger arrays and more detailed simulation models.

关键词： Integrated circuit modeling Antenna arrays Data models Thermal conductivity Solid modeling Thermal analysis Biological system modeling

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Bi-Transfer: A Data Packet Allocation module with Chaining Transmission Mode 5

Bi-Transfer: A Data Packet Allocation Module with Chaining T...

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5th ieee International conference on Computer and Communications, ICCC 2019

作者： Li, Zerun Yang, Sen Wang, Yu Chen, Lirui Guo, Yang Xing, Zuocheng College of Computer NUDT Changsha China

ISBN: (纸本)9781728147437

With the increasing performance requirements of network data interaction on chip, the traditional Direct Memory Access (DMA) often performs with low efficiency of multi-module collaboration due to the competition of bus control, thereby reducing the throughput rate of the bus. Aiming at the working characteristics of inter-core communication and data interaction between multiple modules, this paper designs a packet transmission module Bi-Transfer that supports bidirectional data flow between multiple modules It also realizes chaining transmission of input and output data in parallel with various configuration modes and flexible data scheduling modes. This module can complete the functions of data movement, inter-core communication, task management, etc., and use descriptors to link load data packets to uniformly conFigure the data interaction mode of the on-chip network. In the experimental stage, function planning and code design are carried out first, then the timing simulation and data recording are described. Finally, the performance characteristics of this new data interaction module are discussed. According to statistical observations, increasing the number of channels in the design module can significantly increase the bandwidth of the bus. Under the given clock frequency, bus width and data transmission requirements, the bus operating bandwidth in the four-channel working mode can reach up to 4690 MB/s at most, which is nearly 400 MB/s beyond the ordinary DMA bus bandwidth. In the case of fewer channels, this module can fulfill the data scheduling requirements of most applications and provide the data moving function of ordinary DMA. © 2019 ieee.

关键词： Buses

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Research On FOPLP Package of multi-chip Power module

Research On FOPLP Package of multi-chip Power Module

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Electronics System-Integration Technology conference, ESTC

作者： Jing Jiang Jia ren Huo Guan qiang Song Huaiyu Ye De Bo Liu Guoqi Zhang Jun Tao Jun Wang ACADEMY for ENGINEERING&TECHNOLOGY FUDAN UNIVERSITY Shanghai China Product Research and Development Wuxi Sky Chip Interconnection Technology CO. LTD shenzhen China Shenzhen Institute Of Wide-Bandgap Semiconductors Engineering Research Center of Integrated Circuits for Next-Generation Communications Ministry of Education Southern University of Science and Technology Shenzhen China Wuxi Sky Chip Interconnection Technology CO. LTD Wuxi China Shenzhen Institute Of Wide-Bandgap Semiconductors Electronic Components Technology and Materials Delft University of Technology Delft The Netherlands

ISBN: (数字)9781728162935

ISBN: (纸本)9781728162942

Power devices are developing for the small volume, high performance and modularization. With more and more application scenarios of Brushless Direct Current Motor (BLDC), MOSFET multi-chip module (MCM) is popular with people. However, the conventional wire Bonding and Copper clip welding technology struggles to meet the requirements for the excessive heat accumulation and complex logic problems in MCM. While the above problems can be well solved by using the new Fan out panel level packing(FOPLP) technology for QFN packaging of multi-chip. The traditional welding technology is used at the bottom of the chip, and the copper porous link is used at the top of the chip with low parasitic capacitance, inductance and low R dson in electrical performance. In respect to thermal management, the θ JC on the top of the chip can be reduced, which has the effect of double-sided heat dissipation. Top Layer interconnection technology is adopted in the packaging scheme, which can have complex circuit *** paper mainly describes the technical implementation of this packaging technology, adopting the finite element software to establish a three-dimensional model of a new type of FOPLP and wire welding packaging for MCM. The thermal resistance of different packaging schemes is calculated to confirm the advantages and disadvantages of different schemes by the way of thermal simulation, the internal temperature distribution of different packaging structures and the main influencing factors of the thermal resistance of packaging compared.

关键词： Heating systems Resistance Packaging Wires Thermal resistance Resistance heating Copper

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