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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

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Novel 3.3kV Si-SiC Hybrid Power module 19

Novel 3.3kV Si-SiC Hybrid Power Module

引用

19th International conference on Electronic Packaging Technology (ICEPT)

作者： Li, Daohui Qi, Fang Li, Xiang Packwood, Matthew Luo, Haihui Liu, Guoyou Wang, Yangang Dai, Xiaoping Dynex Semicond Ltd Power Semicond R&D Ctr Lincoln LN6 3LF England CRRC Time Elect Co Ltd State Key Lab Adv Power Semicond Devices Zhuzhou 412000 Peoples R China

ISBN: (纸本)9781538663868

In this paper, one type of novel standardized 140mmx100mm footprint 3.3 kV Si-SiC hybrid power module has been designed and investigated. The power module is characterized by packaging of silicon based insulated-gate bipolar transistors (IGBTs) and silicon carbide (SiC) based Schottky barrier diodes (SBDs). To reduce the thermal coupling and enhance the reliability, each IGBT chip is anti-paralleled with two SBDs. Due to the adoption of new packaging structure, the multi-physics study is conducted for reliability-related analysis and optimization. We present the details about electromagnetic (EM) simulation and thermal network extraction at the design stage together with power module characteristics.

关键词： IGBT thermal network electro-thermal

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Development of high performance synchronous rectifier module by multi-chip Cu sintering technology (IMPACT 2018) 13

Development of high performance synchronous rectifier module...

引用

13th International Microsystems, Packaging, Assembly and Circuits Technology conference (IMPACT)

作者： Chang, J. Y. Fun, S. Y. Cheng, K. H. Cheng, H. W. Lin, H. H. Han, W. K. Hsu, S. F. Tseng, C. M. Chang, T. C. Anai, K. Yamauchi, S. Jo, J. L. Sakaue, T. Ind Technol Res Inst Intelligent Power Module & Syst Dept Elect & Optoelect Syst Res Labs 195 Sect 4Chung Hsing Rd Hsinchu 31040 Taiwan Mitsui Min & Smelting Co Ltd Engn Mat Sect R&D Ctr 1333-2 Haraichi Ageo Saitama Japan

ISBN: (纸本)9781538656150

In Recent year, the traditional Si and wide band-gap power semiconductor devices, particularly Si MOSFET, Si IGBT, SiC MOSFET and GaN E-HEMT have gained considerable attention in several industrial applications such as the hybrid electric vehicle, the internet data center and aero-space applications. Attachment of power semiconductor devices to an insulated metal carrier substrate is essential for providing electrical and structural connections as well as a heat dissipation path. The die attach materials play a vital role in ensuring the system performance and reliability. In this study, the key technologies including multi-chip Cu paste sintering and panel level packaging have been developed. With an optimized process condition, a voidless die attaching joint was gained, and the die shear strength was as high as 70 MPa as sintering. Furthermore, the reduction of thermal resistance was measured by using Cu sintering, and the electrical performance of the newly developed Synchronous Rectifier was fully reported in this study.

关键词： Substrates Rectifiers MOSFET Ceramics Silicon Thermal resistance Thermal conductivity

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Near-and far-field shielding effectiveness analysis of magnetic materials and their effect on wireless power charger 60

Near-and far-field shielding effectiveness analysis of magne...

引用

60th ieee International Symposium on Electromagnetic Compatibility and 9th ieee Asia-Pacific Symposium on Electromagnetic Compatibility, EMC/APEMC 2018

作者： Lin, Han-Nien Wu, Cheng-Hau Huang, Jen-Fu Tseng, Wei-Ding Lin, Jeffrey Yen-Ting Lin, Min-Shang Department of Communications Engineering Feng Chia University Taichung City40724 Taiwan Department of Electrical Engineering National Kaohsiung University Taiwan Bureau of Standards Metrology and Inspection MOEA Taiwan

ISBN: (纸本)9781509059973

As the multi-radio high-performance mobile devices and ever increasing functional smart-phones converge to a RF coexisting and high-speed digital platforms, the issue involving with electromagnetic compatibility (EMC) or radio frequency interference (RFI) is getting more design challenging for the system integration of mobile platforms. To prevent RFI noise degrading the RF front-end sensitivity and communications performance, electromagnetic shielding material is usually implemented on EMI noisy chips or modules. For the analysis of near-and far-field effective shielding, we utilize the far-field method of AST M D4935 and near-field testing method IEC 61967-6 originally developed for chip level EMI measurement in this study. Since wireless charging provides a number of efficiency, convenience, cost and safety advantages over the traditional charging cable for smartphones and hand-held industrial devices recently, we will also investigate the effect of magnetic material used in wireless charging coil module for further optimum applications. © 2018 ieee.

关键词： Electromagnetic compatibility

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Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Packaging Technology for multi-chip and 3D System Integration

Embedded Silicon Fan-Out (eSiFO): A Promising Wafer Level Pa...

引用

ieee Electronic Components and Technology conference

作者： Shuying Ma Jiao Wang Fengxia Zhen Zhiyi Xiao Teng Wang Daquan Yu Huantian Technology (Kunshan) Electronics Co. Ltd. Kunshan Jiangsu China Huantian Technol. (Kunshan) Electron. Co. Ltd. Kunshan China

The demand for miniaturized package size, higher performance and integration density, lower power consumption, and lower manufacturing cost drives the development of various new packaging technologies, such as WLP, 2.5D interposer, 3D WLCSP etc. Recently, Fan-Out Wafer Level Package (FOWLP) has aroused more and more interest since it emerged as a successful technology in providing the solution to meet advanced system packaging and integration requirements. FOWLP has also become a key-enabling technology for multi-chip and 3D system integration. Embedded silicon fan-out (eSiFO?) technology developed by Huatian group was a low cost FOWLP technology, which eliminates molding, temporary bonding and de-bonding in the process flow. The eSiFO? technology for single chip with a high yield of 99.5% was reported. In this paper, the development of eSiFO? technology for multi-chip and 3D system integration was reported. One package in the size of 5.2×4.0 mm~2 and containing 5 chips has been successfully produced. Small warpage of ~lmm for eSiFO? 300mm wafer was achieved even with 2 layer thick RDLs. Another 3D-Integration package based on the eSiFO? technology has also been successfully demonstrated, where two dies were stacked on the top of the eSiFO? wafer by die placement and mass reflow processes. For the 3D eSiFO? SiP package, the size and thickness was 4.1×4.1mm, and 0.375 mm respectively. One RDL was formed on both front and backside of the eSiFO?. The interconnection between the embedded chip and the stacked chips was made through micro bumps and through-silicon vias (TSVs) located in the fan-out area of the carrier wafer. The manufactured packages have shown good electrical yield and passed standard reliability tests.

关键词： Fan-out eSiFO 3D integration multi-chip module

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A versatile electrode sorting module for MEAs: implementation in a FPGA-based real-time system

A versatile electrode sorting module for MEAs: implementatio...

引用

ieee Biomedical Circuits and Systems conference (BioCAS)

作者： Pirog, Antoine Bornat, Yannick Renaud, Sylvie Perrier, Romain Jaffredo, Manon Raoux, Matthieu Lang, Jochen Univ Bordeaux IMS Bordeaux INP CNRS UMR 5218 F-33400 Bordeaux France Univ Bordeaux CNRS UMR 5248 CBMN F-33600 Pessac France

ISBN: (纸本)9781509058037

Extracellular recordings of biological signals using multi-Electrode Arrays (MEAs) generate large quantities of multichannel data which are not all relevant. Indeed, cultured cells might not cover all electrodes or achieve sufficient electrical contact. In both bench experiments and implant-oriented devices, it is necessary to identify such defects and exclude corresponding electrodes from the processing pool. In the context of a real-time, FPGA-based multichannel signal processing system, this paper presents a versatile electrode sorting module. It uses low-complexity, user-configurable algorithms and supports synchronization, frequency, and amplitude criteria, as well as definable inclusion/exclusion rules. This module relieves the experimenter from constantly monitoring unusual behavior and promotes automatization. The module's efficacy was demonstrated during in vitro experiments on noise-prone pancreatic islets.

关键词： FPGA multi-Electrode Array electrode sorting biosignals real-time pancreatic islets

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Realization of Baseband Signal Processing for Beidou/GPS multi-Mode Receiver by FPGA 9

Realization of Baseband Signal Processing for Beidou/GPS Mul...

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2017 9th ieee International conference on Communication Software and Networks (ICCSN 2017)

作者： Yongxi Zeng Yanzhong Yu Lijian Liu College of Physics and Information Engineering Key Laboratory of Information Functional Material for Fujian Higher Education Quanzhou Normal University

ISBN: (纸本)9781509038237;9781509038220

Beidou and GPS are an important part of the GNSS(Global Navigation Satellite System). Beidou is a global satellite navigation system that is independent development and operation in China. GPS is the most mature development system in the world currently. The research on the Beidou/GPS multi-mode receiver has an important practical significance at present. Compared with hardware receiver, software receiver realizes the performance of the receiver by software, and is suitable for developing new algorithms. Therefore it has advantages of flexibility, convenience, and low costs. A method to realize the baseband signal processing of the Beidou/GPS multi-mode receiver is introduced in this paper by using the chip EP2 S90 F1020 I4, which is Stratix II series of Altera's FPGA. Using Verilog HDL to design the baseband processing module of Beidou/GPS, including the fast acquisition module and tracking channel processing module, and the tracking channel processing module includes the carrier/code NCO generation module, the complex phase rotation DDC(Digital Down Converter) module, the Beidou/GPS pseudo-random code generator, code correlator module and frame synchronization module, etc. Test results show that the baseband signal processing module based on FPGA with the DSP calculation module can achieve the normal PVT calculation.

关键词： Beidou GPS FPGA Verilog PVT

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Compact Electro-Thermal Modeling of a SiC MOSFET Power module under Short-Circuit Conditions 43

Compact Electro-Thermal Modeling of a SiC MOSFET Power Modul...

引用

43rd Annual conference of the ieee-Industrial-Electronics-Society (IECON)

作者： Ceccarelli, Lorenzo Reigosa, Paula Diaz Bahman, Amir Sajjad Iannuzzo, Francesco Blaabjerg, Frede Aalborg Univ Ctr Reliable Power Elect Dept Energy Technol Pontoppidanstr 101 DK-9220 Aalborg Denmark

ISBN: (纸本)9781538611272

A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules.

关键词： silicon carbide power MOSFET modeling short-circuit

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Warpage Tuning Study for multi-chip Last Fan Out Wafer Level Package 67

Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level...

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ieee 67th Electronic Components and Technology conference (ECTC)

作者： Li, Hung-Yuan Chen, Allen Peng, Sam Pan, George Chen, Stephen Siliconware Precis Ind Co Ltd 19 Keya Rd Taichung Taiwan

ISBN: (纸本)9781509063154

In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability;besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young's modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm(2) with 8x9 and 4x9 mm(2) multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm;for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uHAST 96 hrs, and drop test by board level reliability.

关键词： FOWLP multi-chips module Carrier Fine Pitch RDL Warpage Molding Compound Ball on Trace

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Design of precision timing circuit for X-ray speed measuring instrument 13

Design of precision timing circuit for X-ray speed measuring...

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2017 13th ieee International conference on Electronic Measurement & Instruments (ICEMI)

作者： Yang Bo School of Electronic & Information Engineering Foshan University

ISBN: (纸本)9781509050369;9781509050352

According to the X-ray velocity measurement instrument based on the zone-block device, it has the characteristics of short timing and high measure *** the fully synchronous(ie, multi-cycle synchronous) technology by single chip microcomputer overcomes the quantization error, and produce a standard time interval to the measured time interval is modified, greatly reducing the system error. The single chip microcomputer as slave computer for timing data acquisition, through the wireless data transmission module real-time transmission to the host computer processing data, realize the multi-channel time interval measurement. The experimental results show that the timing circuit has strong anti-interference ability and good linearity, which can be widely used for timing measurement system of different time synchronization system.

关键词： time interval zone-block device single chip microcomputer X-ray

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Design and Implementation of a Dual-band RF SiP module based on Package-on-Package Technology 10

Design and Implementation of a Dual-band RF SiP Module based...

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International conference on Microwave and Millimeter Wave Technology (ICMMT)

作者： Liu, Jianfeng Wang, Bo Zhou, Yang Chen, Lijie Duan, Zongming Ma, Qiang 38th Res Inst China Elect Technol Grp Corp Dept Microsyst 199 Xiangzhang Rd Hefei 230088 Peoples R China

ISBN: (纸本)9781538624166

This paper presents design and implementation of a dual-band RF system-in-package (SiP) module for radar application. Four channel RF transceivers, each of which consists of dual-band RF front-end, ADC and DAC, are integrated in this SiP module. S and P band RF front-end of the transceiver employ common Intermediate Frequency (IF) window to share digitization circuits efficiently. To achieve more miniaturized package level of SiP, Package-on-Package technology is adopted and realized by stacking two multi-layer organic substrates vertically, which interconnected by Through Mold Via (TMV) and BGA. Dual-band RF front-end is mounted on the top RO4350B substrate, and four-channel ADC and DAC are molding on the bottom BT substrate. With the integration of 50 chips and 251 passive components, this SiP module retains small form factor and measures 3.8x4x0.4 cm(3). The simulation results show that the insertion loss of RF transmission paths are better than 0.4 dB with 60 dB channel isolation, the crosstalk between analog and digital paths is less than -60 dB, and each chip junction temperature is below 100 degrees C in the condition of full load. The above evaluation indicates that the proposed RF SiP module can achieve the optimization of electrical performance, reliability and miniaturization simultaneously.

关键词： Radio frequency Substrates Dual band Propagation losses Transceivers Insertion loss Reliability

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