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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是11-20 订阅

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High Power, Harmonics Suppressed multi-Die Single chip Front-End module for X-Band Radar Application

High Power, Harmonics Suppressed Multi-Die Single Chip Front...

引用

2024 Asia-Pacific Microwave conference

作者： Tan Do Viet-Hung Nguyen Huong Ngo Pham, Binh L. Viettel Grp Viettel Semicond Technol Div Hanoi Vietnam

ISBN: (纸本)9798350363555;9798350363548

This paper presents a high power X-Band multidie, single-chip front-end module (FEM) for active electronically scanned array antenna (AESA) radar applications. The chip is designed using 0.15um GaAs and 0.25um GaN technology and packaged in 7mm x 5mm over-molded QFN. This very compact chip can deliver more than 10W pulsed power with 22dB large signal gain from 8GHz to 11GHz. In this frequency range, it can suppress second and third harmonics for more than 40dBc. When operating in receive mode, it offers 2.4dB Noise Figure and 27dB small signal gain over the same frequency range.

关键词： Front-end module AESA radar high power amplifier harmonics suppression GaN technology

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Embedded mm-Wave chiplet Based module using Fused-Silica Stitch-chip Technology: RF Characterization and Thermal Evaluation 73

Embedded mm-Wave Chiplet Based Module using Fused-Silica Sti...

引用

ieee 73rd Electronic Components and Technology conference (ECTC)

作者： Zheng, Ting Manley, Madison Bakir, Muhannad Georgia Inst Technol Sch Elect Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9798350334982

A fused-silica stitch-chip technology for an embedded low noise amplifier (LNA) module is demonstrated for the first time. In this article, the package substrate and assembly are reported and RF/mm-wave characterization of the LNA module is performed. A <2.5 dB package loss is measured within the LNA bandwidth (24-40 GHz), translating to a <1.4 dB package interconnect loss. In addition, thermal simulations are implemented for the LNA module to investigate the thermal impact of critical package components when a high power-density chiplet is packaged. The stitch-chip technology features broadband low-loss interconnects and enables the scalability of chiplet-based integration;this represents a promising solution for future mm-wave multi-chiplet based modules.

关键词： Millimeter wave interconnects RF packaging transmission lines

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A multi-terminal Silicon Carbide Power module with Low Parasitic Inductance 10

A Multi-terminal Silicon Carbide Power Module with Low Paras...

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10th ieee International Power Electronics and Motion Control conference, IPEMC 2024 ECCE Asia

作者： Jia, Daoyong Jiang, Xi Wang, Ying Ma, Nianlong Ouyang, Renze Yuan, Song Gong, Xiaowu Xidian University The Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Materials and Devices School of Microelectronics Xi'an710071 China Xidian University Guangzhou Institute of Technology Guangzhou510555 China Shenzhen Smartchip Microelectronics Technology Company Ltd. Shenzhen518000 China

ISBN: (纸本)9798350351330

Parasitic inductance reduction in the SiC power module is a crucial aspect in power module design, which can help to decrease energy losses and improve the module's efficiency. This paper proposes an innovative layout for 1200V SiC MOSFET half-bridge power module to lower the parasitic inductance within the power loop and the thermal resistance. Through an extensive evaluation of how upper and lower bridge chip distances affect parasitic inductance and thermal resistance, an optimal chip spacing is selected. Following double pulse experimental test, the fabricated module is benchmarked against a same current rating commercial 1200V SiC MOSFET half-bridge module, exhibits superior switching performance. © 2024 ieee.

关键词： Silicon carbide

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Development of Pressure Contact Technology for multi-chip SiC modules with Low Parasitics 39

Development of Pressure Contact Technology for Multi-chip Si...

引用

Applied Power Electronics conference and Exposition (APEC)

作者： Wang, Lei Wang, Wenbo Rietveld, Gert Hueting, Raymond J. E. Yongjiang Lab Ningbo Peoples R China Univ Twente Enschede Netherlands VSL Enschede Netherlands

ISBN: (纸本)9798350316643

Conventional packaging limits the full exploitation of the high-frequency and high-power density capabilities of silicon-carbide (SiC) metal-semiconductor-oxide field-effect transistors. This work reports a pressure contact packaging technology on SiC modules to replace weak bonding elements and to achieve double-sided cooling. Three viable module layouts for a half bridge with multiple parallel chips are proposed, focusing on maximum power density and functional performance. A novel spring connector is designed to accommodate the small pad size and achieve pressure contacts on the chips. The path for the gate loop and power loop are optimized to ensure a balanced current distribution. The parasitic inductance of the experimental prototype with bus bars is only 4.76 nH, facilitating a high switching speed. The feasibility of the proposed packaging approach is confirmed by both extensive simulations and experiments.

关键词： pressure contact packaging silicon carbide power module stray inductance current balance

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Paralleled multi-chip Current Sensing PCB Coils for SiC Power module 10

Paralleled Multi-Chip Current Sensing PCB Coils for SiC Powe...

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10th ieee International Power Electronics and Motion Control conference, IPEMC 2024 ECCE Asia

作者： Qu, Zelong Sun, Peng Qiao, Jianshen Cai, Yumeng Zhang, Haoran Zhao, Zhibin Xin, Zhen North China Electric Power University State Key Laboratory of Alternate Electrical Power System with Renewable Energy Sources China Hebei University of Technology State Key Laboratory of Reliability and Intelligence of Electrical Equipment China

ISBN: (纸本)9798350351330

Within silicon carbide (SiC) power modules, the chip current is crucial for chip-level electro-thermal status monitoring, active current balancing, and other applications. Due to reasons such as magnetic saturation, non-linearity, and poor anti-interference capabilities, traditional current sensing methods cannot be integrated into SiC power modules. This paper proposed a new integrated PCB structure for SiC power module, playing the role of both low-inductance electrical connection and chip current sensor. The integrated PCB can be connected to the chips through bonding wires. And it possesses high bandwidth, sensor accuracy and anti-interference capability, without magnetic saturation. The double pulse tests results validated that the PCB embedded current sensor meets the requirements for measuring the current of SiC devices. © 2024 ieee.

关键词： Polychlorinated biphenyls

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Initial Investigation of Physically Tightly-Coupled Single-chip MEMS IMU for Mutual Compensation of two Differential Resonant Accelerometers and a Mode-Matched Donut-Mass Gyroscope

Initial Investigation of Physically Tightly-Coupled Single-C...

引用

ieee Sensors conference

作者： Miyazaki, Fumito Ono, Daiki Ogawa, Jumpei Tomioka, Tazuko Masunishi, Kei Uchida, Kengo Murase, Hideaki Ogawa, Etsuji Ishibashi, Fumitaka Tomizawa, Yasushi Toshiba Co Ltd Corp Res & Dev Ctr Kawasaki Kanagawa Japan

ISBN: (纸本)9798350303872

In this study, we report an initial study on mutual compensation between a differential resonant accelerometer (DRA) and a donut-mass gyroscope (DMG). High-precision inertial measurement units (IMUs) require compensation for temperature drift and multi-axis sensitivity in addition to the development of high-precision sensors. One effective means for achieving this is to integrate each sensor into a single chip. DRAs are suitable for IMUs because they can separate the main sensitivity acceleration and temperature drift components from the resonance frequencies of the two beams. We developed the first single-chip that integrates two DRAs with XY-axis sensitivity and a high-precision DMG capable of acquiring Z-axis angular velocity and conducted an initial evaluation using a microcontroller-based module. We demonstrated linear operation of the DMG by applying angular velocities of +1, 5, 10, and 50 deg/s, and found high agreement (R-2 = 0.9826, 0.9965) with the frequencies of DMG and DRA corrected for multi-axis sensitivity of the DRA when +/- 1 G acceleration was applied in the X, Y, and Z-axes.

关键词： MEMS IMU single chip differential resonant accelerometer donut-mass gyroscope microcontroller module multi-axis sensitivity

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Barre Chord: Efficient Virtual Memory Translation for multi-chip-module GPUs 51

Barre Chord: Efficient Virtual Memory Translation for Multi-...

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ACM/ieee 51st Annual International Symposium on Computer Architecture (ISCA)

作者： Feng, Yuan Na, Seonjin Kim, Hyesoon Jeon, Hyeran Univ Calif Merced CA 95343 USA Georgia Inst Technol Atlanta GA 30332 USA

ISBN: (纸本)9798350326598;9798350326581

With the advancement of processor packaging technology and the looming end of Moore's law, multi-chip-module (MCM) GPUs become a promising architecture to continue the performance scaling. However, due to the increasing concurrency, it is challenging to achieve scalable performance. In this study, we show that the limited parallelism in IOMMU is one of the critical bottlenecks and propose Barre Chord to fundamentally reduce the translation loads. By leveraging the unique GPU execution model and page mapping on MCM-GPUs, Barre translates virtual addresses in a unit of coalescing group. Once one page is translated, all the other pages within the same coalescing group can be translated with simple calculations without page table walks. Full Barre (F-Barre) further reduces translations by enabling intra-MCM translation through coalescing information sharing across GPU chiplets and contiguity-aware coalescing group expansion. With the combination of Barre and F-Barre, the Barre Chord outperforms state-of-the-art solutions by an average of 1.36x (2.09x with coalescing group expansion) with negligible area overhead (4.22% of a GPU L2 TLB).

关键词： Program processors

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Research on Influencing Factors of chip Dynamic Current Distribution in IGBT module

Research on Influencing Factors of Chip Dynamic Current Dist...

引用

2023 ieee Sustainable Power and Energy conference, iSPEC 2023

作者： Meiting, Cui Zhongyuan, Chen Hongji, Li Beijing Institute of Smart Energy 102209 Chang Ping District Beijing China

ISBN: (纸本)9798350322699

IGBT (Insulated-gate bipolar transistor) modules are generally composed of multiple chips in parallel. Due to the difference of chip parameters and package parasitic parameters, the current distribution of each chip is not completely consistent. The dynamic current dispersion of the chip is the result of coupling of multiple parameters in multiple stages of the switching process. The analysis of the factors that affect the internal dynamic current distribution, the influence mechanism and degree of each factor has a good reference significance for safe and reliable operation of IGBT module. Firstly, the multi-chip paralleled IGBT module model and test circuit model including internal parasitic parameters are introduced in this paper. Then, the factors affecting the unbalanced distribution of dynamic current in different switching periods are analyzed. Finally, a double-pulse simulation circuit is built to study the influence of each factor on the collector current by controlling a single variable, and the sensitivity of each factor to the dynamic current distribution is determined. The conclusion of this paper can provide reference for the parameter design and optimization of IGBT module in parallel package, which further promote the stable and reliable operation of the power system. © 2023 ieee.

关键词： Dynamic current IGBT multi-chip paralleled Simulation analysis

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An Integrated Dual Channel LTCC Front-End module for mm-Wave Communication Systems 54

An Integrated Dual Channel LTCC Front-End Module for mm-Wave...

引用

54th European Microwave conference (EuMC)

作者： Wang, Xiyu Zhang, Ruiqiang Cui, Kai Lie, Wenming Wang, Dehan Zhang, Yu ZTE Corp State Key Lab Mobile Network & Mobile Multimedia Shenzhen Peoples R China ZTE Corp Shenzhen Peoples R China

ISBN: (纸本)9798350385892;9782874870774

This paper presents a millimeter wave (mm-wave) dual channel MMIC front-end module (FEM), which is designed in 0.15-mu m GaAs E/D p-HEMT process and integrated into a low temperature co-fired ceramic (LTCC) package. The dual channel MMIC FEM includes two fully symmetrical multi-function transmitter and receiver (T/R) chips. A single T/R module integrates a power amplifier (PA), a low-noise amplifier (LNA), two single-pole double-throw (SPDT) switches, and two power control units. The FEM operates over 24-27.5 GHz and is applied in 5G phased array antennas and mm-wave communication systems. A single T/R chip has a known minimum area of mm-wave GaAs MMIC T/R, which is only 3.5 x 1.5 mm(2). A particular power control unit in this design simplifies complex control logic and power connections of the T/R module. This compact FEM device integrated dual channel design saves the area and cost introduced by using two devices, and has high applicability and practicality.

关键词： 5G dual channel front-end module (FEM) gallium arsenide (GaAs) millimeter wave (mm-wave) monolithic microwave integrated circuit (MMIC) T/R module

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New power delivery network(PDN) approach for extremely large FC-BGA with organic substrate based on over 1mm-thick core 74

New power delivery network(PDN) approach for extremely large...

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ieee 74th Electronic Components and Technology conference (ECTC)

作者： Hwang, Kyojin Jung, Woobin Kim, Junghwa Lee, Heeseok Pak, Junso Hwang, Jisoo Samsung Elect Co Ltd SLSI Business Hwaseong South Korea

ISBN: (纸本)9798350375985;9798350375992

In this paper, the authors propose two solutions for thick embedding capacitor that can be embedded in extremely large Flip chip Ball Grid Array (FC-BGA) Package (PKG) using a Thick Core Substrate (TCS) with thickness of more than 1 mm. Firstly, the authors propose an embedded Capacitor module (eCM) solution. In this solution, it is possible to package multiple capacitors into single capacitor module. To do that, mount multiple multi-Layer Ceramic Capacitor (MLCC) on a substrate with external electrodes made of copper (Cu) and then perform molding. This solution is suitable for embedding capacitors into TCS because it allows control of thickness while packaging multiple capacitors. It also enables implementation of larger capacitance, and customization of size and capacitance according to System on chip (SoC) requirements through the combinations of internal capacitors. Furthermore, it is effective for improving Power Delivery Network (PDN) performance as it allows to directly connect capacitance to the desired IP blocks according to SoC package design. Secondly, the authors propose Through Silicon Via (TSV)-based Stacked Silicon Capacitor (SSC). As presented by authors' another paper [1], TSV-based SSC can be used for embedded Capacitor (eCAP) with TCS. A SSC is created by producing silicon capacitor wafers with applied TSV and stacking two identical wafers through wafer-to-wafer bonding. Repeat this process N times to fabricate SSC that consists of N silicon capacitors. SSC provides lower Equivalent Series Inductance (ESL) characteristics and N times higher capacitance compared to conventional silicon capacitors. SSC can be manufactured with the same thickness as that of the core layer of TCS. Additionally, SSC makes shortcut PDN design between die bumps and PKG balls through TSV, which further enhances PDN performance. This paper provides a comparative study on PDNs that are designed using Die Side Capacitor (DSC) versus PDNs that are designed using eCM and TSV-b

关键词： Embedding capacitor module Stacked silicon capacitor TSV silicon capacitor Thick core based large package

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