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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

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Substrate Design of a 3-D Microwave Front-end multi-chip module with Antennas Integrated 16

Substrate Design of a 3-D Microwave Front-end Multi-Chip Mod...

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16 int conf elect packaging technology

作者： Wu, Peng He, Huimin He, Yi Wan, Lixi Liu, Fengman Li, Jun Cao, Liqiang Chinese Acad Sci Inst Microelect Beijing Peoples R China Natl Ctr Adv Packaging Wuxi Peoples R China

ISBN: (纸本)9781467379991

This paper demonstrates the substrate design considerations of a 3-dimensional (3-D) microwave (MW) multi-chip module (MCM). This module is a dual-band microwave front-end working at Ka-band (Transmit) and K-band (Receive). Three organic substrates are stacked up via ball grid array (BGA), combining a transceiver module with both frequency band antennas integrated. Substrate design needs considerations of multiple aspects. As for active chips, selection and placement of MMICs, bond wire design, Electromagnetic (EM) isolation and thermal management of high power MMICs are of great importance. As for passive components patterned on the substrates, band pass filter, DCAC block and antennas are main devices need to be simulated and optimized.

关键词： Microwave front-end MCM Ka-band Stacked patch antenna

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On-chip AC-DC multiple-power-supplies module for transcutaneously powered wearable medical devices

On-chip AC-DC multiple-power-supplies module for transcutane...

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conference Record of the ieee Industry Applications Society Annual Meeting (IAS)

作者： Yen-Chia Chu Dariusz Czarkowski Jialin Zou H. Jonathan Chao Le-Ren Chang-Chien Chih-Hsiang Chang N. Sertac Artan New York University Brooklyn NY USA National Cheng Kung University Tainan City Taiwan New York Institute of Technology New York NY USA

ISBN: (纸本)9781479983988

Conventional wearable medical devices need batteries to sustain reliable power for the circuits. Battery replacement is usually inconvenient to the user experience. Wireless power transfer (WPT) could be the solution for this problem. However, wearable medical devices have their intrinsic specifications that could be challenges to the WPT. Their structures should be concise for the wearable needs. Power efficiency should be made as high as possible for prolonging the user experience. Besides, more computing based algorithms embedded in these devices would require more power consumption. How to fulfill these specifications is the aim of this research work. This paper proposes a wireless power processing module that integrate AC-DC and multi- DC-DC power circuits together for wearable medical devices. The AC-DC circuit is specifically designed using a concise topology to enhance power conversion efficiency. The DC power is further regulated by different mode controls to facilitate battery charging or to provide multiple voltage outputs. The integrated circuit is implemented by a 0.25 μm high voltage CMOS process with 1.9 μm × 2.3 μm circuit dimensions.

关键词： Switches Rectifiers

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DELPHI Style Extraction and Validation of Compact Model for a multichip module Package 17

DELPHI Style Extraction and Validation of Compact Model for ...

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17th ieee Electronics Packaging and Technology conference (EPTC)

作者： Yaddanapudi, Vamsi Krishna Kulkarni, Aniket Abhay Adhiya, Ankit Nagulapally, Manoj Tan, Desmond ANSYS Inc Rajiv Gandhi Infotech PkHinjevvadi Phase 1 Pune 411057 Maharashtra India ANSYS Inc Software Dev Austin TX 78746 USA ANSYS Inc Singapore 117684 Singapore

ISBN: (纸本)9781424451005

DELPHI style compact model generation for single chip packages is an electronics industry standard proposed by the JEDEC council. Such compact network models are boundary condition independent and ensure that junction temperatures are predicted within 10% [7] compared to the predicted detailed package temperatures. These models replace detailed modeling of packages in system level CFD simulations. With the recent trend of packing more and more functionality onto a single package, multi-chip modules (MCM) kind of packages are becoming more prevalent. MCM packages have more than one functional block (chip) and the DELPHI methodology is no longer applicable directly to MCM packages. In this paper, an extended method has been proposed to extract DELPHI style network models for a multi-chip module packages. ANSYS Icepak is used to model and validate the new method by comparing its temperature predictions with a detailed package. The proposed method uses a combination of the JEDEC proposed method and a linear superposition technique to predict junction temperatures of MCM packages. Linear superposition method takes in to account the interdependency of chips with each other, whereas the DELPHI method is based on a boundary condition independent technique. Also, an additional study is also carried out to understand the effect of proximity of chips and its impact on the comparisons with the detailed CFD model.

关键词： Junction temperature

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Study on Electrical Performance of Stacking Die Package with Silicon Interposer 16

Study on Electrical Performance of Stacking Die Package with...

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16 int conf elect packaging technology

作者： Chen, Shan Li, Cheng Chen, Yu Zhang, Wenjie Zhong, Jianhua Cai, Jian Tsinghua Univ Inst Microelect Beijing 100084 Peoples R China State Key Lab Cryptol Beijing 100878 Peoples R China Tsinghua Natl Lab Informat Sci & Technol Beijing 100084 Peoples R China

ISBN: (纸本)9781467379991

As one kind of effective integration structure, die stacking is widely used in advanced packaging designs, like System in Package (SiP), chip Scale Package (CSP), multi-chip module (MCM), etc. Conventional design of the stacking structure highly depends on parameters of the chip design, such as die size and bonding pad distribution. In this paper, stacking structure of a Processor module package with silicon interposer has been designed. Electrical performance of different interconnection paths, mainly focused on output of the upper chip, was evaluated through electromagnetic simulation. Results showed that using silicon interposer can not only decrease failure risks of long wire bonding, but also improve electrical performance of interconnection in comparison to direct long bonding wire structures. Moreover, as partial interconnections are realized on interposer, routing space of package substrate would be increased, which helps to further reduce package size.

关键词： die stack package design interposer S parameters electromagnetic simulation

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A Double-End Sourced multi-chip Improved Wire-bonded SiC MOSFET Power module Design

A Double-End Sourced Multi-Chip Improved Wire-bonded SiC MOS...

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Annual ieee Applied Power Electronics conference and Exposition

作者： Miao Wang Fang Luo Longya Xu Department of Electrical and Computer Engineering The Ohio State University Columbus Ohio United States of America

ISBN: (纸本)9781467395519

This paper proposes an improved wire-bonded design with a unique double-end sourced (DES) structure for multi-chip paralleled silicon carbide (SiC) power modules. The new structure adopts two pairs of DC bus-bars to source the power module from the two ends, not only shortens the equivalent power loops but also provides a symmetrical structure for the paralleled devices. The proposed design achieved a minimized power-loop inductance of 7.2 nH. In addition, the design improved current sharing among the paralleled devices. A 1200 V, 60 A SiC metal-oxide-semiconductor field-effect-transistor (MOSFET) half-bridge module (3 devices in parallel) is fabricated and tested for verification. Improved performances are observed in both switching and continuous operation. A converter level design is also presented to accommodate this unique module structure.

关键词： multi-chip power module wire-bonded power-loop inductance silicon carbide metal-oxide-semiconductor field-effect-transistor double-end sourced current-sharing

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DEVELOPMENT OF SIC multi-chip module FOR PULSE SWITCHING AT 10 KV, 100 KA

DEVELOPMENT OF SIC MULTI-CHIP MODULE FOR PULSE SWITCHING AT ...

引用

2015 ieee Pulsed Power conference (PPC)

作者： O'Brien, H. Ogunniyi, A. Shaheen, W. Scozzie, C. J. Temple, V. US Army Res Lab 2800 Powder Mill Rd Adelphi MD 20783 USA Berkeley Res Associates Inc Beltsville MD USA Silicon Power Corp Clifton Pk NY USA

ISBN: (纸本)9781479984039

The Army Research Laboratory collaborated with Silicon Power Corporation to package sixteen parallel 9 kV, 1.0 cm(2) silicon carbide (SiC) super gate turn-off thyristors (SGTOs) in a single 82 cm(3) module using Silicon Power's materials and techniques from silicon packaging. The peak current switched was 84 kA for a 43-mu s pulse width as measured at half-maximum. The rising slope calculated from 10-90% of the peak was 10 kA/mu s, and the action under the curve was 2.6 x 10(5) A(2)s. Results encouraged further development of larger-area devices with higher 15 kV blocking in order to fully utilize the package area and create a single-layer >10 kV pulse switch. Challenges in the development of this SiC SGTO module include optimizing SiC material uniformity and device yield, controlling turn-on of sixteen parallel devices, and maximizing high-voltage blocking of the complete package.

关键词： Anodes Contacts Logic gates Silicon Silicon carbide Switches Voltage measurement

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Design, Setup and Test of a Heterogeneous module and Characterization by Stress Measurement 20

Design, Setup and Test of a Heterogeneous Module and Charact...

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20th European Microelectronics Packaging conference And Exhibition (EMPC)

作者： Schreier-Alt, Thomas Reitlinger, Claus Kaul, Franz Metzger, Thomas Revenberg, Kees Fraunhofer IZM Berlin Germany EPCOS AG Munich Germany MASER Enschede Netherlands

ISBN: (纸本)9780956808622

This paper presents design, setup and test of a heterogeneous antenna tuner module and its characterization by stress measurements. Key features provided for this integration platform are a small module size in combination with a low module height, a good RF performance, good heat dissipation capabilities, high electrical and thermomechanical reliability also supporting the low pressure encapsulation of MEMS cavity packages, a compatibility with a small pitch (150 mu m) of the devices to be assembled, and high cost efficiency. Based on multi-layer substrates, modules have been designed to develop a low pressure molding process (max. pressure of 30 bar) and to integrate a fine pitch flip chip technology (max. pitch of 150 mu m). Whereas encapsulation with a transfer molding process at pressures below 25 bar did not show promising results, especially with respect to reliability issues due to insufficient underfilling of the assembled components, a newly developed compression molding process shows good results and full compatibility with the cavity packages for MEMS devices. The molding process development was supported by stress measurements utilizing special stress measurement chips mounted on the module by diebonding and wire bonding process. With this method the stress distribution after the molding process and due to reliability testing could be monitored and both process and design optimization could be done to avoid stress peaks as well as to guarantee a sufficient underfilling of the assembled components.

关键词： Antennas

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The development of remote monitoring system for cultivation environment of Pleurotus eryngii

The development of remote monitoring system for cultivation ...

引用

ieee International conference on Information and Automation 2015

作者： Zhao, Li Zhu, Xuejun Ningxia Univ Sch Mech Engn Yinchuan Ningxia Provinc Peoples R China

ISBN: (纸本)9781467391047

Aiming at the defects of the existing technology for Pleurotus eryngii cultivation environment monitoring system in Ningxia Pengyang County, such as: transmission of the data is not stable, small monitoring range and the sensors cannot move conveniently, only the environmental data in a fixed position within each mushroom shed can be collected, need to lay a lot of cables between the collector and the sensors, wiring difficulty, high cost etc., this system is designed a low-cost remote monitoring of digital information platform to automatically, accurately, and remote wirelessly monitor the environmental temperature, humidity, light intensity and carbon dioxide concentration in eight Pleurotus greenhouse simultaneously, based on single-chip, the integrated application of multi sensor fusion technology, Bluetooth wireless transmission technology, GPRS wireless remote transmission technology, combined with the wireless RF module NRF905 set up a tree network structure, the PC monitor centre was developed based on the software LabVIEW. The environmental control equipment heater, refrigerator, fan and shower facilities in each Pleurotus shed can be manually and automatically controlled remotely. The real-time environmental data can also be stored and managed as EXCEL files. This study provides effective technical support for establishing the growth model of Pleurotus eryngii and forming the control strategy of saving energy, so as to improve the quality and yield of Pleurotus eryngii.

关键词： Pleurotus eryngii remote monitoring Wireless RF module Bluetooth LabVIEW

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Electro-Thermo-Mechanical Analyses on Silver Sintered IGBT-module Reliability in Power Cycling 16

Electro-Thermo-Mechanical Analyses on Silver Sintered IGBT-M...

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16th ieee International conference on Thermal, Mechanical and multiphysics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE)

作者： Dudek, R. Doering, R. Rzepka, S. Ehrhardt, C. Guenther, M. Haag, M. Fraunhofer ENAS Micro Mat Ctr Chemnitz Chemnitz Germany Fraunhofer IZM Berlin Germany Robert Bosch GmbH CR APJ3 Stuttgart Germany Bertrandt Ingenieurbuero GmbH Ingolstadt Germany

ISBN: (纸本)9781479999507

New demands on the thermo-mechanical design of sintered silver interconnections emerge. Development of this interconnection technology and both experimental and theoretical studies on their reliability were subjects of the project "PROPOWER". The focus of this paper is on theoretical analysis of thermo-mechanical reliability risks of a project demonstrator, an insulated-gate bipolar transistor (IGBT) module, subjected to power cycling loadings. Coupled electro-thermal-mechanical analyses have been carried out using the finite element method (FEM). Introduction of a new interconnect material means at the same time introduction of a new constitutive behavior and new failure modes. As the material stiffness increases, the decoupling effect of compliant solder layers reduces and intrinsic mechanical stresses increase in the whole power stack. This leads on one hand to less low cycle fatigue in the interconnect, as plastic dissipation is reduced, but on the other hand to higher failure risks like brittle cracking and sub-critical crack growth. However, if early brittle failure can be avoided by appropriate designs, the new interconnection technology allows an increase in fatigue reliability of several hundred percent. Based on the complex theoretical framework simulation results are validated by testing in order to achieve trustworthy thermo-mechanical reliability predictions. Failures like chip metallization damage and the different damage mechanisms of the die bond if either solder or sinter silver is used are related to the different stress situations in the module.

关键词： Power cycles material stiffness collapse mechanism FAILURE MODES brittle cracking thermo-mechanical insulated gate bipolar transistors Finite element method Silver Theoretical Study

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2015 ieee 24th conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015

2015 IEEE 24th Conference on Electrical Performance of Elect...

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24th ieee conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2015

ISBN: (纸本)9781479936410

The proceedings contain 51 papers. The topics discussed include: design of on-chip linear regulator module and measurement of power distribution network noise fluctuation at high-speed output buffer;interconnected capacitors for effective power delivery noise suppression across domains;statistical analysis via generalized decoupled polynomial chaos;enhanced macromodels of high-speed low-power differential drivers;application of CMA evolution strategy to synthesis of multi-resonance SPICE models up to 20 GHz;on the low frequency theory of characteristic mode;hierarchical modeling and scalable algorithms for in-situ analysis of integrated circuit packages;evaluation of near-singular integrals for quadrilateral basis in integral equation solver;the effect of temperature on performance of a RF CMOS power amplifier and bond wires;prediction of near-field shielding effectiveness for conformally-shielded SiP using a magnetic probe;and global sensitivity based dimension reduction for fast variability analysis of nonlinear circuits.

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