检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

530 篇 会议
10 篇 期刊文献

馆藏范围

540 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

397 篇 工学
- 261 篇 电气工程
- 152 篇 电子科学与技术（可...
- 120 篇 计算机科学与技术...
- 59 篇 材料科学与工程（可...
- 53 篇 信息与通信工程
- 52 篇 软件工程
- 35 篇 机械工程
- 27 篇 仪器科学与技术
- 27 篇 化学工程与技术
- 26 篇 动力工程及工程热...
- 21 篇 控制科学与工程
- 17 篇 冶金工程
- 16 篇 石油与天然气工程
- 13 篇 光学工程
- 10 篇 航空宇航科学与技...
- 7 篇 建筑学
- 6 篇 土木工程
- 5 篇 力学（可授工学、理...
- 4 篇 轻工技术与工程
- 4 篇 核科学与技术
104 篇 理学
- 72 篇 物理学
- 25 篇 化学
- 19 篇 数学
- 4 篇 生物学
24 篇 管理学
- 23 篇 管理科学与工程(可...
- 7 篇 工商管理
8 篇 医学
- 5 篇 临床医学
- 5 篇 特种医学
5 篇 经济学
- 5 篇 应用经济学
3 篇 军事学

主题

61 篇 multichip module...
25 篇 silicon
25 篇 multi-chip modul...
24 篇 packaging
23 篇 microprocessor c...
22 篇 switches
20 篇 substrates
19 篇 electronics pack...
18 篇 silicon carbide
16 篇 assembly
13 篇 costs
13 篇 integrated circu...
12 篇 radio frequency
11 篇 multichip module
11 篇 logic gates
11 篇 inductance
10 篇 bonding
10 篇 finite element a...
10 篇 ceramics
9 篇 reliability

机构

4 篇 univ alabama dep...
4 篇 hypres inc elmsf...
3 篇 stanford univ st...
2 篇 shanghai aerospa...
2 篇 marvell burnaby
2 篇 marvell
2 篇 jst tsukuba ibar...
2 篇 sun microsystems...
2 篇 caltech jet prop...
2 篇 georgia inst tec...
2 篇 tyndall natl ins...
2 篇 guilin univ elec...
2 篇 univ alabama dep...
2 篇 micromodule syst...
2 篇 center for integ...
2 篇 fraunhofer izm
2 篇 micromodule syst...
2 篇 shenzhen smartch...
2 篇 academy of infor...
2 篇 keio university ...

作者

4 篇 yorozu shinichi
4 篇 miyazaki toshiyu...
4 篇 lemmon andrew n.
3 篇 paolo mattavelli
3 篇 luo le
3 篇 dai wayne wei-mi...
3 篇 lu hua
3 篇 boroyevich dusha...
3 篇 wang li
3 篇 brian hughes
3 篇 ning puqi
3 篇 castellazzi albe...
3 篇 pence w.e.
3 篇 bailey chris
3 篇 dushan boroyevic...
3 篇 lemmon andrew
3 篇 hughes brian
3 篇 mattavelli paolo
2 篇 zhang tao
2 篇 kameda yoshio

语言

529 篇 英文
7 篇 中文
4 篇 其他

检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 540 条记录，以下是201-210 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Approximation-Aware multi-Level Cells STT-RAM Cache Architecture

Approximation-Aware Multi-Level Cells STT-RAM Cache Architec...

引用

International conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)

作者： Sampaio, Felipe Shafique, Muhammad Zatt, Bruno Bampi, Sergio Henkel, Joerg Univ Fed Rio Grande do Sul PPGC Inst Informat BR-90046900 Porto Alegre RS Brazil Karlsruhe Inst Technol CES D-76021 Karlsruhe Germany Fed Univ Pelotas UFPel CDTec PPGC GACI Pelotas RS Brazil Fed Inst Rio Grande Sul IFRS Bento Goncalves RS Brazil

ISBN: (纸本)9781467383202

Current manycore processors exhibit large on-chip last-level caches that may reach sizes of 32MB - 128MB and incur high power/energy consumption. The emerging multi-Level Cells (MLC) STT-RAM memory technology improves the capacity and energy efficiency issues of large-sized memory banks. However, MLC STT-RAM incurs non-negligible protection overhead to ensure reliable operations when compared to the Single-Level Cells (SLC) STT-RAM. In this paper, we propose an approximation-aware MLC STT-RAM cache architecture, which is partially-protected to restrict the reliability overhead and in turn leverages variable resilience characteristics of different applications for adaptively curtailing the protection overhead under a given error tolerance level. It thereby improves the energy-efficiency of the cache while meeting the reliability requirements. Our cache architecture is equipped with a latency-aware hardware module for double-error correction. To achieve high energy efficiency, approximation-aware read and write policies are proposed that perform approximate storage management while tolerating some errors bounded within the user-provided tolerance level. The architecture also facilitates run-time control on the quality of applications' results. We perform a case study on the next-generation advanced video encoding that exhibit memory-intensive functional blocks with varying resilience properties and support for parallelism. Experimental results demonstrate that our approximation-aware MLC STT-RAM based cache architecture can improve the energy efficiency compared to state-of-the-art fully-protected caches (7%-19%, on average), while incurring minimal quality penalties in the output (-0.219% to -0.426%, on average). Furthermore, our architecture supports complete error protection coverage for all cache data when processing non-resilient application. The hardware overhead to implement our approximation-aware management negligibly affects the energy efficiency (0.15%-1.3%

关键词： cache storage error correction memory architecture multiprocessing systems power aware computing random-access storage reliability MLC STT-RAM memory technology access latency approximate storage management approximation-aware MLC STT-RAM based cache architecture approximation-aware MLC STT-RAM cache architecture approximation-aware management approximation-aware multilevel cell STT-RAM cache architecture approximation-aware read and write policies cache architecture cache data double-error correction energy consumption energy efficiency error protection error tolerance level latency-aware hardware module manycore processors memory banks memory-intensive functional blocks next-generation advanced video encoding nonresilient application processing on-chip last-level caches power consumption runtime control storage management user-provided tolerance level Energy efficiency Store management Memory Bank power aware computing random access machine error protection multiprocessing systems cache storage Memory architecture Cache memory error correction Building construction ARCHITECTURE Power consumption energy consumption

来源：评论

学校读者我要写书评

暂无评论

Organic multi-chip module for high performance systems

Organic Multi-Chip Module for high performance systems

引用

Electronic Components and Technology conference (ECTC)

作者： Lei Shan Young Kwark Christian Baks Michael Gaynes Timothy Chainer Mark Kapfhammer Hajime Saiki Atsushi Kuhara Gil Aguiar Noritaka Ban Yoshiki Nukaya IBM T J Watson Research Center NY Yorktown Heights IBM Semiconductor Research Development Center New York Hopewell Junction NTK Technologies Nagoya Japan

ISBN: (纸本)9781479986101

In this work, IBM Research and NTK Technologies have explored the development of an organic multi-chip module (MCM) solution, with the goal of developing innovative technologies that address the requirements of high performance systems. A 90 × 90 mm organic MCM was designed, fabricated, and assembled with dual side mountable 24 × 28 mm thermal test chips mounted on chip-scale interposers to enable functional screening and rework process. The work demonstrated that a large scale organic MCM was compatible with LGA sockets with over 6000 contacts.

关键词： Substrates Thermal stresses Transmission line measurements Ceramics Assembly Gold Wiring

来源：评论

学校读者我要写书评

暂无评论

All solid-state multi-chip multi-channel WDM photonic module

All solid-state multi-chip multi-channel WDM photonic module

引用

Electronic Components and Technology conference (ECTC)

作者： I. Shubin X. Zheng H. Thacker S. S. Djordjevic S. Lin P. Amberg J. Lexau K. Raj J. E. Cunningham A. V. Krishnamoorthy Oracle San Diego CA USA

In this work we report on a packaged prototype of a WDM photonic transceiver. It is a hybrid assembly based on a 130 nm SOI photonic circuitry integrated with a 40 nm CMOS VLSI driver. Our prototype supports eight tunable WDM channels operating at 10 Gb/s each capable of both transmitting and receiving data on the same chip. We discuss two options to close the link while using the optical fiber or another waveguide bridge chip. We provide hybridization details and supporting link measurement data to describe packaged photonic module and its power efficient functionality as its on-chip power per channel averaged 1.3pJ/bit, laser electrical power excluded.

关键词： Photonics Very large scale integration Couplers Wavelength division multiplexing Optical fibers Silicon

来源：评论

学校读者我要写书评

暂无评论

DELPHI Style Extraction and Validation of Compact Model for a multichip module Package

DELPHI Style Extraction and Validation of Compact Model for ...

引用

ieee Electronics Packaging Technology conference

作者： Vamsi Krishna Yaddanapudi Aniket Abhay Kulkarni Ankit Adhiya Manoj Nagulapally Desmond Tan ANSYS Inc. Software Development ANSYS Inc.

ISBN: (纸本)9781467372701

DELPHI style compact model generation for single chip packages is an electronics industry standard proposed by the JEDEC council. Such compact network models are boundary condition independent and ensure that junction temperatures are predicted within 10% [7] compared to the predicted detailed package temperatures. These models replace detailed modeling of packages in system level CFD simulations. With the recent trend of packing more and more functionality onto a single package, multi-chip modules (MCM) kind of packages are becoming more prevalent. MCM packages have more than one functional block (chip) and the DELPHI methodology is no longer applicable directly to MCM packages. In this paper, an extended method has been proposed to extract DELPHI style network models for a multi-chip module packages. ANSYS Icepak is used to model and validate the new method by comparing its temperature predictions with a detailed package. The proposed method uses a combination of the JEDEC proposed method and a linear superposition technique to predict junction temperatures of MCM packages. Linear superposition method takes in to account the interdependency of chips with each other, whereas the DELPHI method is based on a boundary condition-independent technique. Also, an additional study is also carried out to understand the effect of proximity of chips and its impact on the comparisons with the detailed CFD model.

关键词： Convection Boundary conditions Junctions Graphics processing units Finite element analysis Computational modeling

来源：评论

学校读者我要写书评

暂无评论

Development of SiC multi-chip module for pulse switching at 10 kV, 100 kA

Development of SiC multi-chip module for pulse switching at ...

引用

International conference on Pulsed Power

作者： H. O'Brien A. Ogunniyi W. Shaheen C. J. Scozzie V. Temple U.S. Army Research Laboratory Adelphi MD USA Berkeley Research Associates Beltsville MD USA Silicon Power Corp. Clifton Park NY USA

The Army Research Laboratory collaborated with Silicon Power Corporation to package sixteen parallel 9 kV, 1.0 cm 2 silicon carbide (SiC) super gate turn-off thyristors (SGTOs) in a single 82 cm 3 module using Silicon Power's materials and techniques from silicon packaging. The peak current switched was 84 kA for a 43-μs pulse width as measured at half-maximum. The rising slope calculated from 10-90% of the peak was 10 kA/μs, and the action under the curve was 2.6 × 10 5 A 2 s. Results encouraged further development of larger-area devices with higher 15 kV blocking in order to fully utilize the package area and create a single-layer >10 kV pulse switch. Challenges in the development of this SiC SGTO module include optimizing SiC material uniformity and device yield, controlling turn-on of sixteen parallel devices, and maximizing high-voltage blocking of the complete package.

关键词： Silicon carbide Logic gates Silicon Switches Anodes Voltage measurement Contacts

来源：评论

学校读者我要写书评

暂无评论

Design Considerations for GaN HEMT multichip Half-bridge module for High-Frequency Power Converters

Design Considerations for GaN HEMT Multichip Half-bridge Mod...

引用

29th Annual ieee Applied Power Electronics conference and Exposition (APEC)

作者： Luo, Fang Chen, Zheng Xue, Lingxiao Mattavelli, Paolo Boroyevich, Dushan Hughes, Brian Virginia Tech Ctr Power Elect Syst Blacksburg VA 24061 USA LLC HRL Labs Energy Efficient Elect Dept Malibu CA USA

ISBN: (纸本)9781479923250

This paper discusses the design of a multichip Gallium-Nitride (GaN) power module for high frequency power conversion. The module is designed with HRL 600 V GalliumNitride (GaN) enhancement mode HEMT device. To exploit the capability of fast switching with low loss from high voltage GaN devices, different layout structures have been analyzed to reduce power loop parasitic inductance and improve switching performance. The approach investigated in this paper is based on a multi-chip module where small current rated dies are placed in parallel to achieve higher current handling capability. Moreover, a transmission-line type gate structure has been proposed to minimize the gate loop inductance and reduce the gate voltage ringing. Finite-Element-Analysis (FEA) and switching circuit simulation show that the multi-layer power loop design can effectively reduce the gate loop inductance and voltage overshoot on the devices. This multi-layer design also improves current sharing of the multi-chip module during switching operation. The transmission-line gate design is also proved in both simulation and experiment to be effective for reducing the gate loop inductance as well as gate loop ringing.

关键词： HEMT integrated circuits finite element analysis integrated circuit design microprocessor chips power convertors switching circuits GaN HEMT multichip half- bridge module finite element analysis gate loop inductance reduce high-frequency power converter module transmission-line type gate structure multichip gallium-nitride power module multilayer power loop design switching circuit simulation transmission-line gate design voltage 600 V Capacitors Gallium nitride Inductance Layout Logic gates Packaging Switches

来源：评论

学校读者我要写书评

暂无评论

Reliability Characterization of 2.5D multi-chip module on Board Under Drop Impact

Reliability Characterization of 2.5D Multi-Chip Module on Bo...

引用

International conference on Electronics Packaging (ICEP)

作者： Cheng, Tzu-Hsuan Cheng, Hsien-Chie Chen, Wen-Hwa Huang, Hsin-Yi Chang, Tao-Chih Natl Tsing Hua Univ Dept Power Mech Engn Hsinchu Taiwan

ISBN: (纸本)9784904090107

In the study, the lead-free solder joint reliability and fatigue failure mechanism of an ultra-fine-pitch 2.5D multi-chip module (MCM) on board is predicted under board-level drop impact test according to JEDEC board-level test specification. To achieve the goal, the Input-G method incorporated with finite element (FE) analysis is applied to predict the transient dynamic responses of the 2.5D MCM on board. To demonstrate the effectiveness of the proposed FE model, the calculated results are compared with those obtained from experimental testing. The experimental drop test is performed on the 2.5D MCM on board with or without underfill using a JEDEC-compliant drop tester, and the associated failure mechanism is examined by way of an optical microscope. At last, the dependences of the allowed shock pulse tolerances in JEDEC drop test standard and also underfill are assessed on the dynamic behavior of the solder joints under drop impact.

关键词： Finite element method

来源：评论

学校读者我要写书评

暂无评论

Normally-Off GaN-on-Si multi-chip module Boost Converter with 96% Efficiency and Low Gate and Drain Overshoot

Normally-Off GaN-on-Si Multi-Chip Module Boost Converter wit...

引用

29th Annual ieee Applied Power Electronics conference and Exposition (APEC)

作者： Hughes, Brian Lazar, James Hulsey, Stephen Musni, Marcel Zehnder, Daniel Garrido, Austin Khanna, Raghav Chu, Rongming Khalil, Sameh Boutros, Karim HRL Labs LLC Energy Efficient Elect Dept Malibu CA 90265 USA

ISBN: (纸本)9781479923250

A high efficiency synchronous GaN half-bridge boost converter with fast switching and low overshoot is achieved by minimizing parasitic inductance and critical damping the gate drive. A normally-off GaN-on-Si 2.4kW synchronous half-bridge multi-chip module (MCM) is designed with a power-loop inductance of similar to 4nH using transmission-line techniques to minimize inductance. The gate circuit inductance is reduced to 1nH using bare MOSFET die for driving the GaN gates and a 0.5mil flexible substrate gate transmission-line. Configured as a boost converter with no added gate resistance, the synchronous half-bridge switches 400V in only 1.3ns. The high voltage slew rates of 325V/ns results in overshoot of 200V on the drain and 4V overshoot on the gate, both of which may damage the GaN switches. Critically damping the gate turn-on reduces overshoot to safe levels of 1V gate overshoot and similar to 20V drain overshoot. The gate damping increases drain fall time to 3ns, which only decreases efficiency by 0.2% at 1MHz. The resulting synchronous boost converter has an efficiency of 96%, switching 300V at 1MHz with 50% duty cycle and an output power of 2.4kW. The high efficiency of GaN switches and the 0.6C/W thermal resistance of the MCM enable a maximum junction temperature of 65 degrees C.

关键词： III-V semiconductors damping elemental semiconductors flexible electronics gallium compounds inductance multichip modules power MOSFET power semiconductor switches power transmission lines silicon switching convertors thermal resistance thyristors wide band gap semiconductors GaN switches GaN-Si MCM bare MOSFET die critical damping minimization drain overshoot flexible substrate gate transmission line frequency 1 MHz gate circuit inductance gate damping gate drive gate overshoot high voltage slew rates normally-off GaN-on-Si multichip module boost converter parasitic inductance minimization power 2.4 kW power loop inductance synchronous GaN half bridge boost converter synchronous half-bridge switches thermal resistance time 1.3 ns voltage 1 V voltage 200 V voltage 300 V voltage 4 V voltage 400 V Gallium nitride Inductance Logic gates Resistance Silicon Substrates Switches

来源：评论

学校读者我要写书评

暂无评论

Built-In Reliability Design of a High-Frequency SiC MOSFET Power module

Built-In Reliability Design of a High-Frequency SiC MOSFET P...

引用

International Power Electronics conference (IPEC-ECCE-ASIA)

作者： Li, Jianfeng Gurpinar, Emre Lopez-Arevalo, Saul Castellazzi, Alberto Mills, Liam Univ Nottingham Power Elect Machines & Control Grp Nottingham NG7 2RD England

ISBN: (纸本)9781479927050

A high frequency SiC MOSFET-based three-phase, 2-level power module has been designed, simulated, assembled and tested. The design followed a built-in reliability approach, involving extensive finite-element simulation based analysis of the electro-thermo-mechanical strain and stress affecting the switch during both manufacturing and operation: structural simulations were carried out to identify the materials, geometry and sizes of constituent parts which would maximize reliability. Following hardware development, functional tests were carried out, showing that the module is suitable for high switching frequency operation without impairing efficiency, thus enabling a considerable reduction of system-level size and weight.

关键词： SiC MOSFET multi-chip power modules reliability

来源：评论

学校读者我要写书评

暂无评论

Bi-directional PHEV Battery Charger based on Normally-off GaN-on-Si multi-chip module

Bi-directional PHEV Battery Charger based on Normally-off Ga...

引用

29th Annual ieee Applied Power Electronics conference and Exposition (APEC)

作者： Xue, Lingxiao Shen, Zhiyu Mu, Mingkai Boroyevich, Dushan Burgos, Rolando Hughes, Brian Mattavelli, Paolo Virginia Tech Ctr Power Elect Syst Blacksburg VA 24061 USA LLC HRL Labs Malibu CA USA DTG Univ Padua Padua Italy

ISBN: (纸本)9781479923250

A high frequency, high efficiency bi-directional battery charger for Plug-in Hybrid Electric Vehicle (PHEV) is built with high voltage normally-off GaN-on-Si HFETs. The battery charger topology consists of a 500 kHz Full Bridge (FB) AD/DC stage and a 500 kHz Dual Active Bridge (DAB) DC/DC stage. The system functionality is verified and measured efficiency is 97% for the AC/DC stage and 97.2% for the DC/DC stage, which leads to a total efficiency 94.2%. By doing sinusoidal charging, the DC link capacitance can be reduced to much less than one third but efficiency will drop to 92.0%.

关键词： III-V semiconductors battery chargers battery powered vehicles elemental semiconductors gallium compounds high electron mobility transistors hybrid electric vehicles multichip modules silicon wide band gap semiconductors DAB DC link capacitance GaN HFETs Si battery charger topology bidirectional PHEV battery charger dual active bridge DC-DC stage efficiency 94.2 percent efficiency 97 percent efficiency 97.2 percent frequency 500 MHz full bridge AD-DC stage high frequency high efficiency bidirectional battery charger normally-off multichip module plug-in hybrid electric vehicle sinusoidal charging system functionality Batteries Bridge circuits Capacitance Gallium nitride Inductors Switches Zero voltage switching

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共54页 << < 17 18 19 20 21 22 23 24 25 26 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：