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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 540 条记录，以下是221-230 订阅

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Thermal Characterization and Simulation Study of 2.5D Packages with multi-chip module on Through Silicon Interposer

Thermal Characterization and Simulation Study of 2.5D Packag...

引用

Proceedings of the 2013 ieee 15th Electronics Packaging Technology conference (EPTC)

作者： Zhang, H. Y. Zhang, X. W. Lau, B. L. Lim, Sharon Ding, Liang Yu, M. B. Lee, Y. J. Inst Microelect Singapore 117685 Singapore

ISBN: (纸本)9781479928347;9781479928323

Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6x10.9mm and 8mmx8mm respectively, are arranged on the interposer through the nip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08x5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA, Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.

关键词： Silicon

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A Cooperative Power Management with Auto-Configured multi-Phase Control and Real-Time Power module Swap

A Cooperative Power Management with Auto-Configured Multi-Ph...

引用

9th ieee Asian Solid-State Circuits conference (A-SSCC)

作者： Tsai, Jen-Huan Huang, Shin-Jie Lan, Po-Hsing Huang, Po-Chiun Natl Tsing Hua Univ Hsinchu Taiwan

ISBN: (纸本)9781479902774;9781479902804

For high power efficiency and better signal integrity, distributed power modules with sophisticated management control are popular in modern SiP, SoC and 3D-IC designs. To dynamically and extensively utilize the idle and redundant power modules, this work applies a cooperative concept for on-chip power management. Current control is used to balance the load for distributed power modules. An estimator with digital engine executes intelligent actions such as real-time adding/dropping power modules depending on load and thermal conditions. It automatically configures the power system with proper phase interleaving. In the prototype chip using 0.35-mu m CMOS, four modules are connected as a co-operative power network to convert 2.7V to 4.3V input to 1.8V output voltage with less than 25mV ripple. PFM achieves 76% efficiency under 20mA load. 88% power efficiency in PWM with four cooperative modules is 8.5% higher than that with single module under 300mA load.

关键词： electric current control integrated circuit design phase control power electronics system-in-package system-on-chip three-dimensional integrated circuits

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5.5GHz System z Microprocessor and multichip module

5.5GHz System z Microprocessor and Multichip Module

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ieee International Solid-State Circuits Flagship conference of the ieee Solid-State-Circuits-Society (ISSCC)

作者： Warnock, James Chan, Yuen H. Harrer, Hubert Rude, David Puri, Ruchir Carey, Sean Salem, Gerard Mayer, Guenter Chan, Yiu-Hing Mayo, Mark Jatkowski, Adam Strevig, Gerald Sigal, Leon Datta, Ayan Gattiker, Anne Bansal, Aditya Malone, Douglas Strach, Thomas Wen, Huajun Mak, Pak-Kin Shum, Chung-Lung Plass, Donald Webb, Charles IBM Syst & Technol Grp Yorktown Hts NY 10598 USA IBM Syst & Technol Grp Poughkeepsie NY USA IBM Syst & Technol Grp Boblingen Germany IBM Res Yorktown Hts NY USA IBM Syst & Technol Grp Williston VT USA IBM Syst & Technol Grp Austin TX USA IBM Syst & Technol Grp Bangalore Karnataka India IBM Res Austin TX USA

ISBN: (纸本)9781467345132;9781467345156

The new System z microprocessor chip (¡°CP chip¡±) features a high-frequency processor core running at 5.5GHz in a 32nm high-¦Ê CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the cores) in order to increase the performance and throughput of the design. Also, special considerations were necessary to ensure robust circuit operation in the high-¦Ê technology used for implementation. As seen in the die photo, the chip contains 6 processor cores (compared to 4 cores in the 45nm version), and a large shared 48MB DRAM L3 cache. Each core includes a pair of data and instruction L2 SRAM caches of 1MB each. In addition, the chip contains a memory control unit (MCU), an I/O bus controller (GX), and two sets of interfaces to the L4 cache chips (also in 32nm technology). The CP chip occupies 598 mm2, contains about 2.75B transistors, and has 1071 signal IOs.

关键词： CMOS integrated circuits field effect MMIC high-k dielectric thin films microprocessor chips multichip modules

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EFFECTIVE 3DIC chip module WARPAGE WITH UF DESIGN BY ANALYTICAL METHOD

EFFECTIVE 3DIC CHIP MODULE WARPAGE WITH UF DESIGN BY ANALYTI...

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8th International Microsystems, Packaging, Assembly and Circuits Technology conference (IMPACT)

作者： Lee, Pai-Yuan Yeh, Chi-Tung Huang, Huei-Nuan Chan, Mu-Hsuan. Lin, Chun-Tang Chiu, Steve Ma, Mike Siliconware Precis Ind Co Ltd Taichung 427 Taiwan

ISBN: (纸本)9781479906673

Three dimensional (3D) stacking technologies have been popular among in high level package that can meet miniaturization trend, high performance, and multi-function electronic products. The interposer where the chips are stacked on is an electrical interface routing between one socket or connection to another. Underfill (UF) material is required to fill in the gap between chip and interposer for protecting u-bumps interconnection. Nevertheless, higher coefficient of thermal expansion (CTE) of UF material to lead chip module of 3DIC package warping, so that to cause bridge or non-wet issue during chip module on substrate process. The purpose of this paper is to study the root cause which influences the warpage of 3D stacked chip module. Firstly, the key factors of underfill material properties were selected by experimental study. Furthermore, The JMP Taguchi Orthogonal Table (L9:3<^>4) & FEM simulation were implemented to get maximize desirability of UF material property in warpage result of chip module. Finally it is concluded that the final warpage results can be successfully predicted to avoid bridge or non-wet issue during chip module on substrate process.

关键词： electric connectors electronics packaging finite element analysis integrated circuit interconnections thermal expansion three-dimensional integrated circuits

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Signal-power integrity and EMI analysis for singlechip and multi-chip-module applications

Signal-power integrity and EMI analysis for singlechip and m...

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2013 15th International conference on Electromagnetics in Advanced Applications, ICEAA 2013

作者： Wane, Sidina Erdem, Aykut Le Grontec, Alexis Tesson, Olivier Bardy, Serge Kloczkowski, Robert Abessolo, Dolphin Mattheijssen, Paul NXP Semiconductors Caen France NXP Semiconductors Nijmegen Netherlands NXP Semiconductors Boston United States

ISBN: (纸本)9781467357074

In this paper, a global chip-Package-PCB Co-Design and Co-Verification methodology is successfully applied to Single-chip Down-converter circuit and multi-chip-module in transmit mode. Full-wave electromagnetic and thermal Co-Analysis approach is adopted to investigate impact of critical RF couplings, power dissipation and grounding strategies on systemlevel performances. The Single-chip down-converter circuit shows 43dB conversion gain, with 6.5dB noise figure and output IP3 of 18dBm. The MCM design demonstrates 35dBm output IP3, 25dBm output CP1, with 45dB image rejection with 25dB voltage gain for a dissipated power of 2.2W. © 2013 ieee.

关键词： Thermoanalysis

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A Process-Based Reconfigurable SystemC module for Simulation Speedup

A Process-Based Reconfigurable SystemC Module for Simulation...

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13th International conference on Embedded Computer Systems - Architectures, Modeling and Simulation (IC-SAMOS)

作者： Sotiriou-Xanthopoulos, Efstathios Siozios, Kostas Economakos, George Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece

ISBN: (纸本)9781479901036

As multi-Processor Systems-on-chip (MPSoC) architectures become more and more complex, Design Space Exploration (DSE) becomes the only viable solution for finding the pareto-optimal designs. To evaluate each solution with real dataset, DSE has to simulate the design under test, which is modeled as a Virtual Platform usually written in SystemC. However, the simulation is a very slow task which includes non-productive time periods like system initialization, while the platform re-compilation also imposes a significant overhead. In this paper, a Process-based Reconfigurable module is used in order to bypass the non-productive simulation parts, thus accelerating the simulation. The effectiveness of the proposed methodology is proved with a series of computationally intensive multimedia applications, where the simulation time improvements reach 34% on average.

关键词： C++ language integrated circuit design multimedia communication multiprocessing systems system-on-chip virtual reality

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Compact Fiber-Coupled THz Photoconductive Antenna module for 1550nm wavelength range

Compact Fiber-Coupled THz Photoconductive Antenna Module for...

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38th International conference on Infrared, Millimeter, and Terahertz Waves (IRMMW-THz)

作者： Zandieh, Alireza Kostakis, Ioannis Missous, Mohamed Safavi-Naeini, Safieddin Saeedkia, Daryoosh TeTechS Inc Waterloo ON Canada Univ Manchester Sch Elect & Elect Engn Manchester M13 9PL Lancs England Univ Waterloo Dept Elect & Comp Engn Waterloo ON N2L 3G1 Canada

ISBN: (纸本)9781467347174

A compact, robust, and portable fiber-coupled THz photoconductive antenna module is described. A new technique is used to focus the output light of the fiber on the chip and fix the fiber in place to provide rugged packaging. THz measurements in pulse mode confirm the performance of this module. The fiber coupled unit is very versatile and can be used in both time domain and frequency domain THz systems. A multi-quantum well InGaAs/InAlAs material is used as the photoconductive material.

关键词： Fibers

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Bi-directional PHEV Battery Charger based on Normally-off GaN-on-Si multi-chip module

Bi-directional PHEV Battery Charger based on Normally-off Ga...

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Annual ieee Applied Power Electronics conference and Exposition

作者： Lingxiao Xue Zhiyu Shen Mingkai Mu Dushan Boroyevich Rolando Burgos Brian Hughes Paolo Mattavelli Center for Power Electronics System Virginia Tech Energy Efficient Electronics Department HRL Laboratories LLC DTG-University of Padova

ISBN: (纸本)9781479923250

A high frequency, high efficiency bi-directional battery charger for Plug-in Hybrid Electric Vehicle (PHEV) is built with high voltage normally-off GaN-on-Si HFETs. The battery charger topology consists of a 500 kHz Full Bridge (FB) AD/DC stage and a 500 kHz Dual Active Bridge (DAB) DC/DC stage. The system functionality is verified and measured efficiency is 97% for the AC/DC stage and 97.2% for the DC/DC stage, which leads to a total efficiency 94.2%. By doing sinusoidal charging, the DC link capacitance can be reduced to much less than one third but efficiency will drop to 92.0%.

关键词： BATTERY CHARGERS gallium nitrate multichip modules TWO-COMPONENT

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2013 International conference on Optical Imaging Sensor and Security, ICOSS 2013

2013 International Conference on Optical Imaging Sensor and ...

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2013 International conference on Optical Imaging Sensor and Security, ICOSS 2013

ISBN: (纸本)9781467361293

The proceedings contain 40 papers. The topics discussed include: FIR filter implementation on reconfigurable hardware for ECG noise reduction;simulation and analysis of improved MPPT algorithm for PV module using Matlab/Simulink;optimized feature selection for enhanced epileptic seizure detection;performance of antenna selection techniques to improve the channel capacity in MIMO systems;a static Bluetooth process continuously depend on a multi-robot sequential analysis;MEMS technology in biomedical sensor application;performance improvement of reconfigurable VLSI architecture;performance analysis of HDM and PCA in teeth image recognition;design and development of organ on chip using microfluidic technology for simulation;prevention of unauthorized entry into the reserved compartment of the train;a robotic colonizer system for identifying and estimation of marine habitats in aqueous environment;and replacement of tte in the railway department with the artificial intelligence.

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Peculiarities of multichip Micro module Frameless Design with Ball Contacts on the Flexible Board

Peculiarities of Multichip Micro Module Frameless Design wit...

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ieee International Scientific conference Electronics and Nanotechnology

作者： D. V. Vertyanov K. S. Tikhonov S. P. Timoshenkov V. S. Petrov G. A. Blinov Department of Microelectronics National Research University of Electronic Technology Moscow Zelenograd Russia Scientific-research Institute Microdevices&Technology Moscow Zelenograd Russia

ISBN: (纸本)9781467346696

New design and technological solution of three-dimensional multi-chip modules has been considered. Installation of bare chips on a flexible board has been done by printed circuit board assembly and external module contacts have performed in the matrix ball pins form. Test program was conducted in order to quantify the limits of the process. Application of flip-chip process to a wide range of customers particularly for 3D packaging has been discussed.

关键词： multichip module Flexible board Flip-chip Golden ball pins Three-dimensional assembly

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