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CLICHE network on chip: A novel multichannel acquisition module for a high throughput architecture

CLICHE network on chip: A novel multichannel acquisition mod...

引用

2012 ieee Long Island Systems, Applications and Technology conference, LISAT 2012

作者： Abdallah, Mohammed Abdelghany, M. SUNYIT United States GUC Egypt

ISBN: (纸本)9781457713439

High throughput and low latency are the desirable characteristics of a multi processing system. CLICHE (chipLevel Integration of Communicating Heterogeneous Elements) is the simplest form of Network-on-chip architecture in terms of the layout and the local interconnections between resources and switches. The throughput varies with the number of virtual channels. When the number of virtual channels is increased, the throughput is increased. On the other hand, the average message latency increases with the number of virtual channels. To keep the latency low while preserving the throughput, the number of virtual channels is constrained to certain number. A novel multichannel signal acquisition module is proposed to integrate IP blocks. The proposed module achieves the optimal solution for large number of virtual channels. It reduces the memory requirement and power consumption as well. A Field Programmable Gate Arrays-based prototype is developed to verify the proposed module. Different case studies are studied in this research. As a result, the proposed module can schedule given tasks that are not schedulable via round-robin technique. Even in scenarios that both round-robin and proposed module can successfully schedule the given task, proposed module reduces the amount of data being acquired by 59%, which in turn decreases memory requirements and power consumption as well. © 2012 ieee.

关键词： Throughput

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High-density mixed signal RF front-end electronics for T-R modules

High-density mixed signal RF front-end electronics for T-R m...

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ieee 1st AESS European conference on Satellite Telecommunications (ESTEL)

作者： Bentini, Andrea Ciccognani, Walter Palomba, Mirko Palombini, Diego Limiti, Ernesto Univ Roma Tor Vergata Dipartimento Ingn Elettron Rome Italy

ISBN: (纸本)9781467346887;9781467346863

In this contribution, several multi-Functional chips featuring different functionalities and integration levels are presented. A X-Band Core-chip integrating a 6-bit attenuator, a 6-bit phase shifter, a T/R switch and a digital serial-to-parallel converter has been fabricated with 0.18 mu M OMMIC ED02AH process. The MMIC exhibits 6 dB and 8 dB average insertion gain for transmit and receive mode respectively, full 360 degrees phase coverage with 5.6 degrees phase steps and 31.5 dB attenuation dynamic range with 0.5 dB amplitude resolution in less than 16 mm(2). Two C-Band multi-Functional chips, one consisting of a bidirectional 6-bit phase shifter with on-board digital controls and the other integrating a 6-bit phase shifter, a buffer amplifier and a 5-bit attenuator have been fabricated with the 0.4 mu m E/D GaAs process developed by SELEX Sistemi Integrati. The former exhibits full 360 degree phase coverage with 5.6 degrees phase resolution in less than 18 mm(2). The latter is an unidirectional MMIC featuring 8 dB average gain, full 360 degree phase coverage with 5.6 degrees phase steps and 31 dB attenuation range with 1 dB amplitude resolution in less than 26 mm(2).

关键词： multifunctional chip Core-chip Mixed-signal MMIC Transmit-Receive module RF Front-end

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A Scalable Digital Pulse Process module for the MRPC Detector of Muon Tomography

A Scalable Digital Pulse Process Module for the MRPC Detecto...

引用

ieee Nuclear Science Symposium / Medical Imaging conference Record (NSS/MIC) / 19th Room-Temperature Semiconductor X-ray and Gamma-ray Detector Workshop

作者： Yue, Xiaoguang Zeng, Ming Deng, Zhi Zeng, Zhi Wang, Xuewu Cheng, Jianping Tsinghua Univ Key Lab Particle & Radiat Imaging Minist Educ Beijing 100084 Peoples R China Tsinghua Univ Dept Engn Phys Beijing Peoples R China Tsinghua Univ Dept Engn Phys Beijing Peoples R China

ISBN: (纸本)9781467320306;9781467320283

Muon tomography with cosmic ray muons is a novel technology for high-Z material detection, which requires large-scale, high-efficiency, high spatial resolution detectors to track the muons. From previous studies, we conclude that the multi-gap resistive plate chamber (MRPC) will be an excellent and inexpensive choice for this application, which also offers the possibility of introducing energy information of muons by TOF measurement to image reconstruction of muon tomography owning to the inherent high time resolution of MRPC. To get enough spatial resolution, the dedicated electronics is required to be able to handle thousands of readout channels. To keep the flexibility of charge and time measurement for detector research purpose, a fast preamp with waveform sampling combined with the Digital Pulse Process (DPP) technology was chosen as the readout solution. At present, an 8-ch current sensitive preamp ASIC has been designed and implemented for the SDPP module, and the switched capacitor array (SCA) chip DRS4 designed by the PSI was chosen as the sampler of the SDPP.

关键词： application specific integrated circuits cosmic ray apparatus particle detectors switched capacitor filters time of flight spectra tomography

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A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

A 7Gb/s/link non-contact memory module for multi-drop bus sy...

引用

59th International Solid-State Circuits conference, ISSCC 2012

作者： Yun, Won-Joo Nakano, Shinya Mizuhara, Wataru Kosuge, Atsutake Miura, Noriyuki Ishikuro, Hiroki Kuroda, Tadahiro Keio University Yokohama Japan

ISBN: (纸本)9781467303736

As computing power and speed increases, the demand for higher memory bandwidth increases as well. Recently, the memory interface has been improved up to 20Gb/s/link [1]. Considering PCB routing area, a multi-drop bus architecture is still preferable for large memory capacity to the point-to-point connection. However, the multi-drop approach suffers from performance degradations due to reflections at each stub. To mitigate this problem, reference [2] proposes an impedance-matched bidirectional multi-drop DQ bus architecture that is difficult to realize due to smaller series resistor if more than 4 modules are used. To avoid multi-reflections from each stub, other approaches have used coupled transmission lines (CTL) [3, 4]. While a horizontal directional coupler buried in the PCB was used [3], coupled traces on the bent loop of flex fixed to a module were used for signal delivery in vertical direction [4]. In [3], a long coupler with long main bus line was used so that the signal integrity degrades at the far-end coupler. In [4], the coupling traces on the motherboard and the flex have zigzag geometries for better misalignment tolerance, which result in large area of routing due to the minimum required pitch between traces. In [5], the CTL needs to be placed close to a Tx/Rx chip, as there are no extended transmission lines for signal lead. Therefore, it cannot be used for memory modules. DRAM multi-drop bus interface technology mapping is described in Fig. 2.8.1. © 2012 ieee.

关键词： Drops

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Thermal Simulation and Analysis of Intelligent Power module (IPM) Package

Thermal Simulation and Analysis of Intelligent Power Module ...

引用

13th International conference on Electronic Packaging Technology and High Density Packaging (ICEPT-HDP)

作者： Liu, Peisheng Tong, Liangyu Huang, Jinxin Tao, Yujuan Shen, Haijun Nantong Univ Jiangsu Key Lab ASIC Design Nantong 220619 Peoples R China Nantong Fujitsu Microelect Co Ltd Nantong Peoples R China

ISBN: (纸本)9781467316811;9781467316828

The performance of intelligent power module (IPM) will severely degrade with high junction temperature. Thus, it's important to get the thermal characterization of IPM package. In this paper, a method integrating electrical test method (ETM) and finite elements analysis (FEA) is put forward to analyze the thermal performance of a Transfer Molding IPM package. Electrical test method was used for thermal resistance test of the package under single freewheel diode heating in the one sixth module. The test results were then used for the calibration of finite elements model and boundary conditions. After validating the effectiveness of the finite element model and boundary conditions, thermal performance of the IPM package under multi-chip heating is obtained through numerical simulation. The method has certain practical meaning in the fast evaluation of power electronics' thermal performance.

关键词： calibration finite element analysis multichip modules thermal resistance

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Design and implementation of AMBE based voice codec module over custom FPGA platform

Design and implementation of AMBE based voice codec module o...

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2012 International conference on Computing, Communication and Applications, ICCCA 2012

作者： Mahawar, Kapil Kumar, Vishal Gupta, H.O. Department of Electrical Engineering Indian Institute of Technology Roorkee Roorkee-247 667 India

ISBN: (纸本)9781467302722

This paper presents the design and implementation of a Voice Codec module (VCM) over a Field Programmable Gate Array (FPGA) platform for low bit rate voice communication using Vocoder AMBE (Advanced multi Band Excitation)-2000 and Codec AD-73311. Low bit rate voice communication has become essential to many applications like digital radio, satellite communication, underwater acoustic communication etc. where bandwidth is at a premium and voice intelligibility is imperative. The hardware circuit of VCM is designed using FPGA instead of following the traditional DSPs/Microcontrollers approach so as to fulfill the objective of designing all the major subsystems of voice/data communication baseband unit inside a single FPGA chip. The Codec AD73311 used is a high performance A/D & D/A chip with programmable input and output gain control, and AMBE-2000 is the vocoder which is based on the AMBE compression algorithm. Using this VCM, the call voice is clear and legible at the rate of 2.02.4 Kbps which is very low compression bit rate. © 2012 ieee.

关键词： Field programmable gate arrays (FPGA)

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CLICHE network on chip: A novel multichannel acquisition module for a high throughput architecture

CLICHE network on chip: A novel multichannel acquisition mod...

引用

ieee Long Island Systems, Applications and Technology conference (LISAT)

作者： Mohammed Abdallah M. Abdelghany SUNYIT USA GUC

High throughput and low latency are the desirable characteristics of a multi processing system. CLICHE (chip-Level Integration of Communicating Heterogeneous Elements) is the simplest form of Network-on-chip architecture in terms of the layout and the local interconnections between resources and switches. The throughput varies with the number of virtual channels. When the number of virtual channels is increased, the throughput is increased. On the other hand, the average message latency increases with the number of virtual channels. To keep the latency low while preserving the throughput, the number of virtual channels is constrained to certain number. A novel multichannel signal acquisition module is proposed to integrate IP blocks. The proposed module achieves the optimal solution for large number of virtual channels. It reduces the memory requirement and power consumption as well. A Field Programmable Gate Arrays-based prototype is developed to verify the proposed module. Different case studies are studied in this research. As a result, the proposed module can schedule given tasks that are not schedulable via round-robin technique. Even in scenarios that both round-robin and proposed module can successfully schedule the given task, proposed module reduces the amount of data being acquired by 59%, which in turn decreases memory requirements and power consumption as well.

关键词： Frequency division multiplexing Mathematical model Power demand Equations Throughput Schedules

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multi-chip SiC DMOSFET half-bridge power module for high temperature operation

Multi-chip SiC DMOSFET half-bridge power module for high tem...

引用

Annual ieee conference on Applied Power Electronics conference and Exposition (APEC)

作者： Tsuyoshi Funaki Masashi Sasagawa Takashi Nakamura Division Electrical Electronic and Information Engineering Osaka University Osaka Japan Research and Development Headquarters ROHM Company Limited Kyoto Japan

The authors developed 80A, 1200V half bridge SiC power module for high temperature operation with connecting multiple small current rating SiC MOSFETs in parallel on a ceramic substrate. This paper characterizes and evaluates the static characteristics and switching operation capability of the developed power module from room temperature (25C) to high temperature condition (200C). First, the static current-voltage characteristics for wide temperature range are tested, and then terminal capacitance-voltage characteristics are evaluated. The switching behavior of the SiC power module is experimented and the temperature dependencies are evaluated. The results clarified the high temperature operation capability of the developed SiC power module without degrading fast switching capability.

关键词： Temperature MOSFET circuits Silicon carbide multichip modules Temperature measurement Logic gates Threshold voltage

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High-bandwidth data transmission of new transceiver module through optical interconnection

High-bandwidth data transmission of new transceiver module t...

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ieee International conference on 3D System Integration, 3DIC

作者： Yuka Ito Shinsuke Terada Shinya Arai Koji Choki Takafumi Fukushima Mitsumasa Koyangi New Industry Creation Hatchery Center (NICHe) University of Tohoku Aoba-ku Sendai Japan Circuitry with Optical Interconnection Business Development Department Sumitomo Bakelite Company Limited Utsunomiya Japan

This paper presents optical interconnection for module-to-module length for high-performance computing system. A new multi-chip transceiver module consisting of optical components, IC chips, flexible printed circuits (FPCs), and a sheet of optical polynorbornene (PNB) waveguides was fabricated by simple packaging processes. Waveguide sheet with micromirrors and the FPCs mounting of O/E devices were completed independently. After that, the waveguide sheet was aligned to optical devices on FPCs passively. Optical loss for waveguide including propagation and micromirror couplings was 3.30 dB. We successfully demonstrate high-bandwidth 100-Gbps (12.5 Gbps/ch × 8 channels) data transmission with the module, on which two 4-channel vertical-cavity surface emitting laser (VCSEL) arrays, one VCSEL driver (VD), two 4-channel PD arrays, and one transimpedance amplifier/limiting amplifier (TIA/LA) were mounted.

关键词： Optical waveguides Optical interconnections Optical device fabrication Optical losses Propagation losses Optical films Loss measurement

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A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line

A 7Gb/s/link non-contact memory module for multi-drop bus sy...

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ieee International conference on Solid-State Circuits (ISSCC)

作者： Won-Joo Yun Shinya Nakano Wataru Mizuhara Atsutake Kosuge Noriyuki Miura Hiroki Ishikuro Tadahiro Kuroda Keio University Yokohama Japan

关键词： Couplings Impedance Transmission line measurements Semiconductor device measurement Random access memory Directional couplers

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