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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是21-30 订阅

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Intelligent multi-Physics Design of 3-D Leadframe-based SiC Power module with Die Stacking for Transportation Electrification 73

Intelligent Multi-Physics Design of 3-D Leadframe-based SiC ...

引用

ieee 73rd Electronic Components and Technology conference (ECTC)

作者： Torres-Surillo, Emanuel Molina-Mangual, Christian Smet, Vanessa Georgia Inst Technol Sch Mech Engn Atlanta GA 30332 USA

ISBN: (纸本)9798350334982

The increasing demand for more efficient, compact and reliable power conversion in modern electric vehicles has led to the fast adoption of silicon carbide (SiC) inverters. While SiC devices bring dramatic gains in power density and system efficiency compared to their silicon counterparts, the technology is still underperforming due to aggravated chip-package interactions. On the electrical side, greater switching speeds result in increased dv/dts and di/dts, which, when coupled with the package parasitics result in increased overcurrent and voltage spikes and oscillation, aggravated noise and risks of electrical discharge machining failures. To address this challenge, a new leadframe-based package architecture with die stacking is proposed in this paper. While it provides output capacitance decoupling as well as a low-inductive current flow in the power module, die stacking may lead to thermal densification and subsequent reliability concerns that need to be considered in the design phase. To mitigate these multi-physics trade-offs, a novel machine-learning-based algorithm is used to optimize the package layout for best electrical, thermal and reliability performances and power density.

关键词： Silicon-carbide traction inverter electric vehicles 3D package architectures die stacking machine-learning optimization

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Achieving Spaceworthiness for Large-Size LTCC Packaging of Microwave MCM

Achieving Spaceworthiness for Large-Size LTCC Packaging of M...

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2023 ieee Microwaves, Antennas, and Propagation conference, MAPCON 2023

作者： Prajapati, Ishwarlal Hegde, Ravindra K. Pandya, Shilpa Lal, Ajay Kumar Ahmedabad India

ISBN: (纸本)9798350328264

This paper describes the various methodologies for realization of microwave subsystems through packaging of multiple bare MMICs. The use of LTCC substrate for packaging of hermetic multi-chip modules (MCM) has given significant benefits in terms of miniaturization and mass reduction. However, it poses several challenges for assembly and hermetic sealing of these large-size (>35 mm in both dimensions) LTCC modules. Various techniques for assembly and hermetic sealing were attempted and their outcomes are summarized. © 2023 ieee.

关键词： Epoxy sealing hermetic sealing Laser sealing LTCC multi-chip module

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High Power Thermal Test Vehicle with 2-Phase Cooling for AI Datacenters, 5G RAN, and EDGE Compute Nodes 74

High Power Thermal Test Vehicle with 2-Phase Cooling for AI ...

引用

ieee 74th Electronic Components and Technology conference (ECTC)

作者： Liu, Yang Basavanhally, Nagesh Earnshaw, Mark Salamon, Todd Papazian, Rick Hu, Ting-Chen Cappuzzo, Mark Kopf, Rose Apigo, David Farah, Bob Faisal, Syed Roy, Rishav Nokia Bell Labs Murray Hill NJ 07974 USA

ISBN: (纸本)9798350375985;9798350375992

In this paper, we introduce the design and fabrication of a high-power thermal test vehicle (TTV) equipped with a two-phase cooling system, targeting improved thermal management in multi-chip modules (MCMs) for AI datacenters, 5G RAN, and EDGE compute nodes. With the rise in device integration and component power densities, conventional cooling methods fall short, prompting the need for innovative approaches to achieve efficient heat dissipation. The TTV utilizes advanced heterogeneous integration techniques on a low-temperature cofired ceramic (LTCC) substrate, designed to reliably dissipate over 1000 W of heat. This provides a robust platform for testing advanced two-phase cooling strategies to effectively remove heat from densely packed silicon dies, thus addressing the thermal challenges inherent in modern electronics. We elaborate on the fabrication of two variations of the TTV: the first comprising six X1 MCM modules, each measuring 25 mm x 38 mm, and the second a single X6 module measuring 76 mm x 76 mm, showcasing the robustness of the process. These TTVs are engineered to manage power dissipation of up to 1008 W, with logic chips experiencing background power densities of approximately 34 W/cm<^>2 and hotspots peaking at 400W/cm<^>2, while HBM stack chips exhibit a heat flux of 16 W/cm<^>2. The logic chips, measuring 20 mm x 20 mm, and the HBM stacks, measuring 10 mm x 10 mm, closely replicate the specifications of cutting-edge AI hardware. The importance of this work lies in its capacity to offer a scalable and dependable testing platform for advanced thermal management strategies in high-performance computing. By leveraging two-phase cooling, it paves the way toward more reliable and efficient computing infrastructures, effectively addressing the challenges posed by high power and heat flux in contemporary electronic devices.

关键词： MCM multi-chip module two-phase cooling OHP Thermal Test Vehicle TTV

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Common Source Inductance Compensation Technique for Dynamic Current Balancing in SiC MOSFETs Parallel Operations 38

Common Source Inductance Compensation Technique for Dynamic ...

引用

ieee Applied Power Electronics conference and Exposition (APEC)

作者： Zhang, Boyi Wang, Ruxi Barbosa, Peter Tsai, Yu-Hsuan Wang, Wen-Sheng Lai, Wen-Shang Delta Elect Amer Ltd 5101 Davis Dr Res Triangle Pk NC 27709 USA Delta Elect Inc 16 Tungyuan Rd Taoyuan 320023 Taiwan

ISBN: (纸本)9781665475396

In high-current applications such as traction inverters, SiC MOSFETs are paralleled to increase the current capability. One major issue in paralleling SiC MOSFETs is the dynamic current unbalance. The unbalanced dynamic current could lead to severe device and system failures. It was well known that one of the root causes of dynamic current unbalance is parasitic parameter unbalance due to asymmetrical layout. In this paper, the impact of different parasitic parameters in circuit layout on current sharing is identified. Based on the analysis, a common source inductance (CSI) compensation technique is proposed for SiC MOSFETs in parallel operations to balance the dynamic current during the switching transient. With the proposed technique, the dynamic current among paralleled switches is evenly distributed even when the layout is not symmetrical. The improved current sharing is achieved by designing the common source inductance of each paralleled device inversely proportional to the power loop inductance. Because of the balanced dynamic current, the reliability of the circuit with the proposed layout can be significantly improved. The proposed technique is an easy-to-implement design that requires no additional components. Two types of prototypes are built to verify the proposed technique: A half-bridge configuration with SiC discrete devices in parallel and a multi-chip power module with SiC dies in parallel. The proposed technique is proven effective in both cases.

关键词： Device paralleling dynamic current balance multi-chip power module traction inverters WBG devices

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A multi-module silicon-on-insulator chip assembly containing quantum dots and cryogenic radio-frequency readout electronics 31

A multi-module silicon-on-insulator chip assembly containing...

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31st conference on Electronics Circuits and Systems

作者： Ibberson, David J. Kirkman, James Morton, John J. L. Gonzalez-Zalba, M. Fernando Gomez-Saiz, Alberto Quatum Motion 9 Sterling Way London N7 9HJ England UCL London Ctr Nanotechnol London WC1H 0AH England

ISBN: (纸本)9798350377217;9798350377200

Quantum processing units will be modules of larger information processing systems containing also digital and analog electronics modules. Silicon-based quantum computing offers the enticing opportunity to manufacture all the modules using the same technology platform. Here, we present a cryogenic multi-module assembly for multiplexed readout of silicon quantum devices where all modules have been fabricated using the same fully-depleted silicon-on-insulator (FDSOI) CMOS process. The assembly is constituted by three chiplets: (i) a low-noise amplifier (LNA), (ii) a single-pole eight-throw switch (SP8T), and (iii) a silicon quantum dot (QD) array. We integrate the chiplets into modules and show respectively, (i) a peak gain over 35 dB with a 3-dB bandwidth from 709 MHz to 827 MHz and an average noise temperature of 6.2 K (minimum 4.2 K), (ii) an insertion loss smaller than 1.1 dB and a noise temperature less than 1.1 K over the 0-2 GHz range, and (iii) single-electron box (SEB) charge sensors. Finally, we combine all modules into a single demonstration showing time-domain radio-frequency multiplexing of two SEBs paving the way to an all-silicon quantum computing system.

关键词： Cryo-CMOS cryogenic low-noise amplifiers (LNA) quantum computing single-electron devices single-pole eight-throw switch (SP8T) time-division multiplexing

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multi-Core module Configuration Model Considering 'Cloud-Edge-End-Core' Collaborative Efficiency Optimization 11

Multi-Core Module Configuration Model Considering 'Cloud-Edg...

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11th China International conference on Electricity Distribution, CICED 2024

作者： Lin, Guoying Zhou, Lai Liu, Hangchen Chen, Guan China Southern Power Grid Technology Co. Ltd. Guangdong Provincial Key Laboratory of New Technology for Smart Grid Guangzhou China Intelligent vehicle college Guangzhou Panyu Polytechnic Guangzhou China

ISBN: (纸本)9798350368345

In response to the challenges posed by the traditional vertical 'cloud-edge-end' structure of intelligent measurement systems, which impedes horizontal information exchange and hampers collaboration efficiency, a novel multi-core module configuration model that optimizes 'cloud-edge-end-core' collaborative efficiency is proposed in this paper. Firstly, a 'cloud-edge-device-core' collaborative technology framework for intelligent measurement based on InOS operating system is proposed to enhance data interaction flexibility through multi-core modules and peer-to-peer collaboration. Then, an optimization model is constructed with the objective of minimizing the comprehensive cost including chip configuration and data transmission. The model is designed to optimize cooperative efficiency across the 'cloud-edge-end-chip', with decision variables including the core board of intelligent measurement terminals, chips for smart meter management units, and application deployment locations. Finally, a case study on low-voltage topology identification demonstrates the optimized hardware configuration of multi-core modules, showcasing improved efficiency in 'cloud-edge-device-core' collaboration in intelligent measurement systems. © 2024 ieee.

关键词： Cloud platforms

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Design and Current Balancing Optimization of A 1700V/1000A multi-chip SiC Power module 11

Design and Current Balancing Optimization of A 1700V/1000A M...

引用

11th International conference on Power Electronics - ECCE Asia, ICPE 2023-ECCE Asia

作者： Yang, Junhui Gan, Yongmei Wang, Laili Zhao, Cheng Nie, Yan Ran, Li Xi'an Jiaotong University China University of Warwick United Kingdom

ISBN: (纸本)9788957083505

The rated current of a single SiC MOSFET is always less than 100A at a voltage rating higher than 1.2kV. Therefore, plenty of SiC MOSFET dies paralleled as multichip power modules to increase the current capacity. However, due to the asymmetric layout and the difference between chip parameters, there will be severe current imbalance in power modules, affecting the reliability. This paper presents a multi-chip 1700V/1000A SiC power module, consisting of 18 paralleled chips in each switch of the half-bridge topology. A serial of current balancing optimization method is proposed, including chip classification, the optimization of layout, power terminals and driver loop. Finally, the double pulse test (DPT) is conducted to verify the performance of the power module. © 2023 The Korean Institute of Power Electronics.

关键词： Silicon carbide

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Double-sided heat dissipation numerical modeling of an embedded half-bridge power module with multiple chips 25

Double-sided heat dissipation numerical modeling of an embed...

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25th International conference on Thermal, Mechanical and multi-Physics Simulation and Experiments in Microelectronics and Microsystems, EuroSimE 2024

作者： Li, Wenyu Chen, Wei Jiang, Jing Wang, Wenbo Fan, Xuejun Zhang, Guoqi Fan, Jiajie Fudan University Academy for Engineering and Technology China Shanghai Engineering Technology Research Center of SiC Power Device Fudan University Shanghai China Yongjiang Laboratory Ningbo China Lamar University Department of Mechanical Engineering Beaumont United States Delft University of Technology EEMCS Faculty Delft Netherlands Research Institute of Fudan University in Ningbo Ningbo China

ISBN: (纸本)9798350393637

Thermal management has always played a significant role in power module design. Double-sided heat dissipation is more efficient at transferring heat than the traditional package. Although there are several thermal modeling approaches to power modules, the application of the numerical models, which are computationally fast and accurate, has rarely been investigated for double-sided heat dissipation scenarios. This paper proposes a numerical heat conduction model of a double-sided heat dissipation power module with multiple chips embedded. The model was developed by solving Laplace's equation for the temperature distribution of steady state heat transfer using the separated variable method. The individual chip placement, two-chip distance and orientation, and four-chip placement were discussed through this modeling approach. The optimal layout was found. Then, a half-bridge topology module that consisted of two chips was investigated. To verify the accuracy of the numerical model, Finite Element Analysis (FEA) of the model was performed using the same boundary conditions. The experiments were applied on the power cycling tester to extract the junction temperature and case temperature. The numerical methods show good temperature prediction accuracy compared to both FEA and experiments. © 2024 ieee.

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A High Power Density Gate Driver Integrated SiC multichip Power module with Lower Parasitic Inductance 2

A High Power Density Gate Driver Integrated SiC Multichip Po...

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2nd ieee International Power Electronics and Application Symposium, PEAS 2023

作者： Zeng, Chenhang Chen, Cai Kang, Yong School of Electrical and Electronic Engineering Huazhong University of Science and Technology Wuhan China

ISBN: (纸本)9798350313765

In applications such as multi-electric aircraft, there is an increasing demand for power modules that offer improved volume efficiency and integration. Integration of gate drivers and power semiconductors can reduce the volume of the entire system and reduce the parasitic inductance of the drive circuit, which called intelligent power module(IPM). Consequently, research on high-power intelligent power modules (IPMs) is crucial. However, existing high-power IPMs still suffer from issues such as large physical dimensions and undesirable parasitic inductance. This paper presents a novel approach to address these challenges by introducing a 800V/200A multi-chip parallel intelligent SiC power module with an integrated driver chip. By optimizing the layout of the power loop and the drive loop, a power loop inductance of 7nH and a drive loop inductance of 11.5nH are achieved. Additionally, the warpage of large-size direct bond copper (DBC) substrates is reduced by 36% through the optimization of copper layer thickness, achieving high power density, low parasitic inductance, and enhanced reliability. © 2023 ieee.

关键词： gate driver integrated high power density power module SiC

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Design of an Electric Energy Metering module Combining Software and Hardware 3

Design of an Electric Energy Metering Module Combining Softw...

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3rd International conference on Electrical Engineering and Mechatronics Technology, ICEEMT 2023

作者： Gao, Yuan Wang, Yonggui Feng, Xiao Li, Yunpeng Academy of Information and Communication Research State Grid Information & Telecommunication Group Co. Ltd Beijing China Smart Iot Division State Grid Information & Telecommunication Group Co. Ltd Beijing China

ISBN: (纸本)9798350303698

In order to meet the requirements of the construction of new power system for the metering accuracy, operation reliability and domestic autonomous control of substation gateway meter, this paper proposes a high-precision settlement metering module based on domestic components. The module adopts the architecture of multi-channel high-precision AD chip+FPGA+MCU chip to design, combined with high-precision measurement algorithm, it can realize the power quality analysis function on the basis of high-precision measurement. © 2023 ieee.

关键词： Field programmable gate arrays (FPGA)

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