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International conference on Field-Programmable Technology

作者： Miyamoto, Naoto Ohmi, Tadahiro Tohoku Univ New Ind Creat Hatchery Ctr Aoba Ku Sendai Miyagi 9808579 Japan

ISBN: (纸本)9781424427956

For large-scale circuit emulation with using a multi-context FPGA (MC-FPGA), a circuit is divided into multiple sub-circuits. each sub-circuit is assigned to a context., and the MC-FPGA sequentially executes all the contexts one by one. So, the total execution delay is the sum of the delays of the contexts. It is, therefore, said that the total execution delay of the MC-FPGA increases proportional to the number of contexts used However, in this paper, we show that the total execution delay remains constant if a shift-register-type temporal communication module (SRTCM) is used instead of D-FlipFlop (D-FF) to implement sequential circuits. The SR-TCM is used not only for signal communication of sequential circuit like D-FF, but also for signal communication from preceding context to succeeding contexts. In order to quantify the delay, a MC-FPGA named Flexible Processor (FP), which contains the SR-TCM, have been designed and fabricated in 90nm CMOS process technology. From the measurement results, the total execution delay of the FP was kept constant regardless of the number of contexts used.

关键词： Shift registers

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Development of 3D silicon module with TSV for system in packaging

Development of 3D silicon module with TSV for system in pack...

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2008 58th Electronic Components and Technology conference, ECTC

作者： Khan, Navas Rao, Vempati Srinivasa Lim, Samule We, Ho Soon Lee, Vincent Wu, Zhang Xiao Rui, Yang Ebin, Liao Ranganathan Chai, T.C. Kripesh, V. Lau, John Singapore Science Park 2 11 Science Park Road Singapore 117685 Singapore

ISBN: (纸本)9781424422302

Portable electronic products demand multifunctional module comprising digital, RF and memory functions. Through-silicon via technology provides a means of implementing complex, multi-functional integration with a higher packing density for a System in Package. A 3D silicon module with through silicon via has been developed in this work. Thermo-mechanical analysis has been performed and through silicon via interconnect design is optimized. multiple chips representing different functional circuits are assembled using wirebond and flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burner copper via is exposed by special backgrinding process. A two-stack silicon module is developed and characterized in this work. Power distribution design for the silicon carrier suitable for 5GHz digital application is studied and characterized. The module reliability has been evaluated under temperature cycling (-40/125C) and drop test. Samples with over-mold and underfill passed the JEDEC drop test of 1500G & 0.5ms pulse duration. Thermal cycle test results showed no solder joint failure. ©2008 ieee.

关键词： Three dimensional integrated circuits

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Balanced SiGe PA module for multi-Band and multi-Mode Cellular-Phone Applications

Balanced SiGe PA Module for Multi-Band and Multi-Mode Cellul...

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ieee International conference on Solid-State Circuits (ISSCC)

作者： Antonino Scuderi Carmelo Santagati Michele Vaiana Francesco Pidala Mario Paparo STMicroelectronics Catania Italy

In this paper, the integration of a MM (GSM/EDGE/WCDMA) MB (850/900MHz, 1800/1900/2100MHz) 50 Omega-matched isolator-less flip-chip PAs, capable of envelope and power tracking operation, is discussed. The PAs are integrated in a 0.25 mum SiGe technology and are soldered on a 4-layer substrate. The system is hosted in a 6 x 8 mm 2 plastic module.

关键词： Silicon germanium Germanium silicon alloys GSM Inductors multiaccess communication Radio frequency Directional couplers Capacitors Filters Isolators

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120 Gb/s-level VCSEL array optical subassembly using passive alignment technique

120 Gb/s-level VCSEL array optical subassembly using passive...

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2008 58th Electronic Components and Technology conference, ECTC

作者： Hwang, Sung Hwan Lim, Jung Woon Rho, Byung Sup Integrated Optical Module Laboratory Korea Photonics Technology Institute Wolchul-dong 971-35 Buk-gu Gwangju 500-460 Korea Republic of

ISBN: (纸本)9781424422302

Our suggested VCSEL array optical subassembly (OSA) for 120 Gb/s-level parallel optical interconnect modules was composed of a 12 channel VCSEL array chip, a SiOB, two silicon spacers, and a molded microlens with accurate guide pin holes. For high speed operation above 10 Gb/s per a channel, we carefully designed transmission lines on the SiOB. The results of the transmission lines were measured as large bandwidth more than 26 GHz and low channel crosstalk less than -30 dB. And, to achieve high coupling efficiency, the planar-convex microlens was adopted. The average coupling efficiency coupled to 62.5 μm multi-mode fiber (MMF) ribbon was approximately 85%, the value of which means nothing but material loss itself. In this paper, the fabrication process of the VCSEL OSA is emphasized on low cost packaging. In particular, a suggested passive alignment technique is described in detail to align both the VCSEL and the microlens array. An accurate assembly in this work was carried out through vision alignment using 2-sight camera of a precise pick-and-place machine, Suss MicroTec TRIAD 05 flip-chip bonder. To evaluate the DC and AC characteristics of the completely fabricated VCSEL array OSA, we measured optical output powers (L-I-V curve) and 4.25 Gb/s, 6 Gb/s, 10.31 Gb/s eye-diagrams on condition of setting-up with MT ferrule terminated 12 channel 62.5 um MMF and a G-S-G probe. We successfully demonstrated high speed and high efficient VCSEL array OSA with clear 10.31 Gb/s eye diagrams and low coupling loss. ©2008 ieee.

关键词： Electric lines

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Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT module

Full Electro-Thermal Model of a 6.5kV Field-Stop IGBT Module

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39th ieee Power Electronics Specialists conference (PESC 2008), vol.1

作者： Alberto Castellazzi Emmanuel Batista Mauro Ciappa Jean-Marc Dienot Michel Mermet-Guyennet W. Fichtner Swiss Federal Institute of Technology Zurich Switzerland ALSTOM-Transportation Power Electronics Associated Research Laboratory Semeac France

As the integration level of power electronics equipment increases, the coupling between multi-domain physical effects becomes more and more relevant for design optimization. At the same time, virtual analysis capability acquires a critical importance and is conditioned by the achievement of an adequate compromise between accuracy and computational effort. This paper proposes the compact model development of a 6.5kV field-stop IGBT module, for use in a circuit simulation environment. The model considers the realistic connection of IGBT and anti-parallel freewheeling diode pairs: the description of semiconductor physics is coupled with self-heating effects, both at device and module level;electro-magnetic phenomena associated with the package and layout are also taken into account. The modeling approach follows a mixed physical and behavioral description, resulting in an ideal compromise for realistic analysis of multi-chip structures. Finally, selected examples, derived from a railway traction application scenario, demonstrate the validity of the proposed solution, both for simulation of short transients and periodic operation, qualifying the model as a support tool of general validity, from system design development to reliability investigations.

关键词： Insulated gate bipolar Transistors Modeling multichip modules Simulation

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RadHard 16Mbit SRAM packaged in a cantilever die multi-chip module

RadHard 16Mbit SRAM packaged in a cantilever die multi-chip ...

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2007 ieee Aerospace conference

作者： Hafer, Craig Mabra, Jonathan Slocum, Duane Thorne, Sean Aeroflex Colorado Springs Colorado Springs CO 80907 USA

ISBN: (纸本)9781424405244

Aeroflex Colorado Springs has developed a 16Mbit multi-chip module (MCM) SRAM operating on a single 5V power supply. Using a cantilever die stacking approach, two die are stacked on the top side of the package and two die are stacked on the bottom side of the package for a minimum foot print configuration. Conventional aluminum wire bonding has been used to optimize the reliability of this packaging technique.(1,2).

关键词： Static random access storage

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High-speed experimental results for an adhesive-bonded superconducting multi-chip module

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ieee TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2007年第2期17卷 971-974页

作者： Kaplan, Steven B. Dotsenko, Vladimir Tolpygo, Diana Hypres Inc Elmsford NY 10523 USA

We report experimental results for chip-to-chip data communications on a superconducting multi-chip-module (MCM) using a novel fabrication technique. The MCM was produced using a non-conductive adhesive to bond a 5-mm x 5-mm test chip to a 1-cm x 1-cm carrier. To our knowledge, this is the first time this technique was used for MCM assembly at cryogenic temperatures. The module demonstrated superior mechanical stability and protection from its environment during thermal cycling. The MCM also retained its electrical properties after multiple thermal cycling from room temperature to 4 K. We designed test circuits including various digital test benches, as well as analog test structures for bump characteristics. The superconducting circuitry successfully passed single-flux quanta at rates exceeding 50 Gbps. We measured error rates lower than 5 x 10(-14) at 36 Gbps using 100-micrometerdiameter In-Sn solder bumps, and lower than 6 X 10(-14) at 57 Gbps using 30-micrometer-diameter solder bumps.

关键词： chip-to-chip communications cryogenic package multi-chip module superconducting

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A VME module for a fast readout of the monolithics analog front-end chips

A VME module for a fast readout of the monolithics analog fr...

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ieee Nuclear Science Symposium/Medical Imaging conference

作者： Boiano, C. Guglielmetti, A. Romoli, M. Ist Nazl Fis Nucl Sez Milano Via Celoria 16 I-20133 Milan Italy Univ Milan Ist Nazl Fis Nucl Sez Milano I-20133 Milan Italy Ist Nazl Fis Nucl Sez Napoli Naples Italy

ISBN: (纸本)9781424409228

A single-slot VME card has been developed to digitalize the multiplexed analogue signals coming out from the analog front-end chips (VA32HDR14.2) used in the EXOTIC experiment. The module has 8 differential channels each one sample by 50 MHz 12-bit ADCs. Other features of the ADC card are the use of a sliding-scale technique to improve the differential linearity, the pedestal individually subtracted for each chip channel, a zero suppression with individual threshold, a multi event storage capability (up to 256), a programmable number of chips connected in chain, 8 trigger levels to manage different operations and a Test-Mode functionality to manage and control the VA32HDR14.2 chip.

关键词： Medical imaging

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Single flux quantum circuit and packaging technology for sub-Kelvin temperature operation

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ieee TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY 2007年第2期17卷 967-970页

作者： Yorozu, Shinichi Miyazaki, Toshiyuki Semenov, Vasili Hidaka, Mutsuo Tsai, Jaw-Shen NEC Corp Ltd Fundamental & Environm Res Labs Tsukuba Ibaraki 3058501 Japan Japan Sci & Technol Agcy NEC Tsukuba Lab Tsukuba Ibaraki 3058501 Japan SUNY Stony Brook Dept Phys & Astron Stony Brook NY 11974 USA Int Superconduct Technol Ctr Tsukuba Ibaraki 3058501 Japan

Superconducting single flux quantum (SFQ) technology is well known for digital logic operations below 4.2 K, which are compatible with the Josephson junction qubit. Operation speed and signal sensitivity of circuits in SFQ are also sufficient to control qubits. Therefore, the SFQ circuit is a candidate technology for multiple qubit control. However, the self-heating effect of the SFQ circuit is a potential barrier to development of an SFQ-supported multiple qubit system because the qubit operating temperature is lower than the conventional 4.2 K. The multi-chip approach is a possible solution because the qubit chip can be thermally isolated from the SFQ circuitry. We report on recent progress in SFQ circuit and packaging technology for operation at sub-Kelvin temperatures. As for multi-chip module technology, a test sample of the multi-chip module shows good reliability of electrical connections between chips, and each solder bump has a bandwidth wide enough for signal transmission. We have designed lower power SFQ circuits for sub-Kelvin temperatures. The critical currents of Josephson junctions were scaled down, inductances were scaled up, and bias voltage was reduced to make power consumption lower. Based on our fabrication technology, critical current densities were optimized by considering trade-off relations between fabrication availability and operation speed. We successfully confirmed its correct operations at around 0.35 K. The combination of the multi-chip module and optimized SFQ circuits is very effective way of controlling qubit.

关键词： multi-chip module qubit RSFQ single flux quantum

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High-speed experimental results for an adhesive-bonded superconducting multi-chip module

High-speed experimental results for an adhesive-bonded super...

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Applied Superconductivity conference 2006

作者： Kaplan, Steven B. Dotsenko, Vladimir Tolpygo, Diana Hypres Inc Elmsford NY 10523 USA

关键词： chip-to-chip communications cryogenic package multi-chip module superconducting

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