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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

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On-orbit performance demonstration of terrestrial processor for orbital maintenance system on the Micro-LabSat

On-orbit performance demonstration of terrestrial processor ...

引用

ieee Aerospace conference

作者： Kimura, S Yamamoto, H Nagai, Y Hashimoto, H Takahashi, N Yoshihara, K Commun Res Labs Koganei Tokyo 1848795 Japan

ISBN: (纸本)0780381556

We describe the experimental system and some preliminary experimental results for the Micro-OLIVe mission launched in 2002. An important first step in developing an orbital maintenance system (OMS) is to autonomously recognize and rendezvous with a target satellite. The Communications Research Laboratory developed a microprocessor multi-chip module to control the OMS, including a robotic system and image processing system, and installed them on Micro-LabSat for a mission called Micro-OLIVe. The microprocessor and inspection camera using commercial-off-the-shelf (COTS) C-MOS imaging units exhibited adequate performance, showing the feasibility of using low-cost COTS.

关键词： aerospace instrumentation artificial satellites microprocessor chips multichip modules robots cameras image processing CMOS image sensors on-orbit performance demonstration terrestrial processor orbital maintenance system Micro-LabSat Micro-OLIVe mission autonomous recognition target satellite Communications Research Laboratory microprocessor multichip module OMS control robotic system image processing system inspection camera commercial-off-the-shelf units CMOS imaging units COTS equipment

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Integrated antenna module for broadband wireless applications

Integrated antenna module for broadband wireless application...

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6th Electronics Packaging Technology conference, EPTC 2004

作者： Lu, Albert Chee W. Chua, Kai M. Wai, Lai L. Wong, Stephen C. K. Wang, Jun J. Zhang, Y.P. Singapore Institute of Manufacturing Technology 71 Nanyang Drive Singapore 638075 Singapore School of EEE Nanyang Technological University Nanyang Avenue Singapore 63979 Singapore

ISBN: (纸本)0780388216

This paper describes a module based system integration using LTCC technology to realize a compact integrated antenna module. This approach enables the adoption of "best-of-breed" CMOS, SiGe and GaAs technologies for RF transceiver, power amplifier and antenna switch components. Key advantages of this module integration approach include integration of embedded passives, BGA or SMT assembly compatibility, co-design of RF components, wire-bond or flip-chip silicon interconnection and compact footprint. The integrated antenna module targeted for WLAN applications was realized using multi-layer LTCC fabrication technology. The module size is 17 × 17 × 2 mm 3, and can be seamlessly integrated with any planar antenna configuration. In addition to providing RF integration and improved system performance, this platform also enables improved thermal performance required for high power wireless applications whilst achieving a compact footprint for "plug and play" applications in portable mobile communication products. © 2004 ieee.

关键词： Broadband networks

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Polymer embedded module for SiP application

Polymer embedded module for SiP application

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6th Electronics Packaging Technology conference, EPTC 2004

作者： Yoon, Seung Wook Andy, Lee Keng Jin Ganesh, V.P. Kripesh, Vaidyanathan Singapore 117685 Singapore

ISBN: (纸本)0780388216

Systems in Package (SiP) allow a greater density of silicon devices (IC) to be mounted directly onto a substrate within a single component package. Further miniaturization in microelectronics system requires 3-D integration of active, passive or module components. In order to maintain signal integrity, approaches featuring much shorter, impedance-matched, and less-interconnect-level between chips and passive components are desired, leading to the functional integration. In order to realise miniaturized functional modules, embedding actives and passives is potential baseline. Wafer level integration enables low cost and mass manufacturability of micro modules. In this work, embedding a silicon chip into a wafer level cavity layer was attempted and presented. The polymer module process is investigated using a thick polymer photo-resist to create a multi-layered 3D structure with microchip integration. SU-8 was used as the polymer thick layer to give the carrier structure for the embedding of silicon chip or device. SU-8 with its high aspect ratio capabilities and good photosensitivity, enabled to create a good base structure for embedding silicon chip. Experiments were carried out in the following stages to determine the feasibility of the process. Silicon substrate was coated with a thick SU-8 layer of 100um and developed to form the base substrate. On this base silicon test chip were die-attached and a passivation dielectric layer was deposited and developed over the passivation layer UBM and metal layer were deposited for interconnection and bumping The prototype samples with 3.5mm×3.5mm dies having 70um thickness were successfully thinned. The embedded module was then coated with a dielectric and interconnection processes were followed. The test vehicles showed electrical connectivity and the embedded module technology can be further used in the field of advanced microelectronics or microsystem packaging. The solution to 3D wafer level integration whilst having sm

关键词： Electronics packaging

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Combined thermal and thermomechanical modeling for a multi-chip QFN package with metal-core printed circuit board

Combined thermal and thermomechanical modeling for a multi-c...

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9th Intersociety conference on Thermal and Thermomechanical Phenomena in Electronic Systems

作者： Fan, XJ Philips Res USA Briarcliff Manor NY 10510 USA

ISBN: (纸本)0780383575

multi-chip quad flat no-lead (QFN) (also known as microleadframe (MLF)) package with split leadframe design allows the control FET, synchronous FET, driver and PWM control chips into a single package. When power density increases, thermally sensitive substrates with metal core, such as insulated metal substrate (IMS) or direct-bond copper (DBC) substrate, are required to meet the thermal requirement. However, it has not been clear bow a metal-core substrate affects solder joint reliability. This paper combines the CFD-based thermal modeling with visco-plastic finite element modeling to predict both thermal behavior and mechanical performance under temperature cycling. First, the detailed thermal model is established and validated against the experiment. A two-resistor compact model, on the basis of the validated detailed model, is applied to system-level thermal analysis. It is found that the use of IMS board can reduce the board area by half compared to FR-4 board. Second, a full 3-D finite element nonlinear model is built with the temperature distributions from the thermal modeling in an accelerated cycling condition. We found that the fatigue life of solder joint decreases by a factor of 4 when IMS board is used. A comprehensive model study is performed to investigate the full 3-D model versus a 3-D slice model, as well as the impact of the linearization of center solder pad. A trade-off design in thermal performance, chip layout, leadframe design, and the selection of board material is discussed to meet both thermal and mechanical specifications.

关键词： MOSFET quad flat no-lead (QFN) multi-chip module (MCM) thermal compact model solder joint reliability fatigue visco-plastic metal-core board finite-element

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MAP (Mobile AGP processor) - A high performance integrated graphics module

MAP (Mobile AGP processor) - A high performance integrated g...

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2004 Proceedings - 54th Electronic Components and Technology conference

作者： Pendse, Raj Marcus, Bill Yee, M.H. Yun, J.S. Zahn, Bret Jafari, Bob Dewey, Tom Lau, Tim Michael, M. Singh, Inderjit Starr, Orion ChipPAC Inc. 47400 Kato Rd. Fremont CA 94538 NVidia Corp. 2701 San Tomas Expressway Santa Clara CA 95050

A flip chip multi chip module has been developed for NVidia's MAP (Mobile AGP Processor) family of integrated graphics subsystem products. The graphics subsystem consists of a high-end graphics processing unit (GPU) chip, four high-speed DDR memory components, forty passive components (consisting of resistors, capacitors and jumpers) and a heat spreader, integrated on two sides of a single high-density substrate, within the form factor of a JEDEC-standard 31 × 31 mm Ball Grid Array (EGA) package. The package includes several innovative and unique technological features such as: (a) A graphics processor chip with approximately 1000 solders bumps that is flip chip attached on the ball-side of the BGA package - this is facilitated by bumped wafer thinning technology to achieve a bumped die thickness of 240 um and a unique underfilling process for thin die (b) High speed DDR memory components in CSP packages that are mounted to the same substrate as the flip chip die but on the opposing side;the components are underfilled for high reliability (c) A 2-2-2 Build-up substrate that provides a high-speed interface between the memory components and the graphics chip located on opposing sides of the substrate;this also allows maximum utilization of the build-up layer density on both sides of the core (d) A dual flow path cooling solution consisting of a heat spreader on the topside and direct thermal contact between the GPU and motherboard on the bottom side (e) A unique assembly process that integrates flip chip technology, in-process electrical testing, and SMT processing in a streamlined flow to enable mass production of the package with yields above 99. 5 % in high volume. In this paper, we present the development of this package covering design, assembly process development, and package structure optimization performed to enable high component-level reliability and a successful launch into production. We will present data covering the understanding of failure modes that l

关键词： Microprocessor chips

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Building pixel detector modules in multi chip module deposited technology

Building pixel detector modules in multi chip module deposit...

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ieee Symposium on Nuclear Science (NSS/MIC)

作者： K.-H. Becks T. Flick C. Grah P. Gerlach P. Mattig Department of Physics University of Wuppertal Germany

The MCM-D technique has been used to build hybrid pixel detector modules and single chip assemblies with optimized sensor geometry. Results of test measurements in both a laboratory and a test beam environment are given.

关键词： Detectors Thin film sensors Bonding Flip chip Active matrix technology Sensor systems Geometry Testing Large Hadron Collider Thermal sensors

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Saw singulation characterization on high profile multi chip module packages with thick leadframe

Saw singulation characterization on high profile multi chip ...

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Electronics Packaging Technology conference (EPTC)

作者： N. Anuar A. Taib STATS ChipPAC Malaysia Sdn. Bhd. Kuala Lumpur Malaysia

Increasing demand for multi chip module (MCM) power devices in a quad flat nonleaded (QFN) package outline drives the development of the LFCSPs-P (lead frame chip scale package-saw-power). multi chip module offers host benefit including performance improvements such as shorter interconnect lengths between dies, lower power supply inductance and lower off-chip driver. Besides, it can reduce the manufacturing cost and increase the utility of programmable systems based on V. Biancomano (2002). Compared to the leaded package with similar body sizes and lead counts, QFN offers far superior thermal performance and provides excellent electrical characteristics as stated in D. Comley and P. Smith (2002). Package designers used nominal thickness of standard Cu-Alloy leadframe and standard package height meant for power packages with soft solder die attach and heavy Al wire bonding to enhance heat dissipation capability other than the heat sinks. Map type design is used to enhance productivity by maximizing the device density. Singulation is achieved by sawing through the molded leadframe channels with diamond type blades that separated the arrays rows and columns according to D. Comley and P. Smith (2002). However, the combination of ductile and brittle material in the same sawing process creates real challenges in term of sawing quality, blade life and throughput. Experiments were carried out and its results show that integration of the blade type, parameters, methodology and other external features give the maximum result for the said challenges.

关键词： Lead Sawing Blades chip scale packaging Heat sinks Power system interconnection Power supplies Inductance Manufacturing Costs

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Polymer embedded module for SiP application

Polymer embedded module for SiP application

引用

Electronics Packaging Technology conference (EPTC)

作者： Seung Wook Yoon L.K.J. Andy V.P. Ganesh V. Kripesh Mechanical Engineering Department Institute of Microelectronics (IME) National University of Singapore Singapore

Systems in package (SiP) allow a greater density of silicon devices (IC) to be mounted directly onto a substrate within a single component package. Further miniaturization in microelectronics system requires 3D integration of active, passive or module components. In order to maintain signal integrity, approaches featuring much shorter, impedance-matched, and less-interconnect-level between chips and passive components are desired, leading to the functional integration. In order to realise miniaturized functional modules, embedding actives and passives is potential baseline. Wafer level integration enables low cost and mass manufacturability of micro modules. In this work, embedding a silicon chip into a wafer level cavity layer was attempted and presented. The polymer module process is investigated using a thick polymer photoresist to create a multi-layered 3D structure with microchip integration. SU-8 was used as the polymer thick layer to give the carrier structure for the embedding of silicon chip or device. SU-8 with its high aspect ratio capabilities and good photosensitivity, enabled to create a good base structure for embedding silicon chip. Experiments were carried out in the following stages to determine the feasibility of the process. Silicon substrate was coated with a thick SU-8 layer of 100mum and developed to form the base substrate. On this base silicon test chip were die-attached and a passivation dielectric layer was deposited and developed over the passivation layer UBM and metal layer were deposited for interconnection and bumping. The prototype samples with 3.5mmtimes3.5mm dies having 70mum thickness were successfully thinned. The embedded module was then coated with a dielectric and interconnection processes were followed. The test vehicles showed electrical connectivity and the embedded module technology can be further used in the field of advanced microelectronics or microsystem packaging. The solution to 3D wafer level integration whilst havi

关键词： Polymers Dielectric substrates Integrated circuit packaging Microelectronics Testing Passivation Silicon devices Impedance Costs Manufacturing

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Integrated antenna module for broadband wireless applications

Integrated antenna module for broadband wireless application...

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Electronics Packaging Technology conference (EPTC)

作者： A.C.W. Lu K.M. Chua L.L. Wai S.C.K. Wong J.J. Wang Y.P. Zhang Singapore Inst. of Manuf. Technol. Singapore Singapore Institute of Manufacturing Technology Singapore Singapore Institute of Manufacturing Technology Singapore SG School of EEE Nanyang Technological University Singapore

This paper describes a module based system integration using LTCC technology to realize a compact integrated antenna module. This approach enables the adoption of "best-of-breed" CMOS, SiGe and GaAs technologies for RF transceiver, power amplifier and antenna switch components. Key advantages of this module integration approach include integration of embedded passives, BGA or SMT assembly compatibility, co-design of RF components, wire-bond or flip-chip silicon interconnection and compact footprint. The integrated antenna module targeted for WLAN applications was realized using multi-layer LTCC fabrication technology. The module size is 17 /spl times/ 17 /spl times/ 2 mm/sup 3/, and can be seamlessly integrated with any planar antenna configuration. In addition to providing RF integration and improved system performance, this platform also enables improved thermal performance required for high power wireless applications whilst achieving a compact footprint for "plug and play" applications in portable mobile communication products.

关键词： Broadband antennas Radio frequency CMOS technology Switches Silicon germanium Germanium silicon alloys Gallium arsenide Transceivers Broadband amplifiers Power amplifiers

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MAP (mobile AGP processor) - a high performance integrated graphics module

MAP (mobile AGP processor) - a high performance integrated g...

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Electronic Components and Technology conference (ECTC)

作者： R. Pendse B. Marcus M.H. Yee J.S. Yun B. Zahn B. Jafari T. Dewey T. Lau M. Michael I. Singh O. Starr ChipPAC Inc. Fremont Ca USA NVidia Corp. Santa Clara Ca USA NVidia Corp. Santa Clara Ca

A flip-chip multi-chip module has been developed for NVidia's mobile AGP processor (MAP) family of integrated graphics subsystem products. The graphics subsystem consists of a high-end graphics processing unit (GPU) chip, four high-speed DDR memory components, forty passive components (consisting of resistors, capacitors and jumpers) and a heat spreader, integrated on two sides of a single high-density substrate, within the form factor of a JEDEC-standard 31 /spl times/ 31 mm ball grid array (BGA) package. The package includes several innovative and unique technological features such as: (a) A graphics processor chip with approximately 1000 solders bumps that is flip chip attached on the ball-side of the BGA package. This is facilitated by bumped wafer thinning technology to achieve a bumped die thickness of 240 /spl mu/m and a unique underfilling process for a thin die. (b) High speed DDR memory components in CSP packages that are mounted to the same substrate as the flip chip die but on the opposing side; the components are underfilled for high reliability. (c) A 2-2-2 build-up substrate that provides a high-speed interface between the memory components and the graphics chip located on opposing sides of the substrate; this also allows maximum utilization of the build-up layer density on both sides of the core. (d) A dual flow path cooling solution consisting of a heat spreader on the topside and direct thermal contact between the GPU and motherboard on the bottom side. (e) A unique assembly process that integrates flip chip technology, in-process electrical testing, and SMT processing in a streamlined flow to enable mass production of the package with yields above 99.5 % in high volume. In this paper, we present the development of this package covering design, assembly process development, and package structure optimization performed to enable high component-level reliability and a successful launch into production. We will present data covering the understanding

关键词： Graphics Flip chip Assembly Resistors Capacitors Electronics packaging chip scale packaging Cooling Resistance heating Contacts

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