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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 540 条记录，以下是361-370 订阅

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System-on-a-package (SOP) substrate and module with digital, RF and optical integration

System-on-a-package (SOP) substrate and module with digital,...

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Electronic Components and Technology conference (ECTC)

作者： V. Sundaram R. Tummala G. White K. Lim Lixi Wan D. Guidotti Fuhan Liu S. Bhattacharya R.M. Pulugurtha I.R. Abothu R. Doraiswami R.V. Pucha J. Laskar M. Tentzeris G.K. Chang M. Swaminathan Packaging Research Center Georgia Institute of Technology USA Packaging Research Center Georgia Institute of Technology

The Packaging Research Center has been developing next generation system-on-a-package (SOP) technology with digital, RF, and optical system integration on a single package. SOP aims to utilize the best of on-chip SOC integration and package integration to achieve the highest system performance at the lowest cost. The micro-miniaturized multi-functional SOP package is highly integrated and fabricated on large area substrates similar to the wafer-to-IC concept. In addition to novel mixed signal design methodologies, SOP research at PRC is targeted at developing enabling technologies for package level integration including ultra-high density wiring, embedded passive components, embedded optical interconnects, wafer level packaging and fine pitch assembly. Several of these enabling technologies have been recently integrated into the first successful system level demonstration of SOP technology using the intelligent network communicator (INC) testbed. This paper reports on the latest INC and SOP testbed results at the PRC and provides an insight into the future SOP integration strategy for convergent microsystems. The focus of this paper is on integration of materials, processes and structures in a single package substrate for system-on-a-package (SOP) implementation.

关键词： Radio frequency Integrated optics Packaging Wafer scale integration Partial response channels System-on-a-chip System performance Costs Signal design Wiring

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Compact receiver module for X-band radar applications

Compact receiver module for X-band radar applications

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33rd European Microwave conference

作者： Billström, N Ericsson Microwave Syst AB S-43184 Molndal Sweden

ISBN: (纸本)1580538347

This paper presents, the design, realization and measured results of a highly integrated multi-chip-module (MCM) developed for X-band radar applications. The MCM is built up in a LTCC substrate. Embedded within the substrate is a bandpass stripline filter. The main functionality is realized by two multi-function MMIC. The MCM is an integral part of a future multi-channel AESA radar system.

关键词： Radar measurement

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multi-chip memory module with a flip-chip-on-chip structure and an optional center via hole for underfill dispensing

Multi-chip memory module with a flip-chip-on-chip structure ...

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53rd Electronic Components and Technology conference

作者： Lee, SWR Tsui, YK So, R Luo, L Hong Kong Univ Sci & Technol Dept Mech Engn Elect Packaging Lab Kowloon Hong Kong Peoples R China

ISBN: (纸本)0780379915

This paper presents an innovative package design for multi-chip memory modules. The developed package has a flip-chip-on-chip structure. Four memory chips are assembled on a silicon carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon carrier to form an area array with larger solder balls. An optional via hole is made through the silicon at the center of the carrier for underfill dispensing. The whole multi-chip memory module is assembled to the printed circuit board by the standard surface mount reflow process. In case that package encapsulation is required, the underfill material is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. After the board level assembly, non-destructive evaluations and cross-section inspections are performed. The experimental results show that good solder joints and void-free underfill can be achieved. Although the current study uses DRAM chips for demonstration, the developed silicon carrier is suitable for SRAM and FLASH memory chips as well. With this innovative package design, low profile and high density multi-chip memory modules can be easily implemented. Due to the unique package structure, it is believed that good board level reliability can be achieved. The reliability tests are under way.

关键词： multichip modules

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The design and fabrication techniques of multilayer substrate for MCM-C 5

The design and fabrication techniques of multilayer substrat...

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5th International conference on Electronic Packaging Technology (ICEPT2003)

作者： Huang, JS Zhao, P Zou, YM Fu, HL Zheng, HY Gao, ST Hebei Semicond Res Inst Package Dept Shijiazhuang 050051 Peoples R China

ISBN: (纸本)0780381688

With the rapid development of semiconductor industry the scale of IC becomes larger and larger, the speed of chip higher and higher, and the volume of package smaller and smaller To meet the challenge, multi-chip module (MCM) must be developed simultaneously, which makes a module with many single chips, reduces the cost of circuit, and improves the performance of circuit. MCM ceramic substrate is an important part of MCM. We have developed a series of multiplayer substrates for MCM-C This paper presents our design and fabrication techniques of MCM ceramic substrate, includes modeling, library, routing, simulation, part, co-firing, and plating technologies, and introduces the information of our MCM-C substrates.

关键词： electronic package multi-chip module (MCM) model Computer Aided Design (CAD) Computer Aided Manufacturing (CAM) design fabrication

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Three-dimensional packaging for multi-chip module with through-the-silicon via hole 5

Three-dimensional packaging for multi-chip module with throu...

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5th Electronics Packaging Technology conference (EPTC 2003)

作者： Tsui, YK Lee, SWR Wu, JS Kim, JK Yuen, MMF Hong Kong Univ Sci & Technol Dept Mech Engn Elect Packaging Lab Kowloon Hong Kong Peoples R China

ISBN: (纸本)0780382056

This paper presents an innovative package design for multi-chip modules. The developed package has a flip-chip-on-chip structure. Four memory chips (DRAM for demonstration) are assembled on a silicon chip carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. An optional through-the-silicon via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of underfill. Afterwards, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of those packages is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1,000 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, right under the pads of large solder balls. The ATC test of packages with underfill encapsulation is still ongoing (no observable failure recorded up to 1,200 cycles). With this innovative package design, low profile and high density multi-chip modules can be implemented. Due to the unique package structure and underfill encapsulation, it is believed that good board level reliability can be achieved.

关键词： Dynamic random access storage

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Highly reliable and low-cost multi-chip module composed of wafer process packages

Highly reliable and low-cost multi-chip module composed of w...

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53rd Electronic Components and Technology conference

作者： Naka, Y Tanaka, N Naito, T Hitachi Ltd Mech Engn Res Lab Tsuchiura Ibaraki 3000013 Japan

ISBN: (纸本)0780379915

A high-performance, low-cost, and highly reliable multi-chip module (MCM) was developed. It is composed of a MP U and a synchronous DRAM [i.e., wafer process packages (WPPs)] on a substrate. To. reduce the, cost of the MCM, a low-cost FR-4 base is used a substrate on which the WPPs are mounted. Since the mismatch between the thermal expansion coefficients (TEC) of the MPU and DRAM chips and the substrate increases, thermal deformation due to the mismatch may cause cracking of the chip or decrease the life of the solder joints between the MCM and a FR-4 base motherboard. To minimize the stress caused by thermal deformation in the MCM and, thus, to improve its reliability, the structure of the MCM was therefore optimized by finite element analysis (FEA). The FEA results show that thermal stresses in both the chips and the solder bumps are a function. of the ratio. of chip thickness (tc) and substrate thickness (ts), i.e., tc/ts, and these stresses decrease when tc/ts is decreased. Furthermore, thermal-cycling test results show, that. MCM reliability is assured when tc/ts is 0.5 or less. A MCM with tc/ts of 0.4, including a margin of safety, was developed. It was found that the life of this MCM is over 1000 cycles (no chip cracking and no solder joint failure) under thermal-cycling between -55degreesC and 125degreesC.

关键词： multichip modules

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Integrated packaging of a 1 kW switching module using planar interconnect on embedded power chips technology

Integrated packaging of a 1 kW switching module using planar...

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18th Annual ieee Applied Power Electronics conference and Exposition

作者： Liang, ZX Lee, FC van Wyk, JD Boroyevich, D Scott, E Chen, J Lu, B Pang, Y Virginia Polytech Inst & State Univ CPES Blacksburg VA 24061 USA

ISBN: (纸本)0780377680

A 1 kW MOSFET half-bridge switching subassembly with gate drivers has been designed and fabricated, in integrated three-dimensional (3-D) form factor, using a planar integration technology, through building up dielectric/metallization thin-film interconnection directly on co-planar bare power chips embedded in a ceramic carrier. The 3-D geometrical layout was optimized through simulating electrical and thermal performance, with Maxwell Q3D and I-DEAS, respectively. The advantages of this module have been experimentally demonstrated by the electrical and thermal performance in the testbeds and IPEM-based DC/DC converter.

关键词： power electronics integrated packaging power electronics assemblies (modules) multi-chip integration planar process

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RF module using MCM-L and BGA technology for 5GHz WLAN application

RF module using MCM-L and BGA technology for 5GHz WLAN appli...

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33rd European Microwave conference

作者： Hiura, S Ishida, M Kitahara, T Yamamoto, T Toshiba Co Ltd Corp Mfg Engn Ctr Yokohama Kanagawa 2350017 Japan

ISBN: (纸本)1580538347

This paper presents the design concept and experimental results about small size radio frequency (RF) module for 5GRz;wireless local area network (WLAN). Functions of the RF module include from base band input/output to antenna switch. The size is 20mm x 15mm x 3mm and that is minimum size in modules with same functions as far as the authors get to know. For the purpose of small size and low cost, generally known technologies are used. They are multi chip module on laminated-base dielectric substrate (MCM-L) technology, interconnection of each layer using build-up technology, flip chip technology and ball grid array (BGA) technology. Parts and ICs are on both sides of the RF module's substrate and are vertically connected in the substrate. In order to ensure electrical performance at 5GRz frequency band in the high-density package, transmission line characteristics in the substrate and BGA characteristic are simulated by 3 dimensional (3D) electromagnetic (EM) software. The fabricated RF module is evaluated using the test set up for 5GHz WLAN application and the result is shown.

关键词： Ball grid arrays

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Package embedded heat exchanger for stacked multi-chip module 12

Package embedded heat exchanger for stacked multi-chip modul...

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12th International conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS 03)

作者： Lee, H Jeong, Y Shin, J Kim, S Kim, M Kang, M Chun, K Seoul Natl Univ Sch Elect Engn & Comp Sci Seoul South Korea

ISBN: (纸本)0780377311

This paper described a polymer type micro heat exchanger for stacked multi-chip module (MCM). Usually, heat exchanger was fabricated by high thermal conductive substrate such as metal, silicon etc. Of course it showed efficient heat exchange ability. However, there was packaging problem when it was integrated in a package, because the heat exchanger became too huge to accommodate in present packaging technology. Therefore the packaging technology compatible to heat exchanger that could be fabricated using the present packaging technology was needed. We fabricated the PDMS heat exchanger that was 300 mum thin and had the same size to the chip. This speculation satisfied the general MCM packaging. And we could decrease thermal resistance from 50 to 8.3 degreesC/W with liquid cooling method.

关键词： Costs Electronic packaging thermal management Heat sinks Liquid cooling Polymers Silicon Space heating Space technology Thermal conductivity Thermal resistance

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Receptacle transceiver module using silica waveguide for bi-directional transmission over single fiber

Receptacle transceiver module using silica waveguide for bi-...

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53rd Electronic Components and Technology conference

作者： Kimura, N Shinozaki, K Kitamura, N Fukutomi, Y Minota, Y Tanaka, H Sato, A Ando, H NEC Corp Ltd Fiber Opt Devices Div Nakahara Ku Kawasaki Kanagawa 21186666 Japan

ISBN: (纸本)0780379915

We have newly developed a receptacle transceiver module for single fiber, bi-directional optical access network systems. Outline dimensions and pin assignment of the receptacle transceiver module are according to 2x5 small form factor (SFF) multi-source agreement (MSA) specification. A new compact-size optical module using silica waveguide (PLC: Planar Lightwave Circuit) has been developed. All the optical components, which are the LD, the PD, the WDM filter and the fiber terminal, are mounted on the PLC chip using passive alignment techniques and covered with resin for sealing. We have confirmed that the transceiver module shows clear eye pattern under 156Mb/s modulation and minimum receiver sensitivity of less than -34dBm under the fall duplex operation at 156Mb/s.

关键词： Optical devices

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