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检索条件"任意字段=IEEE Conference on Multi-Chip Module"

共 539 条记录，以下是31-40 订阅

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Integrated Design of a multi-Channel Cyclic Data Acquisition module Circuit 3

Integrated Design of a Multi-Channel Cyclic Data Acquisition...

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3rd International conference on Electrical Engineering and Mechatronics Technology, ICEEMT 2023

作者： Xiang, Qing Hu, Ying Shao, Yaoyu Ye, Xi Jianghan University School of Intelligent Manufacturing Wuhan China

ISBN: (纸本)9798350303698

In the embedded development process of industrial control and mechatronics equipment, extensive sensor data acquisition is indispensable. However, this also occupies many ports of the MCU, increasing both the cost and the difficulty of port expansion. To address the issue, this paper presents a low-cost and reliable cascaded multi-channel cyclic data acquisition circuit. The circuit combines the CD4017 digital logic chip with analog circuits to satisfy data acquisition requirements while being easy to expand and has advantages in terms of performance and cost. Additionally, this paper provides a dedicated integrated circuit chip design scheme based on this circuit, suitable for multi-channel fast scanning acquisition applications. © 2023 ieee.

关键词： Data acquisition

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Analysis of Influencing Factors of Parallel Current Sharing of High Power module 2

Analysis of Influencing Factors of Parallel Current Sharing ...

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2nd ieee-Industrial-Electronics-Society Annual On-Line conference (ONCON)

作者： Qi, Zhaoxuan Wang, Li He, Yongsheng Nanjing Univ Aeronaut & Astronaut Coll Automat Engn Nanjing Peoples R China

ISBN: (纸本)9798350357974

The multi-chip power module serves as the core component of high-power Solid State Power Controller (SSPC). However, discrepancies in the intrinsic parameters of parallel-connected chips and the layout structure of the module result in uneven current distribution among parallel chips, significantly compromising the reliability of SSPC. This paper focuses on a developed 270V/200A power module and establishes an equivalent circuit model considering the parasitic parameters of the module's actual structure. Firstly, simulations were conducted to observe the current sharing among parallel power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) under various operating modes. Secondly, a typical equivalent circuit model of a power module with three parallel branches was established. By altering the parasitic parameters of the MOSFET itself and the module's layout structure, an analysis was carried out to investigate the impact of the imbalance in internal parasitic parameters on the module's parallel current-sharing capability. Simulation results indicate that the steady-state current sharing capability of the power module is significantly influenced by stray resistances and MOSFET's on-state resistances. Transient current sharing capability, on the other hand, is greatly affected by MOSFET's threshold voltage, transconductance, gate drive resistance, and the parasitic inductance of the power circuit's source busbar. Parasitic inductances of the gate drive circuit and drain copper busbar have minimal impact on transient current balance.

关键词： SSPC Power module Parallel Current Sharing

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Superconducting Molybdenum multi-chip module Approach for Cryogenic and Quantum Applications 72

Superconducting Molybdenum Multi-Chip Module Approach for Cr...

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72nd ieee Electronic Components and Technology conference (ECTC)

作者： Shah, Archit Peek, Sherman E. Yelamanchili, Bhargav Gupta, Vaibhav Tuckerman, David B. Cantaloube, Chris Sellers, John A. Hamilton, Michael C. Auburn Univ Dept Elect Engn Auburn AL 36849 USA Tuckerman & Associates Inc Washington DC USA Microsoft Corp Redmond WA 98052 USA

ISBN: (纸本)9781665479431

We describe a superconducting multi-chip module (S-MCM) technology using Mo as a robust substrate on which to construct multi-layer superconducting redistribution layers for chip-to-chip signal transmission for densely-integrated cryogenic and quantum electronics. The mechanical robustness and ductile nature of Mo can allow for the integration of chips on a larger scale S-MCM substrate compared to currently available technologies. We demonstrate this integration technology by flip-chip bonding Si chips to Mo substrates using In bumps and epoxy underfill. Superconducting daisy-chain test structures were formed by Mo substrates with polyimide dielectric and superconducting Nb traces connected to Si chips with varying numbers of transitions and bump array densities. Resistance and superconducting transition temperatures of the various daisy-chain configurations were measured from room temperature to 4.2 K. To explore CTE-related challenges, assemblies using Si chips with dimensions up to 27 mm x 22 mm (In bump array size of 20 mm x 20 mm) were found to survive the multiple thermal cycles from room temperature to cryogenic temperatures.

关键词： S-MCM large-scale integration superconducting packaging flip-chip technology

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Package Power Delivery Architecture for High Performance Computing Systems With a 1 kW IVR Operated in CCM-DCM Boundary Mode Condition 74

Package Power Delivery Architecture for High Performance Com...

引用

ieee 74th Electronic Components and Technology conference (ECTC)

作者： Khorasani, Ramin Rahimzadeh Li, Xingchen Kim, Joon Woo Murali, Prahalad Sharma, Rohit Swaminathan, Madhavan Penn State Univ Sch Elect Engn & Comp Sci University Pk PA 16802 USA Indian Inst Technol Ropar Dept Elect Engn Rupnagar 140001 India

ISBN: (纸本)9798350375985;9798350375992

This paper investigates a package power delivery architecture for high-performance computing (HPC), incorporating a novel modular multi-phase integrated voltage regulator (IVR). The 1-kW 48-12/1 V architecture integrates an efficient interleaved buck-derived converter at the continuous-discontinuous boundary condition, facilitating parallel-connected networks of embedded inductors to deliver hundreds of amperes per phase. Due to the increased duty cycle and zero switching losses provided for the high side switch, the converter's frequency can be further increased up to 50 MHz with 8 parallel phases and 100 MHz with 16 parallel phases for a 48/1 V, 1 kW architecture. A conceptual 3-D stacked architecture using stacked glass substrates with flip chip GaN switches and embedded inductors, and capacitors is presented, offering a high-density single-stage 48-12/1 V IVR for the next generation of data center applications.

关键词： 3-d stack heterogeneous integration integrated voltage regulator module (IVR) soft switching zero switching losses vertical power delivery embedded inductor

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A Portable Ultra-low-cost multi-Gas Sensing System-on-module for Wireless Air Quality Monitoring Network 36

A Portable Ultra-low-cost Multi-Gas Sensing System-on-Module...

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36th International conference on VLSI Design (VLSID) / 22nd International conference on Embedded Systems (ES)

作者： Sharma, Anamika Divekar, Sachin Zele, Rajesh Indian Inst Technol Dept Elect Engn Bombay Maharashtra India

ISBN: (纸本)9798350346787

Air pollution is a major problem in cities around the world. It poses a serious threat to human health and the environment. A low-cost sensing infrastructure is essential for real-time monitoring of ambient air quality. We introduce an ultra-low-cost portable sensing device that can monitor multiple air pollutants like NO2, O-3 and Particulate Matter (PM). Chronic exposure to these gases causes serious health concerns. We propose to use an integrated microcontroller and a sub-1 GHz transceiver chip to significantly reduce the cost and power consumption of the sensing device. It is a portable device with a small form factor of 15 x 11 x 5 cm(3), costing less than US$ 250 and consuming approx 100 mW of power. The sensing devices equipped with wireless networking capabilities can form a dense network and assist in examining the toxicity of air.

关键词： Air pollution air quality monitoring portable multi-gas sensing ultra-low-cost wireless sensor network

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multi-RF chip module through FOWLP 26

Multi-RF chip module through FOWLP

引用

26th Electronics Packaging Technology conference, EPTC 2024

作者： Boon, Serine Soh Siew Wee, David Ho Soon Yee, Chia Lai Jaafar, Norhanani Soh, Jacob Yao, Hsiao Hsiang Shan, Sharon Lim Pei Feng, Xu Kuan, Ong Poh Teck, Chan Kien 2 Fusionopolis Way Innovis #08-02 Singapore138634 Singapore MEDs Technologies Pte Ltd Singapore

ISBN: (纸本)9798331522001

This paper depicts the development of multiple Pseudomorphic high electron mobility transistor (pHEMT) semiconductors with AlGaAs/InGaAs/GaAs developed to realize high power and high-efficiency amplifiers for System-in-Package (SiP) modules. The developed Fan-out package measures 5.27mm X 7.15 mm X 0.15mm, based on the electrical simulation has anticipated gain of approximately 3-4dB, with power consumption © 2024 ieee.

关键词： System-in-package

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SAC: Sharing-Aware Caching in multi-chip GPUs 23

SAC: Sharing-Aware Caching in Multi-Chip GPUs

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50th Annual International Symposium on Computer Architecture (ISCA)

作者： Zhang, Shiqing Naderan-Tahan, Mahmood Jahre, Magnus Eeckhout, Lieven Univ Ghent Ghent Belgium Norwegian Univ Sci & Technol NTNU Trondheim Norway

ISBN: (纸本)9798400700958

Bandwidth non-uniformity in multi-chip GPUs poses a major design challenge for its last-level cache (LLC) architecture. Whereas a memory-side LLC caches data from the local memory partition while being accessible by all chips, an SM-side LLC is private to a chip while caching data from all memory partitions. We find that some workloads prefer a memory-side LLC while others prefer an SM-side LLC, and this preference solely depends on which organization maximizes the effective LLC bandwidth. In contrast to prior work which optimizes bandwidth beyond the LLC, we make the observation that the effective bandwidth ahead of the LLC is critical to end-to-end application performance. We propose Sharing-Aware Caching (SAC) to adopt either a memory-side or SM-side LLC organization by dynamically reconfiguring the routing policies in the intra-chip interconnection network and LLC controllers. SAC is driven by a simple and lightweight analytical model that predicts the impact of data sharing across chips on the effective LLC bandwidth. SAC improves average performance by 76% and 12% (and up to 157% and 49%) compared to a memory-side and SM-side LLC, respectively. We demonstrate significant performance improvements across the design space and across workloads.

关键词： multi-socket GPU multi-chip-module (MCM) GPU Network-onchip (NoC) data sharing cache organization

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Analysis and Mitigation of Short Circuit Current in multichip Power module with Paralleled SiC MOSFETs 3

Analysis and Mitigation of Short Circuit Current in Multichi...

引用

3rd ieee International Power Electronics and Application conference and Exposition, PEAC 2022

作者： Zhang, Man Li, Helong Han, Lianglaing Zhao, Shuang Ding, Lijian Hefei University of Technology School of Electrical Engineering and Automation Hefei China

ISBN: (数字)9781665491419

ISBN: (纸本)9781665491419

In this paper, a new substrate layout is proposed in order to mitigate the short-circuit current imbalance of a typical multi-chip power module with paralleled SiC MOSFETs. Compared with the typical SiC power modules, the influence of common-source inductance mismatch on the current imbalance is effectively minimized in the proposed layout. Consequently, the current sharing performance of the paralleled SiC MOSFETs in the multi-chip power module is improved. The analyses are verified by simulation and experimental results, which further validate the effectiveness of this mitigating method. © 2022 ieee.

关键词： Silicon carbide

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A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical Driver and chip-to-module Long Reach Capability of 40dB in 5nm FinFET 72

A 212Gb/s PAM-4 Retimer with Integrated High-Swing Optical D...

引用

72nd ieee International Solid-State Circuits conference, ISSCC 2025

作者： Gurumoorthy, V. Tan, A. Iyer, A. Fan, A. Farhoodfar, A. Alnabulsi, B. Helal, B. Abidin, C. Loi, C. Cartina, D. Lo, H. Fabiano, I. Riani, J. Teo, J.H. Wang, J.Q. Raviprakash, K. Ravi Prakash, K.K. Cai, L. Patra, L. Bachu, M. Codega, N. Shivashankar, N. Ray, S. Chong, S. Jafarlou, S. Yu, S. Wu, T.-F. Neo, W.Y. Ding, X. Wang, Y. Yan, Z. Sun, Z. Jantzi, S. Tse, L. Chang, K. Marvell Santa ClaraCA United States Marvell IrvineCA United States Marvell Ottawa Canada Marvell Singapore Singapore Marvell Burnaby Canada Marvell Pavia Italy

ISBN: (纸本)9798331541019

An increasing need for higher throughput driven by artificial intelligence (AI) and machine learning (ML) applications, makes faster l/O interfaces with lower power consumption essential. Top-of-rack switches in hyperscalers now require data rates of 200Gb/s per lambda while adhering to the power budget dictated by multi-source agreements (MSA) such as OSFP-XD. Eliminating extra components like an external laser driver is crucial as it not only reduces power consumption but also minimizes development cost and form factor. Additionally, a key challenge is the chip-to-module (C2M) interface, which is expected to drive long electrical interconnects in GPU-based racks. To address these challenges, this work presents a 4-lane 212.5Gb/s/lane retimer for optical direct detect applications with an integrated high-swing laser driver on the line transmitter (TX) and the ability to equalize 40dB channel loss on the C2M interface. © 2025 ieee.

关键词： Budget control

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Design and Development of a Low Phase Noise multi-Output Millimeter-Wave Frequency Synthesizer with High Output Power 22

Design and Development of a Low Phase Noise Multi-Output Mil...

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ieee 22nd Annual Wireless and Microwave Technology conference (WAMICON)

作者： Bhattacharyya, Shrija Tolani, Harshita Bhattacharya, Anamiya Shaik, Latheef A. Bhadoria, Mahendra P. S. Chakraborty, Prantik Rao, Ch. V. N. Jyoti, Rajeev Space Applicat Ctr Microwave Remote Sensors Area Ahmadabad Gujarat India

ISBN: (纸本)9781665421959

This paper describes the design and realization of a compact, low phase noise, multi-output millimeter-wave frequency synthesizer (FS) using a combination of fractional-N Phase Locked Loop (PLL) and direct frequency synthesis for the generation of tunable local oscillator (LO) signals centered at 37.56GHz and 5.07GHz. Input reference for coherent signal generation is derived from a highly stable Temperature Compensated Crystal Oscillator (TCXO). High power GaAs Monolithic Microwave Integrated Circuits (MMICs) accommodated within a compact multi-chip Drop-in module (DIM) provide 1.2W CW output at 37.56GHz with proper thermal management to mitigate localized heat dissipation. Measured results demonstrate output power of +30.8dBm at 37.56GHz with phase noise of -78.36dBc/Hz at 1KHz offset and +14.3dBm at 5.07GHz with phase noise of -89.68dBc/Hz at 1KHz offset and close-to-carrier spurious below 60dBc.

关键词： Ka-band loop filter MMIC multi-chip module output power PLL phase noise spurious

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