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chiplets Integrated Solution with FO-EB Package in HPC and Networking Application 72

Chiplets Integrated Solution with FO-EB Package in HPC and N...

引用

72nd ieee Electronic Components and Technology conference (ECTC)

作者： Su, Po Yuan (James) Ho, David Pu, Jacy Wang, Yu Po Siliconware Precis Ind Co Ltd SPIL 123Sec 3Chung Shan Rd Taichung Taiwan

ISBN: (纸本)9781665479431

Since its introduction in the 1960s, high performance computing (HPC) has made enormous contribution to scientific, engineering and industrial competitiveness as well as other goverment missions. High data rate with high speed transmission has been required for networking and high performance computing application, the chip size and package design has been become larger and larger. Accompanied by the big size design with package, the physical limits has the high cost for the advanced silicon node. The demand for higher functionality devices drives integration technologies to overcome limitations in Moore's Law. Heterogeneous integration is the one of technologies to meet high performance computing application standards using high bandwidth and Input/Output (I/O) density. The split die of integration in package is the best solution to increase gross die with wafer good yield rate for cost efficiency, and Fan-out Embedded Bridge (FO-EB) Package would be the best representative for HPC and Networking application. The FO-EB is meaning spilt dies with embedded bridge die in fan out package which Inter Connect Die (ICD) become silicon bridge die to do the communications for high electrical performance purpose. Comparing with 2.5D package and FO-MCM package, FO-EB package warpage not only close with 2.5D package, but also better than FO-MCM (Fan-out multi chip module) package. Besides, the electrical performance for high bandwidth memory as good as 2.5D package and FO-MCM package. The FO-EB package has integrated silicon ICD which means provide interconnections between spilt dies with short distance and the package model is more flexable than 2.5D package. That is why FO-EB would be the better choice for HPC and Networking application. The reason we choose FO-EB because it can contribute the same electrical performance to 2.5D package with FO-MCM package and the package warpgae well to be controlled. In this paper, we like to discuss a designed to evaluate the FO-EB and do

关键词： High Performance Computing (HPC) Input/Output (I/O) Fan-out Embedded Bridge (FO-EB) Fan-out multi chip module (FO-MCM) Inter Connect Die (ICD)

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A multi-chip-module-Based Architecture Simulator for Scaling Vision Transformer Inference

A Multi-Chip-Module-Based Architecture Simulator for Scaling...

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ieee International conference on Consumer Electronics (ICCE)

作者： Jicheon Kim System LSI Business Samsung Electronics Hwaseong Korea

ISBN: (数字)9798331521165

ISBN: (纸本)9798331521172

Vision transformers (ViTs) have achieved remarkable performance in various computer vision tasks. However, they demand significant computational and memory bandwidth, making them difficult to efficiently run on a monolithic accelerator, particularly in edge computing environments. A multi-chip module (MCM)-based architecture, which incorporates multiple accelerator modules with a chip-to-chip (C2C) interface, offers a promising solution for scaling and accelerating ViTs. Unfortunately, estimating the performance of an MCM system for ViT inference is challenging, as existing ViT acceleration simulators primarily target monolithic designs without considering C2C communication. To address this shortcoming, this paper proposes an MCM-based architecture simulator to estimate the impact of C2C bandwidth and the number of chips on latency and energy efficiency when scaling ViT inference. The experimental results show that increasing the number of chips and reducing C2C bandwidth can significantly affect performance due to C2C communication overhead. The framework helps identify optimal design configurations, balancing trade-offs within given constraints.

关键词： Computer vision Memory management Bandwidth Transformers Energy efficiency Computational efficiency Consumer electronics Edge computing

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AICAS 2023 - ieee International conference on Artificial Intelligence Circuits and Systems, Proceeding

AICAS 2023 - IEEE International Conference on Artificial Int...

引用

5th ieee International conference on Artificial Intelligence Circuits and Systems, AICAS 2023

ISBN: (纸本)9798350332674

The proceedings contain 119 papers. The topics discussed include: a fully differential 4-bit analog compute-in-memory architecture for inference application;memory-immersed collaborative digitization for area-efficient compute-in-memory deep learning;optimization strategies for digital compute-in-memory from comparative analysis with systolic array;a systolic computing-in-memory array based accelerator with predictive early activation for spatiotemporal convolutions;securing decision tree inference using order-preserving cryptography;binary is all you need: ultra-efficient arrhythmia detection with a binary-only compressive system;a convolved self-attention model for imu-based gait detection and human activity recognition;bandit-supported care planning for older people with complex health and care needs;a convolutional spiking network for gesture recognition in brain-computer interfaces;deep learning compiler optimization on multi-chiplet architecture;integrated system-on-module for design-space exploration of spiking neural networks;neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks;unsupervised learning of spike-timing-dependent plasticity based on a neuromorphic implementation;and an interpretable pixel intensity reconstruction model for asynchronous event camera.

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Design and Test of Beidou RF module Based on JT110 7

Design and Test of Beidou RF Module Based on JT110

引用

7th International conference on Intelligent Computing and Signal Processing, ICSP 2022

作者： Wang, Li Jia, Meng Liu, Jinxiang Dalian Neusoft University of Information Department of Microelectronics Science and Engineering Dalian China

ISBN: (纸本)9781665478571

This paper mainly introduces the RF module composed of JT110 and 89C51. JT110 is a highly integrated RNSS multi frequency point dual-mode RF receiver, which supports two channels to work independently at the same time;As the main control chip of the control circuit, 89C51 completes the function of the control circuit through SPI control circuit and programming. The designed circuits including: RF input circuit, clock reference circuit, power supply circuit and so on. In the software part, the PADs is selected to design the circuit schematic diagram and draw the PCB layout, and the test instrument is used to test the phase noise, noise coefficient, input standing wave and other parameters. © 2022 ieee.

关键词： Schematic diagrams

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Effect of power module layer thickness on reliability 5

Effect of power module layer thickness on reliability

引用

5th ieee International Electrical and Energy conference, CIEEC 2022

作者： Zhao, Yao Liu, Zheng Wang, Zhiqiang Li, Guofeng Ji, Bing Dalian University of Technology School of Electrical Engineering Dalian China University of Leicester Department of Engineering LeicesterLEI 7RH United Kingdom

ISBN: (数字)9781665411042

ISBN: (纸本)9781665411042

With the rapid development and wide application of power modules, the requirements for their reliability are also increasing. Power modules are generally multi-layer structures, and it is critical to understand the impact of the thickness of each layer of a power module on its reliability. Taking IGBT power module as an example, this paper quantifies the reliability of power module through power cycle lifetime model and thermal cycle lifetime model, and uses finite element model to calculate the key parameters of reliability model. Then, the influence of each layer thickness on the reliability of power module is compared through global sensitivity analysis. In order to reduce the amount of calculation of sensitivity analysis, an active learning surrogate model is introduced to map the thickness of each layer into the reliability index of power module. Finally, the effects of common packaging materials such as solder, ceramic, and baseplate on the performance of the power module are compared. The sensitivity analysis results show that the thickness of chip solder layer, the thickness of copper layer on direct bonded copper (DBC) and the thickness of ceramic layer are the key factors affecting the power cycle lifetime of power modules, while the thickness of DBC ceramic layer and baseplate solder layer are the key factors affecting the thermal cycle lifetime of power modules. © 2022 ieee.

关键词： Junction temperature

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PowerSynth-Guided Reliability Optimization of multi-chip Power module 36

PowerSynth-Guided Reliability Optimization of Multi-Chip Pow...

引用

26th Annual ieee Applied Power Electronics conference and Exposition (APEC)

作者： Al Razi, Imam Huitink, David R. Peng, Yarui Univ Arkansas Comp Sci & Comp Engn Dept Fayetteville AR 72701 USA Univ Arkansas Mech Engn Dept Fayetteville AR 72701 USA

ISBN: (纸本)9781728189499

High-performance multi-chip Power modules (MCPMs) are essential for high-density and efficient power conversion. Meanwhile, the chip layout and design methodology fundamentally determine thermal and reliability performance. Hign-density power modules typically consist of wide-bandgap (WBG) semiconductor die, soldering materials, baseplate, and heatsink packed on a single substrate. To a great extent, the reliability of power modules depends on these material electro-thermal-mechanical properties during variable operating conditions. Appropriate thermal management can reduce stress and enhance the component lifetime by controlling junction temperature. In this work, a fast, generic, and scalable transient thermal model has been developed for the PowerSynth layout synthesis tool to optimize layer material, thickness, and layer stack configurations by minimizing thermal stress due to thermal cycling. This model has shown approximately 3,489 times speed up with less than 10% mismatch compared to ANSYS simulation. A PowerSynth-guided design-for-reliability computer-aided design (CAD) flow is presented to optimize both the layer stack and the layout simultaneously.

关键词： PowerSynth Transient Thermal Model multi-chip Power module Reliability Optimization Phase Change Material

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High Density multi-chip module for Photonic Reservoir Computing 71

High Density Multi-Chip Module for Photonic Reservoir Comput...

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ieee 71st Electronic Components and Technology conference (ECTC)

作者： Heroux, Jean Benoit Yamane, Toshiyuki Numata, Hidetoshi Nakano, Daiju IBM Res Tokyo Kawasaki Kanagawa Japan

ISBN: (纸本)9780738145235

Simulation and experimental results of a time-delay photonic reservoir computer based on VCSEL and photodiode chips with multi-mode waveguide splitter and combiner is presented. The design is based on technology developed for a high bandwidth density optical mulit-chip module with polymer waveguides for optical interconnect applications. The number of virtual nodes in the reservoir can be adjusted by varying the feedback delay lime and the input signal rate. Results on distorted signal recovery and non-linear waveform generation tasks are presented and are promising for the development of a platform for board-integrated photonic neural network architecture.

关键词： Vertical Cavity Surface Emitting Laser Optoelectronic Device Neural Network Hardware Analog Circuit Reservoir Computing

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A multi-terminal Silicon Carbide Power module with Low Parasitic Inductance

A Multi-terminal Silicon Carbide Power Module with Low Paras...

引用

International conference on Power Electronics and Motion Control (IPEMC)

作者： Daoyong Jia Xi Jiang Ying Wang Nianlong Ma Renze Ouyang Song Yuan Xiaowu Gong The Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Materials and Devices School of Microelectronics Xidian University Xi’an China Guangzhou Institute of Technology Xidian University Guangzhou China Shenzhen Smartchip Microelectronics Technology Company Ltd. Shenzhen China

ISBN: (数字)9798350351330

ISBN: (纸本)9798350351347

Parasitic inductance reduction in the SiC power module is a crucial aspect in power module design, which can help to decrease energy losses and improve the module’s efficiency. This paper proposes an innovative layout for 1200V SiC MOSFET half-bridge power module to lower the parasitic inductance within the power loop and the thermal resistance. Through an extensive evaluation of how upper and lower bridge chip distances affect parasitic inductance and thermal resistance, an optimal chip spacing is selected. Following double pulse experimental test, the fabricated module is benchmarked against a same current rating commercial 1200V SiC MOSFET half-bridge module, exhibits superior switching performance.

关键词： Bridges Inductance MOSFET Interference cancellation Power measurement Silicon carbide Thermal resistance

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Research on Influencing Factors of chip Dynamic Current Distribution in IGBT module

Research on Influencing Factors of Chip Dynamic Current Dist...

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Sustainable Power and Energy conference (iSPEC)

作者： Cui Meiting Chen Zhongyuan Li Hongji Beijing Institute of Smart Energy Chang Ping District Beijing

IGBT (Insulated-gate bipolar transistor) modules are generally composed of multiple chips in parallel. Due to the difference of chip parameters and package parasitic parameters, the current distribution of each chip is not completely consistent. The dynamic current dispersion of the chip is the result of coupling of multiple parameters in multiple stages of the switching process. The analysis of the factors that affect the internal dynamic current distribution, the influence mechanism and degree of each factor has a good reference significance for safe and reliable operation of IGBT module. Firstly, the multi-chip paralleled IGBT module model and test circuit model including internal parasitic parameters are introduced in this paper. Then, the factors affecting the unbalanced distribution of dynamic current in different switching periods are analyzed. Finally, a double-pulse simulation circuit is built to study the influence of each factor on the collector current by controlling a single variable, and the sensitivity of each factor to the dynamic current distribution is determined. The conclusion of this paper can provide reference for the parameter design and optimization of IGBT module in parallel package, which further promote the stable and reliable operation of the power system.

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Embedded mm-Wave chiplet Based module using Fused-Silica Stitch-chip Technology: RF Characterization and Thermal Evaluation

Embedded mm-Wave Chiplet Based Module using Fused-Silica Sti...

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Electronic Components and Technology conference (ECTC)

作者： Ting Zheng Madison Manley Muhannad Bakir Sch. Electr. Comp. Eng. Georgia Institute of Technology Atlanta GA

A fused-silica stitch-chip technology for an embed-ded low noise amplifier (LNA) module is demonstrated for the first time. In this article, the package substrate and assembly are reported and RF/mm-wave characterization of the LNA module is performed. A <2.5 dB package loss is measured within the LNA bandwidth (24–40 GHz), translating to a <1.4 dB package interconnect loss. In addition, thermal simulations are implemented for the LNA module to investigate the thermal impact of critical package components when a high power-density chiplet is packaged. The stitch-chip technology features broadband low-loss interconnects and enables the scalability of chiplet-based integration; this represents a promising solution for future mm-wave multi-chiplet based modules.

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